arch/arm/mach-omap2/clock.h

   1 /*
   2  *  linux/arch/arm/mach-omap24xx/clock.h
   3  *
   4  *  Copyright (C) 2005 Texas Instruments Inc.
   5  *  Richard Woodruff <r-woodruff2@ti.com>
   6  *  Created for OMAP2.
   7  *
   8  *  Copyright (C) 2004 Nokia corporation
   9  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  10  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
  18 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
  19
  20 #include "prm.h"
  21 #include "cm.h"
  22 #include "prm_regbits_24xx.h"
  23 #include "cm_regbits_24xx.h"
  24
  25 static void omap2_sys_clk_recalc(struct clk * clk);
  26 static void omap2_clksel_recalc(struct clk * clk);
  27 static void omap2_followparent_recalc(struct clk * clk);
  28 static void omap2_propagate_rate(struct clk * clk);
  29 static void omap2_mpu_recalc(struct clk * clk);
  30 static int omap2_select_table_rate(struct clk * clk, unsigned long rate);
  31 static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate);
  32 static void omap2_clk_disable(struct clk *clk);
  33 static void omap2_sys_clk_recalc(struct clk * clk);
  34 static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val);
  35 static u32 omap2_clksel_get_divisor(struct clk *clk);
  36
  37 /* REVISIT: should use a clock flag for this, not a magic number */
  38 #define PARENT_CONTROLS_CLOCK   0xff
  39
  40 #define RATE_IN_242X    (1 << 0)
  41 #define RATE_IN_243X    (1 << 1)
  42
  43 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  44  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  45  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  46  */
  47 struct prcm_config {
  48         unsigned long xtal_speed;       /* crystal rate */
  49         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  50         unsigned long mpu_speed;        /* speed of MPU */
  51         unsigned long cm_clksel_mpu;    /* mpu divider */
  52         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  53         unsigned long cm_clksel_gfx;    /* gfx dividers */
  54         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  55         unsigned long cm_clksel1_pll;   /* m,n */
  56         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  57         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  58         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  59         unsigned char flags;
  60 };
  61
  62 /* Mask for clksel which support parent settign in set_rate */
  63 #define SRC_SEL_MASK (CM_CORE_SEL1 | CM_CORE_SEL2 | CM_WKUP_SEL1 | \
  64                         CM_PLL_SEL1 | CM_PLL_SEL2 | CM_SYSCLKOUT_SEL1)
  65
  66 /* Mask for clksel regs which support rate operations */
  67 #define SRC_RATE_SEL_MASK (CM_MPU_SEL1 | CM_DSP_SEL1 | CM_GFX_SEL1 | \
  68                         CM_MODEM_SEL1 | CM_CORE_SEL1 | CM_CORE_SEL2 | \
  69                         CM_WKUP_SEL1 | CM_PLL_SEL1 | CM_PLL_SEL2 | \
  70                         CM_SYSCLKOUT_SEL1)
  71
  72 /*
  73  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  74  * These configurations are characterized by voltage and speed for clocks.
  75  * The device is only validated for certain combinations. One way to express
  76  * these combinations is via the 'ratio's' which the clocks operate with
  77  * respect to each other. These ratio sets are for a given voltage/DPLL
  78  * setting. All configurations can be described by a DPLL setting and a ratio
  79  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  80  *
  81  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  82  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  83  * 2430 (iva2.1, NOdsp, mdm)
  84  */
  85
  86 /* Core fields for cm_clksel, not ratio governed */
  87 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  88 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  89 #define RX_CLKSEL_SSI                   (0x5 << 20)
  90
  91 /*-------------------------------------------------------------------------
  92  * Voltage/DPLL ratios
  93  *-------------------------------------------------------------------------*/
  94
  95 /* 2430 Ratio's, 2430-Ratio Config 1 */
  96 #define R1_CLKSEL_L3                    (4 << 0)
  97 #define R1_CLKSEL_L4                    (2 << 5)
  98 #define R1_CLKSEL_USB                   (4 << 25)
  99 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
 100                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 101                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
 102 #define R1_CLKSEL_MPU                   (2 << 0)
 103 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
 104 #define R1_CLKSEL_DSP                   (2 << 0)
 105 #define R1_CLKSEL_DSP_IF                (2 << 5)
 106 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
 107 #define R1_CLKSEL_GFX                   (2 << 0)
 108 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
 109 #define R1_CLKSEL_MDM                   (4 << 0)
 110 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
 111
 112 /* 2430-Ratio Config 2 */
 113 #define R2_CLKSEL_L3                    (6 << 0)
 114 #define R2_CLKSEL_L4                    (2 << 5)
 115 #define R2_CLKSEL_USB                   (2 << 25)
 116 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
 117                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 118                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
 119 #define R2_CLKSEL_MPU                   (2 << 0)
 120 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 121 #define R2_CLKSEL_DSP                   (2 << 0)
 122 #define R2_CLKSEL_DSP_IF                (3 << 5)
 123 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 124 #define R2_CLKSEL_GFX                   (2 << 0)
 125 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 126 #define R2_CLKSEL_MDM                   (6 << 0)
 127 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 128
 129 /* 2430-Ratio Bootm (BYPASS) */
 130 #define RB_CLKSEL_L3                    (1 << 0)
 131 #define RB_CLKSEL_L4                    (1 << 5)
 132 #define RB_CLKSEL_USB                   (1 << 25)
 133 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 134                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 135                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 136 #define RB_CLKSEL_MPU                   (1 << 0)
 137 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 138 #define RB_CLKSEL_DSP                   (1 << 0)
 139 #define RB_CLKSEL_DSP_IF                (1 << 5)
 140 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 141 #define RB_CLKSEL_GFX                   (1 << 0)
 142 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 143 #define RB_CLKSEL_MDM                   (1 << 0)
 144 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 145
 146 /* 2420 Ratio Equivalents */
 147 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 148 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 149
 150 /* 2420-PRCM III 532MHz core */
 151 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 152 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 153 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 154 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 155                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 156                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 157                                         RIII_CLKSEL_L3
 158 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 159 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 160 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 161 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 162 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 163 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 164 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 165 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 166                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 167                                         RIII_CLKSEL_DSP
 168 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 169 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 170
 171 /* 2420-PRCM II 600MHz core */
 172 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 173 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 174 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 175 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 176                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 177                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 178                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 179 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 180 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 181 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 182 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 183 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 184 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 185 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 186 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 187                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 188                                         RII_CLKSEL_DSP
 189 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 190 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 191
 192 /* 2420-PRCM I 660MHz core */
 193 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 194 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 195 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 196 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 197                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 198                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 199                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 200 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 201 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 202 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 203 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 204 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 205 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 206 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 207 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 208                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 209                                         RI_CLKSEL_DSP
 210 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 211 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 212
 213 /* 2420-PRCM VII (boot) */
 214 #define RVII_CLKSEL_L3                  (1 << 0)
 215 #define RVII_CLKSEL_L4                  (1 << 5)
 216 #define RVII_CLKSEL_DSS1                (1 << 8)
 217 #define RVII_CLKSEL_DSS2                (0 << 13)
 218 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 219 #define RVII_CLKSEL_SSI                 (1 << 20)
 220 #define RVII_CLKSEL_USB                 (1 << 25)
 221
 222 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 223                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 224                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 225
 226 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 227 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 228
 229 #define RVII_CLKSEL_DSP                 (1 << 0)
 230 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 231 #define RVII_SYNC_DSP                   (0 << 7)
 232 #define RVII_CLKSEL_IVA                 (1 << 8)
 233 #define RVII_SYNC_IVA                   (0 << 13)
 234 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 235                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 236
 237 #define RVII_CLKSEL_GFX                 (1 << 0)
 238 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 239
 240 /*-------------------------------------------------------------------------
 241  * 2430 Target modes: Along with each configuration the CPU has several
 242  * modes which goes along with them. Modes mainly are the addition of
 243  * describe DPLL combinations to go along with a ratio.
 244  *-------------------------------------------------------------------------*/
 245
 246 /* Hardware governed */
 247 #define MX_48M_SRC                      (0 << 3)
 248 #define MX_54M_SRC                      (0 << 5)
 249 #define MX_APLLS_CLIKIN_12              (3 << 23)
 250 #define MX_APLLS_CLIKIN_13              (2 << 23)
 251 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 252
 253 /*
 254  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 255  * #2   (ratio1) baseport-target
 256  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 257  */
 258 #define M5A_DPLL_MULT_12                (133 << 12)
 259 #define M5A_DPLL_DIV_12                 (5 << 8)
 260 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 261                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 262                                         MX_APLLS_CLIKIN_12
 263 #define M5A_DPLL_MULT_13                (266 << 12)
 264 #define M5A_DPLL_DIV_13                 (12 << 8)
 265 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 266                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 267                                         MX_APLLS_CLIKIN_13
 268 #define M5A_DPLL_MULT_19                (180 << 12)
 269 #define M5A_DPLL_DIV_19                 (12 << 8)
 270 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 271                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 272                                         MX_APLLS_CLIKIN_19_2
 273 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 274 #define M5B_DPLL_MULT_12                (50 << 12)
 275 #define M5B_DPLL_DIV_12                 (2 << 8)
 276 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 277                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 278                                         MX_APLLS_CLIKIN_12
 279 #define M5B_DPLL_MULT_13                (200 << 12)
 280 #define M5B_DPLL_DIV_13                 (12 << 8)
 281
 282 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 283                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 284                                         MX_APLLS_CLIKIN_13
 285 #define M5B_DPLL_MULT_19                (125 << 12)
 286 #define M5B_DPLL_DIV_19                 (31 << 8)
 287 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 288                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 289                                         MX_APLLS_CLIKIN_19_2
 290 /*
 291  * #4   (ratio2)
 292  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 293  */
 294 #define M3_DPLL_MULT_12                 (55 << 12)
 295 #define M3_DPLL_DIV_12                  (1 << 8)
 296 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 297                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 298                                         MX_APLLS_CLIKIN_12
 299 #define M3_DPLL_MULT_13                 (330 << 12)
 300 #define M3_DPLL_DIV_13                  (12 << 8)
 301 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 302                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 303                                         MX_APLLS_CLIKIN_13
 304 #define M3_DPLL_MULT_19                 (275 << 12)
 305 #define M3_DPLL_DIV_19                  (15 << 8)
 306 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 307                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 308                                         MX_APLLS_CLIKIN_19_2
 309 /* boot (boot) */
 310 #define MB_DPLL_MULT                    (1 << 12)
 311 #define MB_DPLL_DIV                     (0 << 8)
 312 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 313                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 314
 315 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 316                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 317
 318 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 319                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 320
 321 /*
 322  * 2430 - chassis (sedna)
 323  * 165 (ratio1) same as above #2
 324  * 150 (ratio1)
 325  * 133 (ratio2) same as above #4
 326  * 110 (ratio2) same as above #3
 327  * 104 (ratio2)
 328  * boot (boot)
 329  */
 330
 331 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 332 #define MI_DPLL_MULT_12                 (55 << 12)
 333 #define MI_DPLL_DIV_12                  (1 << 8)
 334 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 335                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 336                                         MX_APLLS_CLIKIN_12
 337
 338 /*
 339  * 2420 Equivalent - mode registers
 340  * PRCM II , target DPLL = 2*300MHz = 600MHz
 341  */
 342 #define MII_DPLL_MULT_12                (50 << 12)
 343 #define MII_DPLL_DIV_12                 (1 << 8)
 344 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 345                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 346                                         MX_APLLS_CLIKIN_12
 347 #define MII_DPLL_MULT_13                (300 << 12)
 348 #define MII_DPLL_DIV_13                 (12 << 8)
 349 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 350                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 351                                         MX_APLLS_CLIKIN_13
 352
 353 /* PRCM III target DPLL = 2*266 = 532MHz*/
 354 #define MIII_DPLL_MULT_12               (133 << 12)
 355 #define MIII_DPLL_DIV_12                (5 << 8)
 356 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 357                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 358                                         MX_APLLS_CLIKIN_12
 359 #define MIII_DPLL_MULT_13               (266 << 12)
 360 #define MIII_DPLL_DIV_13                (12 << 8)
 361 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 362                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 363                                         MX_APLLS_CLIKIN_13
 364
 365 /* PRCM VII (boot bypass) */
 366 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 367 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 368
 369 /* High and low operation value */
 370 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 371 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 372
 373 /*
 374  * These represent optimal values for common parts, it won't work for all.
 375  * As long as you scale down, most parameters are still work, they just
 376  * become sub-optimal. The RFR value goes in the opposite direction. If you
 377  * don't adjust it down as your clock period increases the refresh interval
 378  * will not be met. Setting all parameters for complete worst case may work,
 379  * but may cut memory performance by 2x. Due to errata the DLLs need to be
 380  * unlocked and their value needs run time calibration. A dynamic call is
 381  * need for that as no single right value exists acorss production samples.
 382  *
 383  * Only the FULL speed values are given. Current code is such that rate
 384  * changes must be made at DPLLoutx2. The actual value adjustment for low
 385  * frequency operation will be handled by omap_set_performance()
 386  *
 387  * By having the boot loader boot up in the fastest L4 speed available likely
 388  * will result in something which you can switch between.
 389  */
 390 #define V24XX_SDRC_RFR_CTRL_165MHz      (0x00044c00 | 1)
 391 #define V24XX_SDRC_RFR_CTRL_133MHz      (0x0003de00 | 1)
 392 #define V24XX_SDRC_RFR_CTRL_100MHz      (0x0002da01 | 1)
 393 #define V24XX_SDRC_RFR_CTRL_110MHz      (0x0002da01 | 1) /* Need to calc */
 394 #define V24XX_SDRC_RFR_CTRL_BYPASS      (0x00005000 | 1) /* Need to calc */
 395
 396 /* MPU speed defines */
 397 #define S12M    12000000
 398 #define S13M    13000000
 399 #define S19M    19200000
 400 #define S26M    26000000
 401 #define S100M   100000000
 402 #define S133M   133000000
 403 #define S150M   150000000
 404 #define S165M   165000000
 405 #define S200M   200000000
 406 #define S266M   266000000
 407 #define S300M   300000000
 408 #define S330M   330000000
 409 #define S400M   400000000
 410 #define S532M   532000000
 411 #define S600M   600000000
 412 #define S660M   660000000
 413
 414 /*-------------------------------------------------------------------------
 415  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 416  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 417  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 418  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 419  *
 420  * Filling in table based on H4 boards and 2430-SDPs variants available.
 421  * There are quite a few more rates combinations which could be defined.
 422  *
 423  * When multiple values are defined the start up will try and choose the
 424  * fastest one. If a 'fast' value is defined, then automatically, the /2
 425  * one should be included as it can be used.    Generally having more that
 426  * one fast set does not make sense, as static timings need to be changed
 427  * to change the set.    The exception is the bypass setting which is
 428  * availble for low power bypass.
 429  *
 430  * Note: This table needs to be sorted, fastest to slowest.
 431  *-------------------------------------------------------------------------*/
 432 static struct prcm_config rate_table[] = {
 433         /* PRCM I - FAST */
 434         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 435                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 436                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 437                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_165MHz,
 438                 RATE_IN_242X},
 439
 440         /* PRCM II - FAST */
 441         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 442                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 443                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 444                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 445                 RATE_IN_242X},
 446
 447         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 448                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 449                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 450                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 451                 RATE_IN_242X},
 452
 453         /* PRCM III - FAST */
 454         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 455                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 456                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 457                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 458                 RATE_IN_242X},
 459
 460         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 461                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 462                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 463                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 464                 RATE_IN_242X},
 465
 466         /* PRCM II - SLOW */
 467         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 468                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 469                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 470                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 471                 RATE_IN_242X},
 472
 473         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 474                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 475                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 476                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 477                 RATE_IN_242X},
 478
 479         /* PRCM III - SLOW */
 480         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 481                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 482                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 483                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 484                 RATE_IN_242X},
 485
 486         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 487                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 488                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 489                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 490                 RATE_IN_242X},
 491
 492         /* PRCM-VII (boot-bypass) */
 493         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 494                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 495                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 496                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
 497                 RATE_IN_242X},
 498
 499         /* PRCM-VII (boot-bypass) */
 500         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 501                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 502                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 503                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
 504                 RATE_IN_242X},
 505
 506         /* PRCM #3 - ratio2 (ES2) - FAST */
 507         {S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 508                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 509                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 510                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 511                 V24XX_SDRC_RFR_CTRL_110MHz,
 512                 RATE_IN_243X},
 513
 514         /* PRCM #5a - ratio1 - FAST */
 515         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 516                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 517                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 518                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 519                 V24XX_SDRC_RFR_CTRL_133MHz,
 520                 RATE_IN_243X},
 521
 522         /* PRCM #5b - ratio1 - FAST */
 523         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 524                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 525                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 526                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 527                 V24XX_SDRC_RFR_CTRL_100MHz,
 528                 RATE_IN_243X},
 529
 530         /* PRCM #3 - ratio2 (ES2) - SLOW */
 531         {S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 532                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 533                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 534                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 535                 V24XX_SDRC_RFR_CTRL_110MHz,
 536                 RATE_IN_243X},
 537
 538         /* PRCM #5a - ratio1 - SLOW */
 539         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 540                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 541                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 542                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 543                 V24XX_SDRC_RFR_CTRL_133MHz,
 544                 RATE_IN_243X},
 545
 546         /* PRCM #5b - ratio1 - SLOW*/
 547         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 548                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 549                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 550                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 551                 V24XX_SDRC_RFR_CTRL_100MHz,
 552                 RATE_IN_243X},
 553
 554         /* PRCM-boot/bypass */
 555         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 556                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 557                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 558                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 559                 V24XX_SDRC_RFR_CTRL_BYPASS,
 560                 RATE_IN_243X},
 561
 562         /* PRCM-boot/bypass */
 563         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 564                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 565                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 566                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 567                 V24XX_SDRC_RFR_CTRL_BYPASS,
 568                 RATE_IN_243X},
 569
 570         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 571 };
 572
 573 /*-------------------------------------------------------------------------
 574  * 24xx clock tree.
 575  *
 576  * NOTE:In many cases here we are assigning a 'default' parent. In many
 577  *      cases the parent is selectable. The get/set parent calls will also
 578  *      switch sources.
 579  *
 580  *      Many some clocks say always_enabled, but they can be auto idled for
 581  *      power savings. They will always be available upon clock request.
 582  *
 583  *      Several sources are given initial rates which may be wrong, this will
 584  *      be fixed up in the init func.
 585  *
 586  *      Things are broadly separated below by clock domains. It is
 587  *      noteworthy that most periferals have dependencies on multiple clock
 588  *      domains. Many get their interface clocks from the L4 domain, but get
 589  *      functional clocks from fixed sources or other core domain derived
 590  *      clocks.
 591  *-------------------------------------------------------------------------*/
 592
 593 /* Base external input clocks */
 594 static struct clk func_32k_ck = {
 595         .name           = "func_32k_ck",
 596         .rate           = 32000,
 597         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 598                                 RATE_FIXED | ALWAYS_ENABLED,
 599 };
 600
 601 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 602 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 603         .name           = "osc_ck",
 604         .rate           = 26000000,             /* fixed up in clock init */
 605         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 606                                 RATE_FIXED | RATE_PROPAGATES,
 607 };
 608
 609 /* With out modem likely 12MHz, with modem likely 13MHz */
 610 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 611         .name           = "sys_ck",             /* ~ ref_clk also */
 612         .parent         = &osc_ck,
 613         .rate           = 13000000,
 614         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 615                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 616         .rate_offset    = 6, /* sysclkdiv 1 or 2, already handled or no boot */
 617         .recalc         = &omap2_sys_clk_recalc,
 618 };
 619
 620 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 621         .name           = "alt_ck",
 622         .rate           = 54000000,
 623         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 624                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 625         .recalc         = &omap2_propagate_rate,
 626 };
 627
 628 /*
 629  * Analog domain root source clocks
 630  */
 631
 632 /* dpll_ck, is broken out in to special cases through clksel */
 633 static struct clk dpll_ck = {
 634         .name           = "dpll_ck",
 635         .parent         = &sys_ck,              /* Can be func_32k also */
 636         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 637                                 RATE_PROPAGATES | RATE_CKCTL | CM_PLL_SEL1,
 638         .recalc         = &omap2_clksel_recalc,
 639 };
 640
 641 static struct clk apll96_ck = {
 642         .name           = "apll96_ck",
 643         .parent         = &sys_ck,
 644         .rate           = 96000000,
 645         .flags          = CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X |
 646                                 RATE_FIXED | RATE_PROPAGATES,
 647         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 648         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 649         .recalc         = &omap2_propagate_rate,
 650 };
 651
 652 static struct clk apll54_ck = {
 653         .name           = "apll54_ck",
 654         .parent         = &sys_ck,
 655         .rate           = 54000000,
 656         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 657                                 RATE_FIXED | RATE_PROPAGATES,
 658         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 659         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 660         .recalc         = &omap2_propagate_rate,
 661 };
 662
 663 /*
 664  * PRCM digital base sources
 665  */
 666 static struct clk func_54m_ck = {
 667         .name           = "func_54m_ck",
 668         .parent         = &apll54_ck,   /* can also be alt_clk */
 669         .rate           = 54000000,
 670         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 671                                 RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
 672         .src_offset     = 5,
 673         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 674         .enable_bit     = PARENT_CONTROLS_CLOCK,
 675         .recalc         = &omap2_propagate_rate,
 676 };
 677
 678 static struct clk core_ck = {
 679         .name           = "core_ck",
 680         .parent         = &dpll_ck,             /* can also be 32k */
 681         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 682                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 683         .recalc         = &omap2_propagate_rate,
 684 };
 685
 686 static struct clk sleep_ck = {          /* sys_clk or 32k */
 687         .name           = "sleep_ck",
 688         .parent         = &func_32k_ck,
 689         .rate           = 32000,
 690         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 691         .recalc         = &omap2_propagate_rate,
 692 };
 693
 694 static struct clk func_96m_ck = {
 695         .name           = "func_96m_ck",
 696         .parent         = &apll96_ck,
 697         .rate           = 96000000,
 698         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 699                                 RATE_FIXED | RATE_PROPAGATES,
 700         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 701         .enable_bit     = PARENT_CONTROLS_CLOCK,
 702         .recalc         = &omap2_propagate_rate,
 703 };
 704
 705 static struct clk func_48m_ck = {
 706         .name           = "func_48m_ck",
 707         .parent         = &apll96_ck,    /* 96M or Alt */
 708         .rate           = 48000000,
 709         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 710                                 RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
 711         .src_offset     = 3,
 712         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 713         .enable_bit     = PARENT_CONTROLS_CLOCK,
 714         .recalc         = &omap2_propagate_rate,
 715 };
 716
 717 static struct clk func_12m_ck = {
 718         .name           = "func_12m_ck",
 719         .parent         = &func_48m_ck,
 720         .rate           = 12000000,
 721         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 722                                 RATE_FIXED | RATE_PROPAGATES,
 723         .recalc         = &omap2_propagate_rate,
 724         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 725         .enable_bit     = PARENT_CONTROLS_CLOCK,
 726 };
 727
 728 /* Secure timer, only available in secure mode */
 729 static struct clk wdt1_osc_ck = {
 730         .name           = "ck_wdt1_osc",
 731         .parent         = &osc_ck,
 732         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 733         .recalc         = &omap2_followparent_recalc,
 734 };
 735
 736 static struct clk sys_clkout = {
 737         .name           = "sys_clkout",
 738         .parent         = &func_54m_ck,
 739         .rate           = 54000000,
 740         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 741                                 CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
 742         .src_offset     = 0,
 743         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 744         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 745         .rate_offset    = 3,
 746         .recalc         = &omap2_clksel_recalc,
 747 };
 748
 749 /* In 2430, new in 2420 ES2 */
 750 static struct clk sys_clkout2 = {
 751         .name           = "sys_clkout2",
 752         .parent         = &func_54m_ck,
 753         .rate           = 54000000,
 754         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 755                                 CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
 756         .src_offset     = 8,
 757         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 758         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 759         .rate_offset    = 11,
 760         .recalc         = &omap2_clksel_recalc,
 761 };
 762
 763 static struct clk emul_ck = {
 764         .name           = "emul_ck",
 765         .parent         = &func_54m_ck,
 766         .flags          = CLOCK_IN_OMAP242X,
 767         .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL,
 768         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 769         .recalc         = &omap2_propagate_rate,
 770
 771 };
 772
 773 /*
 774  * MPU clock domain
 775  *      Clocks:
 776  *              MPU_FCLK, MPU_ICLK
 777  *              INT_M_FCLK, INT_M_I_CLK
 778  *
 779  * - Individual clocks are hardware managed.
 780  * - Base divider comes from: CM_CLKSEL_MPU
 781  *
 782  */
 783 static struct clk mpu_ck = {    /* Control cpu */
 784         .name           = "mpu_ck",
 785         .parent         = &core_ck,
 786         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL |
 787                                 ALWAYS_ENABLED | CM_MPU_SEL1 | DELAYED_APP |
 788                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
 789         .rate_offset    = 0,    /* bits 0-4 */
 790         .recalc         = &omap2_clksel_recalc,
 791 };
 792
 793 /*
 794  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
 795  * Clocks:
 796  *      2430: IVA2.1_FCLK, IVA2.1_ICLK
 797  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
 798  */
 799 static struct clk iva2_1_fck = {
 800         .name           = "iva2_1_fck",
 801         .parent         = &core_ck,
 802         .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
 803                                 DELAYED_APP | RATE_PROPAGATES |
 804                                 CONFIG_PARTICIPANT,
 805         .rate_offset    = 0,
 806         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 807         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
 808         .recalc         = &omap2_clksel_recalc,
 809 };
 810
 811 static struct clk iva2_1_ick = {
 812         .name           = "iva2_1_ick",
 813         .parent         = &iva2_1_fck,
 814         .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
 815                                 DELAYED_APP | CONFIG_PARTICIPANT,
 816         .rate_offset    = 5,
 817         .recalc         = &omap2_clksel_recalc,
 818 };
 819
 820 /*
 821  * Won't be too specific here. The core clock comes into this block
 822  * it is divided then tee'ed. One branch goes directly to xyz enable
 823  * controls. The other branch gets further divided by 2 then possibly
 824  * routed into a synchronizer and out of clocks abc.
 825  */
 826 static struct clk dsp_fck = {
 827         .name           = "dsp_fck",
 828         .parent         = &core_ck,
 829         .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
 830                         DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
 831         .rate_offset    = 0,
 832         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 833         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
 834         .recalc         = &omap2_clksel_recalc,
 835 };
 836
 837 static struct clk dsp_ick = {
 838         .name           = "dsp_ick",     /* apparently ipi and isp */
 839         .parent         = &dsp_fck,
 840         .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
 841                                 DELAYED_APP | CONFIG_PARTICIPANT,
 842         .rate_offset    = 5,
 843         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
 844         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,            /* for ipi */
 845         .recalc         = &omap2_clksel_recalc,
 846 };
 847
 848 static struct clk iva1_ifck = {
 849         .name           = "iva1_ifck",
 850         .parent         = &core_ck,
 851         .flags          = CLOCK_IN_OMAP242X | CM_DSP_SEL1 | RATE_CKCTL |
 852                         CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
 853         .rate_offset    = 8,
 854         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 855         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
 856         .recalc         = &omap2_clksel_recalc,
 857 };
 858
 859 /* IVA1 mpu/int/i/f clocks are /2 of parent */
 860 static struct clk iva1_mpu_int_ifck = {
 861         .name           = "iva1_mpu_int_ifck",
 862         .parent         = &iva1_ifck,
 863         .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1,
 864         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 865         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
 866         .recalc         = &omap2_clksel_recalc,
 867 };
 868
 869 /*
 870  * L3 clock domain
 871  * L3 clocks are used for both interface and functional clocks to
 872  * multiple entities. Some of these clocks are completely managed
 873  * by hardware, and some others allow software control. Hardware
 874  * managed ones general are based on directly CLK_REQ signals and
 875  * various auto idle settings. The functional spec sets many of these
 876  * as 'tie-high' for their enables.
 877  *
 878  * I-CLOCKS:
 879  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
 880  *      CAM, HS-USB.
 881  * F-CLOCK
 882  *      SSI.
 883  *
 884  * GPMC memories and SDRC have timing and clock sensitive registers which
 885  * may very well need notification when the clock changes. Currently for low
 886  * operating points, these are taken care of in sleep.S.
 887  */
 888 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
 889         .name           = "core_l3_ck",
 890         .parent         = &core_ck,
 891         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 892                                 RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
 893                                 DELAYED_APP | CONFIG_PARTICIPANT |
 894                                 RATE_PROPAGATES,
 895         .rate_offset    = 0,
 896         .recalc         = &omap2_clksel_recalc,
 897 };
 898
 899 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
 900         .name           = "usb_l4_ick",
 901         .parent         = &core_l3_ck,
 902         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 903                                 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP |
 904                                 CONFIG_PARTICIPANT,
 905         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 906         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
 907         .rate_offset    = 25,
 908         .recalc         = &omap2_clksel_recalc,
 909 };
 910
 911 /*
 912  * SSI is in L3 management domain, its direct parent is core not l3,
 913  * many core power domain entities are grouped into the L3 clock
 914  * domain.
 915  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
 916  *
 917  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
 918  */
 919 static struct clk ssi_ssr_sst_fck = {
 920         .name           = "ssi_fck",
 921         .parent         = &core_ck,
 922         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 923                                 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
 924         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),       /* bit 1 */
 925         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
 926         .rate_offset    = 20,
 927         .recalc         = &omap2_clksel_recalc,
 928 };
 929
 930 /*
 931  * GFX clock domain
 932  *      Clocks:
 933  * GFX_FCLK, GFX_ICLK
 934  * GFX_CG1(2d), GFX_CG2(3d)
 935  *
 936  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
 937  * The 2d and 3d clocks run at a hardware determined
 938  * divided value of fclk.
 939  *
 940  */
 941 static struct clk gfx_3d_fck = {
 942         .name           = "gfx_3d_fck",
 943         .parent         = &core_l3_ck,
 944         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 945                                 RATE_CKCTL | CM_GFX_SEL1,
 946         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
 947         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
 948         .rate_offset    = 0,
 949         .recalc         = &omap2_clksel_recalc,
 950 };
 951
 952 static struct clk gfx_2d_fck = {
 953         .name           = "gfx_2d_fck",
 954         .parent         = &core_l3_ck,
 955         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 956                                 RATE_CKCTL | CM_GFX_SEL1,
 957         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
 958         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
 959         .rate_offset    = 0,
 960         .recalc         = &omap2_clksel_recalc,
 961 };
 962
 963 static struct clk gfx_ick = {
 964         .name           = "gfx_ick",            /* From l3 */
 965         .parent         = &core_l3_ck,
 966         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 967                                 RATE_CKCTL,
 968         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),  /* bit 0 */
 969         .enable_bit     = OMAP_EN_GFX_SHIFT,
 970         .recalc         = &omap2_followparent_recalc,
 971 };
 972
 973 /*
 974  * Modem clock domain (2430)
 975  *      CLOCKS:
 976  *              MDM_OSC_CLK
 977  *              MDM_ICLK
 978  */
 979 static struct clk mdm_ick = {           /* used both as a ick and fck */
 980         .name           = "mdm_ick",
 981         .parent         = &core_ck,
 982         .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_MODEM_SEL1 |
 983                                 DELAYED_APP | CONFIG_PARTICIPANT,
 984         .rate_offset    = 0,
 985         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
 986         .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
 987         .recalc         = &omap2_clksel_recalc,
 988 };
 989
 990 static struct clk mdm_osc_ck = {
 991         .name           = "mdm_osc_ck",
 992         .rate           = 26000000,
 993         .parent         = &osc_ck,
 994         .flags          = CLOCK_IN_OMAP243X | RATE_FIXED,
 995         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, OMAP24XX_CM_FCLKEN),
 996         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
 997         .recalc         = &omap2_followparent_recalc,
 998 };
 999
1000 /*
1001  * L4 clock management domain
1002  *
1003  * This domain contains lots of interface clocks from the L4 interface, some
1004  * functional clocks.   Fixed APLL functional source clocks are managed in
1005  * this domain.
1006  */
1007 static struct clk l4_ck = {             /* used both as an ick and fck */
1008         .name           = "l4_ck",
1009         .parent         = &core_l3_ck,
1010         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1011                                 RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
1012                                 DELAYED_APP | RATE_PROPAGATES,
1013         .rate_offset    = 5,
1014         .recalc         = &omap2_clksel_recalc,
1015 };
1016
1017 static struct clk ssi_l4_ick = {
1018         .name           = "ssi_l4_ick",
1019         .parent         = &l4_ck,
1020         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
1021         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),        /* bit 1 */
1022         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1023         .recalc         = &omap2_followparent_recalc,
1024 };
1025
1026 /*
1027  * DSS clock domain
1028  * CLOCKs:
1029  * DSS_L4_ICLK, DSS_L3_ICLK,
1030  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1031  *
1032  * DSS is both initiator and target.
1033  */
1034 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1035         .name           = "dss_ick",
1036         .parent         = &l4_ck,       /* really both l3 and l4 */
1037         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
1038         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1039         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1040         .recalc         = &omap2_followparent_recalc,
1041 };
1042
1043 static struct clk dss1_fck = {
1044         .name           = "dss1_fck",
1045         .parent         = &core_ck,             /* Core or sys */
1046         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1047                                 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
1048         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1049         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1050         .rate_offset    = 8,
1051         .src_offset     = 8,
1052         .recalc         = &omap2_clksel_recalc,
1053 };
1054
1055 static struct clk dss2_fck = {          /* Alt clk used in power management */
1056         .name           = "dss2_fck",
1057         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1058         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1059                                 RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED |
1060                                 DELAYED_APP,
1061         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1062         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
1063         .src_offset     = 13,
1064         .recalc         = &omap2_followparent_recalc,
1065 };
1066
1067 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1068         .name           = "dss_54m_fck",        /* 54m tv clk */
1069         .parent         = &func_54m_ck,
1070         .rate           = 54000000,
1071         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1072                                 RATE_FIXED | RATE_PROPAGATES,
1073         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1074         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
1075         .recalc         = &omap2_propagate_rate,
1076 };
1077
1078 /*
1079  * CORE power domain ICLK & FCLK defines.
1080  * Many of the these can have more than one possible parent. Entries
1081  * here will likely have an L4 interface parent, and may have multiple
1082  * functional clock parents.
1083  */
1084 static struct clk gpt1_ick = {
1085         .name           = "gpt1_ick",
1086         .parent         = &l4_ck,
1087         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1088         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), /* Bit0 */
1089         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1090         .recalc         = &omap2_followparent_recalc,
1091 };
1092
1093 static struct clk gpt1_fck = {
1094         .name           = "gpt1_fck",
1095         .parent         = &func_32k_ck,
1096         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1097                                 CM_WKUP_SEL1,
1098         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),        /* Bit0 */
1099         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1100         .src_offset     = 0,
1101         .recalc         = &omap2_followparent_recalc,
1102 };
1103
1104 static struct clk gpt2_ick = {
1105         .name           = "gpt2_ick",
1106         .parent         = &l4_ck,
1107         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1108         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit4 */
1109         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1110         .recalc         = &omap2_followparent_recalc,
1111 };
1112
1113 static struct clk gpt2_fck = {
1114         .name           = "gpt2_fck",
1115         .parent         = &func_32k_ck,
1116         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1117                                 CM_CORE_SEL2,
1118         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1119         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1120         .src_offset     = 2,
1121         .recalc         = &omap2_followparent_recalc,
1122 };
1123
1124 static struct clk gpt3_ick = {
1125         .name           = "gpt3_ick",
1126         .parent         = &l4_ck,
1127         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1128         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit5 */
1129         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1130         .recalc         = &omap2_followparent_recalc,
1131 };
1132
1133 static struct clk gpt3_fck = {
1134         .name           = "gpt3_fck",
1135         .parent         = &func_32k_ck,
1136         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1137                                 CM_CORE_SEL2,
1138         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1139         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1140         .src_offset     = 4,
1141         .recalc         = &omap2_followparent_recalc,
1142 };
1143
1144 static struct clk gpt4_ick = {
1145         .name           = "gpt4_ick",
1146         .parent         = &l4_ck,
1147         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1148         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit6 */
1149         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1150         .recalc         = &omap2_followparent_recalc,
1151 };
1152
1153 static struct clk gpt4_fck = {
1154         .name           = "gpt4_fck",
1155         .parent         = &func_32k_ck,
1156         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1157                                 CM_CORE_SEL2,
1158         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1159         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1160         .src_offset     = 6,
1161         .recalc         = &omap2_followparent_recalc,
1162 };
1163
1164 static struct clk gpt5_ick = {
1165         .name           = "gpt5_ick",
1166         .parent         = &l4_ck,
1167         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1168         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* Bit7 */
1169         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1170         .recalc         = &omap2_followparent_recalc,
1171 };
1172
1173 static struct clk gpt5_fck = {
1174         .name           = "gpt5_fck",
1175         .parent         = &func_32k_ck,
1176         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1177                                 CM_CORE_SEL2,
1178         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1179         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1180         .src_offset     = 8,
1181         .recalc         = &omap2_followparent_recalc,
1182 };
1183
1184 static struct clk gpt6_ick = {
1185         .name           = "gpt6_ick",
1186         .parent         = &l4_ck,
1187         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1188         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1189         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit8 */
1190         .recalc         = &omap2_followparent_recalc,
1191 };
1192
1193 static struct clk gpt6_fck = {
1194         .name           = "gpt6_fck",
1195         .parent         = &func_32k_ck,
1196         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1197                                 CM_CORE_SEL2,
1198         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1199         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1200         .src_offset     = 10,
1201         .recalc         = &omap2_followparent_recalc,
1202 };
1203
1204 static struct clk gpt7_ick = {
1205         .name           = "gpt7_ick",
1206         .parent         = &l4_ck,
1207         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1208         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit9 */
1209         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1210         .recalc         = &omap2_followparent_recalc,
1211 };
1212
1213 static struct clk gpt7_fck = {
1214         .name           = "gpt7_fck",
1215         .parent         = &func_32k_ck,
1216         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1217                                 CM_CORE_SEL2,
1218         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1219         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1220         .src_offset     = 12,
1221         .recalc         = &omap2_followparent_recalc,
1222 };
1223
1224 static struct clk gpt8_ick = {
1225         .name           = "gpt8_ick",
1226         .parent         = &l4_ck,
1227         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1228         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit10 */
1229         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1230         .recalc         = &omap2_followparent_recalc,
1231 };
1232
1233 static struct clk gpt8_fck = {
1234         .name           = "gpt8_fck",
1235         .parent         = &func_32k_ck,
1236         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1237                                 CM_CORE_SEL2,
1238         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1239         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1240         .src_offset     = 14,
1241         .recalc         = &omap2_followparent_recalc,
1242 };
1243
1244 static struct clk gpt9_ick = {
1245         .name           = "gpt9_ick",
1246         .parent         = &l4_ck,
1247         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1248         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1249         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1250         .recalc         = &omap2_followparent_recalc,
1251 };
1252
1253 static struct clk gpt9_fck = {
1254         .name           = "gpt9_fck",
1255         .parent         = &func_32k_ck,
1256         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1257                                         CM_CORE_SEL2,
1258         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1259         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1260         .src_offset     = 16,
1261         .recalc         = &omap2_followparent_recalc,
1262 };
1263
1264 static struct clk gpt10_ick = {
1265         .name           = "gpt10_ick",
1266         .parent         = &l4_ck,
1267         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1268         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1269         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1270         .recalc         = &omap2_followparent_recalc,
1271 };
1272
1273 static struct clk gpt10_fck = {
1274         .name           = "gpt10_fck",
1275         .parent         = &func_32k_ck,
1276         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1277                                         CM_CORE_SEL2,
1278         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1279         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1280         .src_offset     = 18,
1281         .recalc         = &omap2_followparent_recalc,
1282 };
1283
1284 static struct clk gpt11_ick = {
1285         .name           = "gpt11_ick",
1286         .parent         = &l4_ck,
1287         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1288         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1289         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1290         .recalc         = &omap2_followparent_recalc,
1291 };
1292
1293 static struct clk gpt11_fck = {
1294         .name           = "gpt11_fck",
1295         .parent         = &func_32k_ck,
1296         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1297                                         CM_CORE_SEL2,
1298         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1299         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1300         .src_offset     = 20,
1301         .recalc         = &omap2_followparent_recalc,
1302 };
1303
1304 static struct clk gpt12_ick = {
1305         .name           = "gpt12_ick",
1306         .parent         = &l4_ck,
1307         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1308         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit14 */
1309         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1310         .recalc         = &omap2_followparent_recalc,
1311 };
1312
1313 static struct clk gpt12_fck = {
1314         .name           = "gpt12_fck",
1315         .parent         = &func_32k_ck,
1316         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1317                                         CM_CORE_SEL2,
1318         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1319         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1320         .src_offset     = 22,
1321         .recalc         = &omap2_followparent_recalc,
1322 };
1323
1324 /* REVISIT: bit comment below wrong? */
1325 static struct clk mcbsp1_ick = {
1326         .name           = "mcbsp1_ick",
1327         .parent         = &l4_ck,
1328         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1329         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit16 */
1330         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1331         .recalc         = &omap2_followparent_recalc,
1332 };
1333
1334 static struct clk mcbsp1_fck = {
1335         .name           = "mcbsp1_fck",
1336         .parent         = &func_96m_ck,
1337         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1338         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1339         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1340         .recalc         = &omap2_followparent_recalc,
1341 };
1342
1343 static struct clk mcbsp2_ick = {
1344         .name           = "mcbsp2_ick",
1345         .parent         = &l4_ck,
1346         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1347         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1348         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1349         .recalc         = &omap2_followparent_recalc,
1350 };
1351
1352 static struct clk mcbsp2_fck = {
1353         .name           = "mcbsp2_fck",
1354         .parent         = &func_96m_ck,
1355         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1356         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1357         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1358         .recalc         = &omap2_followparent_recalc,
1359 };
1360
1361 static struct clk mcbsp3_ick = {
1362         .name           = "mcbsp3_ick",
1363         .parent         = &l4_ck,
1364         .flags          = CLOCK_IN_OMAP243X,
1365         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1366         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1367         .recalc         = &omap2_followparent_recalc,
1368 };
1369
1370 static struct clk mcbsp3_fck = {
1371         .name           = "mcbsp3_fck",
1372         .parent         = &func_96m_ck,
1373         .flags          = CLOCK_IN_OMAP243X,
1374         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1375         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1376         .recalc         = &omap2_followparent_recalc,
1377 };
1378
1379 static struct clk mcbsp4_ick = {
1380         .name           = "mcbsp4_ick",
1381         .parent         = &l4_ck,
1382         .flags          = CLOCK_IN_OMAP243X,
1383         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1384         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1385         .recalc         = &omap2_followparent_recalc,
1386 };
1387
1388 static struct clk mcbsp4_fck = {
1389         .name           = "mcbsp4_fck",
1390         .parent         = &func_96m_ck,
1391         .flags          = CLOCK_IN_OMAP243X,
1392         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1393         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1394         .recalc         = &omap2_followparent_recalc,
1395 };
1396
1397 static struct clk mcbsp5_ick = {
1398         .name           = "mcbsp5_ick",
1399         .parent         = &l4_ck,
1400         .flags          = CLOCK_IN_OMAP243X,
1401         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1402         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1403         .recalc         = &omap2_followparent_recalc,
1404 };
1405
1406 static struct clk mcbsp5_fck = {
1407         .name           = "mcbsp5_fck",
1408         .parent         = &func_96m_ck,
1409         .flags          = CLOCK_IN_OMAP243X,
1410         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1411         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1412         .recalc         = &omap2_followparent_recalc,
1413 };
1414
1415 static struct clk mcspi1_ick = {
1416         .name           = "mcspi_ick",
1417         .id             = 1,
1418         .parent         = &l4_ck,
1419         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1420         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1421         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1422         .recalc         = &omap2_followparent_recalc,
1423 };
1424
1425 static struct clk mcspi1_fck = {
1426         .name           = "mcspi_fck",
1427         .id             = 1,
1428         .parent         = &func_48m_ck,
1429         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1430         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1431         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1432         .recalc         = &omap2_followparent_recalc,
1433 };
1434
1435 static struct clk mcspi2_ick = {
1436         .name           = "mcspi_ick",
1437         .id             = 2,
1438         .parent         = &l4_ck,
1439         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1440         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1441         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1442         .recalc         = &omap2_followparent_recalc,
1443 };
1444
1445 static struct clk mcspi2_fck = {
1446         .name           = "mcspi_fck",
1447         .id             = 2,
1448         .parent         = &func_48m_ck,
1449         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1450         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1451         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1452         .recalc         = &omap2_followparent_recalc,
1453 };
1454
1455 static struct clk mcspi3_ick = {
1456         .name           = "mcspi_ick",
1457         .id             = 3,
1458         .parent         = &l4_ck,
1459         .flags          = CLOCK_IN_OMAP243X,
1460         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1461         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1462         .recalc         = &omap2_followparent_recalc,
1463 };
1464
1465 static struct clk mcspi3_fck = {
1466         .name           = "mcspi_fck",
1467         .id             = 3,
1468         .parent         = &func_48m_ck,
1469         .flags          = CLOCK_IN_OMAP243X,
1470         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1471         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1472         .recalc         = &omap2_followparent_recalc,
1473 };
1474
1475 static struct clk uart1_ick = {
1476         .name           = "uart1_ick",
1477         .parent         = &l4_ck,
1478         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1479         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1480         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1481         .recalc         = &omap2_followparent_recalc,
1482 };
1483
1484 static struct clk uart1_fck = {
1485         .name           = "uart1_fck",
1486         .parent         = &func_48m_ck,
1487         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1488         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1489         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1490         .recalc         = &omap2_followparent_recalc,
1491 };
1492
1493 static struct clk uart2_ick = {
1494         .name           = "uart2_ick",
1495         .parent         = &l4_ck,
1496         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1497         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1498         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1499         .recalc         = &omap2_followparent_recalc,
1500 };
1501
1502 static struct clk uart2_fck = {
1503         .name           = "uart2_fck",
1504         .parent         = &func_48m_ck,
1505         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1506         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1507         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1508         .recalc         = &omap2_followparent_recalc,
1509 };
1510
1511 static struct clk uart3_ick = {
1512         .name           = "uart3_ick",
1513         .parent         = &l4_ck,
1514         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1515         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1516         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1517         .recalc         = &omap2_followparent_recalc,
1518 };
1519
1520 static struct clk uart3_fck = {
1521         .name           = "uart3_fck",
1522         .parent         = &func_48m_ck,
1523         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1524         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1525         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1526         .recalc         = &omap2_followparent_recalc,
1527 };
1528
1529 static struct clk gpios_ick = {
1530         .name           = "gpios_ick",
1531         .parent         = &l4_ck,
1532         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1533         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1534         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1535         .recalc         = &omap2_followparent_recalc,
1536 };
1537
1538 static struct clk gpios_fck = {
1539         .name           = "gpios_fck",
1540         .parent         = &func_32k_ck,
1541         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1542         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
1543         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1544         .recalc         = &omap2_followparent_recalc,
1545 };
1546
1547 static struct clk mpu_wdt_ick = {
1548         .name           = "mpu_wdt_ick",
1549         .parent         = &l4_ck,
1550         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1551         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1552         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
1553         .recalc         = &omap2_followparent_recalc,
1554 };
1555
1556 static struct clk mpu_wdt_fck = {
1557         .name           = "mpu_wdt_fck",
1558         .parent         = &func_32k_ck,
1559         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1560         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
1561         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
1562         .recalc         = &omap2_followparent_recalc,
1563 };
1564
1565 static struct clk sync_32k_ick = {
1566         .name           = "sync_32k_ick",
1567         .parent         = &l4_ck,
1568         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1569         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1570         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
1571         .recalc         = &omap2_followparent_recalc,
1572 };
1573 static struct clk wdt1_ick = {
1574         .name           = "wdt1_ick",
1575         .parent         = &l4_ck,
1576         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1577         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1578         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
1579         .recalc         = &omap2_followparent_recalc,
1580 };
1581 static struct clk omapctrl_ick = {
1582         .name           = "omapctrl_ick",
1583         .parent         = &l4_ck,
1584         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1585         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1586         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
1587         .recalc         = &omap2_followparent_recalc,
1588 };
1589 static struct clk icr_ick = {
1590         .name           = "icr_ick",
1591         .parent         = &l4_ck,
1592         .flags          = CLOCK_IN_OMAP243X,
1593         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1594         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
1595         .recalc         = &omap2_followparent_recalc,
1596 };
1597
1598 static struct clk cam_ick = {
1599         .name           = "cam_ick",
1600         .parent         = &l4_ck,
1601         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1602         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1603         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
1604         .recalc         = &omap2_followparent_recalc,
1605 };
1606
1607 static struct clk cam_fck = {
1608         .name           = "cam_fck",
1609         .parent         = &func_96m_ck,
1610         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1611         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1612         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
1613         .recalc         = &omap2_followparent_recalc,
1614 };
1615
1616 static struct clk mailboxes_ick = {
1617         .name           = "mailboxes_ick",
1618         .parent         = &l4_ck,
1619         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1620         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1621         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
1622         .recalc         = &omap2_followparent_recalc,
1623 };
1624
1625 static struct clk wdt4_ick = {
1626         .name           = "wdt4_ick",
1627         .parent         = &l4_ck,
1628         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1629         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1630         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
1631         .recalc         = &omap2_followparent_recalc,
1632 };
1633
1634 static struct clk wdt4_fck = {
1635         .name           = "wdt4_fck",
1636         .parent         = &func_32k_ck,
1637         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1638         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1639         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
1640         .recalc         = &omap2_followparent_recalc,
1641 };
1642
1643 static struct clk wdt3_ick = {
1644         .name           = "wdt3_ick",
1645         .parent         = &l4_ck,
1646         .flags          = CLOCK_IN_OMAP242X,
1647         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1648         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
1649         .recalc         = &omap2_followparent_recalc,
1650 };
1651
1652 static struct clk wdt3_fck = {
1653         .name           = "wdt3_fck",
1654         .parent         = &func_32k_ck,
1655         .flags          = CLOCK_IN_OMAP242X,
1656         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1657         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
1658         .recalc         = &omap2_followparent_recalc,
1659 };
1660
1661 static struct clk mspro_ick = {
1662         .name           = "mspro_ick",
1663         .parent         = &l4_ck,
1664         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1665         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1666         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
1667         .recalc         = &omap2_followparent_recalc,
1668 };
1669
1670 static struct clk mspro_fck = {
1671         .name           = "mspro_fck",
1672         .parent         = &func_96m_ck,
1673         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1674         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1675         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
1676         .recalc         = &omap2_followparent_recalc,
1677 };
1678
1679 static struct clk mmc_ick = {
1680         .name           = "mmc_ick",
1681         .parent         = &l4_ck,
1682         .flags          = CLOCK_IN_OMAP242X,
1683         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1684         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
1685         .recalc         = &omap2_followparent_recalc,
1686 };
1687
1688 static struct clk mmc_fck = {
1689         .name           = "mmc_fck",
1690         .parent         = &func_96m_ck,
1691         .flags          = CLOCK_IN_OMAP242X,
1692         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1693         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
1694         .recalc         = &omap2_followparent_recalc,
1695 };
1696
1697 static struct clk fac_ick = {
1698         .name           = "fac_ick",
1699         .parent         = &l4_ck,
1700         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1701         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1702         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
1703         .recalc         = &omap2_followparent_recalc,
1704 };
1705
1706 static struct clk fac_fck = {
1707         .name           = "fac_fck",
1708         .parent         = &func_12m_ck,
1709         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1710         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1711         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
1712         .recalc         = &omap2_followparent_recalc,
1713 };
1714
1715 static struct clk eac_ick = {
1716         .name           = "eac_ick",
1717         .parent         = &l4_ck,
1718         .flags          = CLOCK_IN_OMAP242X,
1719         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1720         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
1721         .recalc         = &omap2_followparent_recalc,
1722 };
1723
1724 static struct clk eac_fck = {
1725         .name           = "eac_fck",
1726         .parent         = &func_96m_ck,
1727         .flags          = CLOCK_IN_OMAP242X,
1728         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1729         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
1730         .recalc         = &omap2_followparent_recalc,
1731 };
1732
1733 static struct clk hdq_ick = {
1734         .name           = "hdq_ick",
1735         .parent         = &l4_ck,
1736         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1737         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1738         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
1739         .recalc         = &omap2_followparent_recalc,
1740 };
1741
1742 static struct clk hdq_fck = {
1743         .name           = "hdq_fck",
1744         .parent         = &func_12m_ck,
1745         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1746         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1747         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
1748         .recalc         = &omap2_followparent_recalc,
1749 };
1750
1751 static struct clk i2c2_ick = {
1752         .name           = "i2c_ick",
1753         .id             = 2,
1754         .parent         = &l4_ck,
1755         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1756         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1757         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
1758         .recalc         = &omap2_followparent_recalc,
1759 };
1760
1761 static struct clk i2c2_fck = {
1762         .name           = "i2c_fck",
1763         .id             = 2,
1764         .parent         = &func_12m_ck,
1765         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1766         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1767         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
1768         .recalc         = &omap2_followparent_recalc,
1769 };
1770
1771 static struct clk i2chs2_fck = {
1772         .name           = "i2chs_fck",
1773         .id             = 2,
1774         .parent         = &func_96m_ck,
1775         .flags          = CLOCK_IN_OMAP243X,
1776         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1777         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
1778         .recalc         = &omap2_followparent_recalc,
1779 };
1780
1781 static struct clk i2c1_ick = {
1782         .name           = "i2c_ick",
1783         .id             = 1,
1784         .parent         = &l4_ck,
1785         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1786         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1787         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
1788         .recalc         = &omap2_followparent_recalc,
1789 };
1790
1791 static struct clk i2c1_fck = {
1792         .name           = "i2c_fck",
1793         .id             = 1,
1794         .parent         = &func_12m_ck,
1795         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1796         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1797         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
1798         .recalc         = &omap2_followparent_recalc,
1799 };
1800
1801 static struct clk i2chs1_fck = {
1802         .name           = "i2chs_fck",
1803         .id             = 1,
1804         .parent         = &func_96m_ck,
1805         .flags          = CLOCK_IN_OMAP243X,
1806         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1807         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
1808         .recalc         = &omap2_followparent_recalc,
1809 };
1810
1811 static struct clk vlynq_ick = {
1812         .name           = "vlynq_ick",
1813         .parent         = &core_l3_ck,
1814         .flags          = CLOCK_IN_OMAP242X,
1815         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1816         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
1817         .recalc         = &omap2_followparent_recalc,
1818 };
1819
1820 static struct clk vlynq_fck = {
1821         .name           = "vlynq_fck",
1822         .parent         = &func_96m_ck,
1823         .flags          = CLOCK_IN_OMAP242X  | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
1824         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1825         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
1826         .src_offset     = 15,
1827         .recalc         = &omap2_followparent_recalc,
1828 };
1829
1830 static struct clk sdrc_ick = {
1831         .name           = "sdrc_ick",
1832         .parent         = &l4_ck,
1833         .flags          = CLOCK_IN_OMAP243X,
1834         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP2430_CM_ICLKEN3),
1835         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
1836         .recalc         = &omap2_followparent_recalc,
1837 };
1838
1839 static struct clk des_ick = {
1840         .name           = "des_ick",
1841         .parent         = &l4_ck,
1842         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1843         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1844         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
1845         .recalc         = &omap2_followparent_recalc,
1846 };
1847
1848 static struct clk sha_ick = {
1849         .name           = "sha_ick",
1850         .parent         = &l4_ck,
1851         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1852         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1853         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
1854         .recalc         = &omap2_followparent_recalc,
1855 };
1856
1857 static struct clk rng_ick = {
1858         .name           = "rng_ick",
1859         .parent         = &l4_ck,
1860         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1861         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1862         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
1863         .recalc         = &omap2_followparent_recalc,
1864 };
1865
1866 static struct clk aes_ick = {
1867         .name           = "aes_ick",
1868         .parent         = &l4_ck,
1869         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1870         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1871         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
1872         .recalc         = &omap2_followparent_recalc,
1873 };
1874
1875 static struct clk pka_ick = {
1876         .name           = "pka_ick",
1877         .parent         = &l4_ck,
1878         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1879         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1880         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
1881         .recalc         = &omap2_followparent_recalc,
1882 };
1883
1884 static struct clk usb_fck = {
1885         .name           = "usb_fck",
1886         .parent         = &func_48m_ck,
1887         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1888         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1889         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1890         .recalc         = &omap2_followparent_recalc,
1891 };
1892
1893 static struct clk usbhs_ick = {
1894         .name           = "usbhs_ick",
1895         .parent         = &core_l3_ck,
1896         .flags          = CLOCK_IN_OMAP243X,
1897         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1898         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
1899         .recalc         = &omap2_followparent_recalc,
1900 };
1901
1902 static struct clk mmchs1_ick = {
1903         .name           = "mmchs1_ick",
1904         .parent         = &l4_ck,
1905         .flags          = CLOCK_IN_OMAP243X,
1906         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1907         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
1908         .recalc         = &omap2_followparent_recalc,
1909 };
1910
1911 static struct clk mmchs1_fck = {
1912         .name           = "mmchs1_fck",
1913         .parent         = &func_96m_ck,
1914         .flags          = CLOCK_IN_OMAP243X,
1915         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1916         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
1917         .recalc         = &omap2_followparent_recalc,
1918 };
1919
1920 static struct clk mmchs2_ick = {
1921         .name           = "mmchs2_ick",
1922         .parent         = &l4_ck,
1923         .flags          = CLOCK_IN_OMAP243X,
1924         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1925         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
1926         .recalc         = &omap2_followparent_recalc,
1927 };
1928
1929 static struct clk mmchs2_fck = {
1930         .name           = "mmchs2_fck",
1931         .parent         = &func_96m_ck,
1932         .flags          = CLOCK_IN_OMAP243X,
1933         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1934         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
1935         .recalc         = &omap2_followparent_recalc,
1936 };
1937
1938 static struct clk gpio5_ick = {
1939         .name           = "gpio5_ick",
1940         .parent         = &l4_ck,
1941         .flags          = CLOCK_IN_OMAP243X,
1942         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1943         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
1944         .recalc         = &omap2_followparent_recalc,
1945 };
1946
1947 static struct clk gpio5_fck = {
1948         .name           = "gpio5_fck",
1949         .parent         = &func_32k_ck,
1950         .flags          = CLOCK_IN_OMAP243X,
1951         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1952         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
1953         .recalc         = &omap2_followparent_recalc,
1954 };
1955
1956 static struct clk mdm_intc_ick = {
1957         .name           = "mdm_intc_ick",
1958         .parent         = &l4_ck,
1959         .flags          = CLOCK_IN_OMAP243X,
1960         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1961         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
1962         .recalc         = &omap2_followparent_recalc,
1963 };
1964
1965 static struct clk mmchsdb1_fck = {
1966         .name           = "mmchsdb1_fck",
1967         .parent         = &func_32k_ck,
1968         .flags          = CLOCK_IN_OMAP243X,
1969         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1970         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
1971         .recalc         = &omap2_followparent_recalc,
1972 };
1973
1974 static struct clk mmchsdb2_fck = {
1975         .name           = "mmchsdb2_fck",
1976         .parent         = &func_32k_ck,
1977         .flags          = CLOCK_IN_OMAP243X,
1978         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1979         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
1980         .recalc         = &omap2_followparent_recalc,
1981 };
1982
1983 /*
1984  * This clock is a composite clock which does entire set changes then
1985  * forces a rebalance. It keys on the MPU speed, but it really could
1986  * be any key speed part of a set in the rate table.
1987  *
1988  * to really change a set, you need memory table sets which get changed
1989  * in sram, pre-notifiers & post notifiers, changing the top set, without
1990  * having low level display recalc's won't work... this is why dpm notifiers
1991  * work, isr's off, walk a list of clocks already _off_ and not messing with
1992  * the bus.
1993  *
1994  * This clock should have no parent. It embodies the entire upper level
1995  * active set. A parent will mess up some of the init also.
1996  */
1997 static struct clk virt_prcm_set = {
1998         .name           = "virt_prcm_set",
1999         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2000                                 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
2001         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
2002         .recalc         = &omap2_mpu_recalc,    /* sets are keyed on mpu rate */
2003         .set_rate       = &omap2_select_table_rate,
2004         .round_rate     = &omap2_round_to_table_rate,
2005 };
2006
2007 static struct clk *onchip_clks[] = {
2008         /* external root sources */
2009         &func_32k_ck,
2010         &osc_ck,
2011         &sys_ck,
2012         &alt_ck,
2013         /* internal analog sources */
2014         &dpll_ck,
2015         &apll96_ck,
2016         &apll54_ck,
2017         /* internal prcm root sources */
2018         &func_54m_ck,
2019         &core_ck,
2020         &sleep_ck,
2021         &func_96m_ck,
2022         &func_48m_ck,
2023         &func_12m_ck,
2024         &wdt1_osc_ck,
2025         &sys_clkout,
2026         &sys_clkout2,
2027         &emul_ck,
2028         /* mpu domain clocks */
2029         &mpu_ck,
2030         /* dsp domain clocks */
2031         &iva2_1_fck,            /* 2430 */
2032         &iva2_1_ick,
2033         &dsp_ick,               /* 2420 */
2034         &dsp_fck,
2035         &iva1_ifck,
2036         &iva1_mpu_int_ifck,
2037         /* GFX domain clocks */
2038         &gfx_3d_fck,
2039         &gfx_2d_fck,
2040         &gfx_ick,
2041         /* Modem domain clocks */
2042         &mdm_ick,
2043         &mdm_osc_ck,
2044         /* DSS domain clocks */
2045         &dss_ick,
2046         &dss1_fck,
2047         &dss2_fck,
2048         &dss_54m_fck,
2049         /* L3 domain clocks */
2050         &core_l3_ck,
2051         &ssi_ssr_sst_fck,
2052         &usb_l4_ick,
2053         /* L4 domain clocks */
2054         &l4_ck,                 /* used as both core_l4 and wu_l4 */
2055         &ssi_l4_ick,
2056         /* virtual meta-group clock */
2057         &virt_prcm_set,
2058         /* general l4 interface ck, multi-parent functional clk */
2059         &gpt1_ick,
2060         &gpt1_fck,
2061         &gpt2_ick,
2062         &gpt2_fck,
2063         &gpt3_ick,
2064         &gpt3_fck,
2065         &gpt4_ick,
2066         &gpt4_fck,
2067         &gpt5_ick,
2068         &gpt5_fck,
2069         &gpt6_ick,
2070         &gpt6_fck,
2071         &gpt7_ick,
2072         &gpt7_fck,
2073         &gpt8_ick,
2074         &gpt8_fck,
2075         &gpt9_ick,
2076         &gpt9_fck,
2077         &gpt10_ick,
2078         &gpt10_fck,
2079         &gpt11_ick,
2080         &gpt11_fck,
2081         &gpt12_ick,
2082         &gpt12_fck,
2083         &mcbsp1_ick,
2084         &mcbsp1_fck,
2085         &mcbsp2_ick,
2086         &mcbsp2_fck,
2087         &mcbsp3_ick,
2088         &mcbsp3_fck,
2089         &mcbsp4_ick,
2090         &mcbsp4_fck,
2091         &mcbsp5_ick,
2092         &mcbsp5_fck,
2093         &mcspi1_ick,
2094         &mcspi1_fck,
2095         &mcspi2_ick,
2096         &mcspi2_fck,
2097         &mcspi3_ick,
2098         &mcspi3_fck,
2099         &uart1_ick,
2100         &uart1_fck,
2101         &uart2_ick,
2102         &uart2_fck,
2103         &uart3_ick,
2104         &uart3_fck,
2105         &gpios_ick,
2106         &gpios_fck,
2107         &mpu_wdt_ick,
2108         &mpu_wdt_fck,
2109         &sync_32k_ick,
2110         &wdt1_ick,
2111         &omapctrl_ick,
2112         &icr_ick,
2113         &cam_fck,
2114         &cam_ick,
2115         &mailboxes_ick,
2116         &wdt4_ick,
2117         &wdt4_fck,
2118         &wdt3_ick,
2119         &wdt3_fck,
2120         &mspro_ick,
2121         &mspro_fck,
2122         &mmc_ick,
2123         &mmc_fck,
2124         &fac_ick,
2125         &fac_fck,
2126         &eac_ick,
2127         &eac_fck,
2128         &hdq_ick,
2129         &hdq_fck,
2130         &i2c1_ick,
2131         &i2c1_fck,
2132         &i2chs1_fck,
2133         &i2c2_ick,
2134         &i2c2_fck,
2135         &i2chs2_fck,
2136         &vlynq_ick,
2137         &vlynq_fck,
2138         &sdrc_ick,
2139         &des_ick,
2140         &sha_ick,
2141         &rng_ick,
2142         &aes_ick,
2143         &pka_ick,
2144         &usb_fck,
2145         &usbhs_ick,
2146         &mmchs1_ick,
2147         &mmchs1_fck,
2148         &mmchs2_ick,
2149         &mmchs2_fck,
2150         &gpio5_ick,
2151         &gpio5_fck,
2152         &mdm_intc_ick,
2153         &mmchsdb1_fck,
2154         &mmchsdb2_fck,
2155 };
2156
2157 #endif