arch/arm/mach-omap2/clock.h

   1 /*
   2  *  linux/arch/arm/mach-omap24xx/clock.h
   3  *
   4  *  Copyright (C) 2005 Texas Instruments Inc.
   5  *  Richard Woodruff <r-woodruff2@ti.com>
   6  *  Created for OMAP2.
   7  *
   8  *  Copyright (C) 2004 Nokia corporation
   9  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  10  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
  18 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
  19
  20 #include "prm.h"
  21 #include "cm.h"
  22 #include "prm_regbits_24xx.h"
  23 #include "cm_regbits_24xx.h"
  24
  25 static void omap2_sys_clk_recalc(struct clk * clk);
  26 static void omap2_clksel_recalc(struct clk * clk);
  27 static void omap2_followparent_recalc(struct clk * clk);
  28 static void omap2_propagate_rate(struct clk * clk);
  29 static void omap2_mpu_recalc(struct clk * clk);
  30 static int omap2_select_table_rate(struct clk * clk, unsigned long rate);
  31 static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate);
  32 static void omap2_clk_disable(struct clk *clk);
  33 static void omap2_sys_clk_recalc(struct clk * clk);
  34 static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val);
  35 static u32 omap2_clksel_get_divisor(struct clk *clk);
  36
  37 /* REVISIT: should use a clock flag for this, not a magic number */
  38 #define PARENT_CONTROLS_CLOCK   0xff
  39
  40 #define RATE_IN_242X    (1 << 0)
  41 #define RATE_IN_243X    (1 << 1)
  42 #define RATE_IN_343X    (1 << 2)
  43
  44 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  45  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  46  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  47  */
  48 struct prcm_config {
  49         unsigned long xtal_speed;       /* crystal rate */
  50         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  51         unsigned long mpu_speed;        /* speed of MPU */
  52         unsigned long cm_clksel_mpu;    /* mpu divider */
  53         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  54         unsigned long cm_clksel_gfx;    /* gfx dividers */
  55         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  56         unsigned long cm_clksel1_pll;   /* m,n */
  57         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  58         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  59         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  60         unsigned char flags;
  61 };
  62
  63 /* Mask for clksel which support parent settign in set_rate */
  64 #define SRC_SEL_MASK (CM_CORE_SEL1 | CM_CORE_SEL2 | CM_WKUP_SEL1 | \
  65                         CM_PLL_SEL1 | CM_PLL_SEL2 | CM_SYSCLKOUT_SEL1)
  66
  67 /* Mask for clksel regs which support rate operations */
  68 #define SRC_RATE_SEL_MASK (CM_MPU_SEL1 | CM_DSP_SEL1 | CM_GFX_SEL1 | \
  69                         CM_MODEM_SEL1 | CM_CORE_SEL1 | CM_CORE_SEL2 | \
  70                         CM_WKUP_SEL1 | CM_PLL_SEL1 | CM_PLL_SEL2 | \
  71                         CM_SYSCLKOUT_SEL1)
  72
  73 /*
  74  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  75  * These configurations are characterized by voltage and speed for clocks.
  76  * The device is only validated for certain combinations. One way to express
  77  * these combinations is via the 'ratio's' which the clocks operate with
  78  * respect to each other. These ratio sets are for a given voltage/DPLL
  79  * setting. All configurations can be described by a DPLL setting and a ratio
  80  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  81  *
  82  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  83  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  84  * 2430 (iva2.1, NOdsp, mdm)
  85  */
  86
  87 /* Core fields for cm_clksel, not ratio governed */
  88 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  89 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  90 #define RX_CLKSEL_SSI                   (0x5 << 20)
  91
  92 /*-------------------------------------------------------------------------
  93  * Voltage/DPLL ratios
  94  *-------------------------------------------------------------------------*/
  95
  96 /* 2430 Ratio's, 2430-Ratio Config 1 */
  97 #define R1_CLKSEL_L3                    (4 << 0)
  98 #define R1_CLKSEL_L4                    (2 << 5)
  99 #define R1_CLKSEL_USB                   (4 << 25)
 100 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
 101                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 102                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
 103 #define R1_CLKSEL_MPU                   (2 << 0)
 104 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
 105 #define R1_CLKSEL_DSP                   (2 << 0)
 106 #define R1_CLKSEL_DSP_IF                (2 << 5)
 107 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
 108 #define R1_CLKSEL_GFX                   (2 << 0)
 109 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
 110 #define R1_CLKSEL_MDM                   (4 << 0)
 111 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
 112
 113 /* 2430-Ratio Config 2 */
 114 #define R2_CLKSEL_L3                    (6 << 0)
 115 #define R2_CLKSEL_L4                    (2 << 5)
 116 #define R2_CLKSEL_USB                   (2 << 25)
 117 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
 118                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 119                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
 120 #define R2_CLKSEL_MPU                   (2 << 0)
 121 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 122 #define R2_CLKSEL_DSP                   (2 << 0)
 123 #define R2_CLKSEL_DSP_IF                (3 << 5)
 124 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 125 #define R2_CLKSEL_GFX                   (2 << 0)
 126 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 127 #define R2_CLKSEL_MDM                   (6 << 0)
 128 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 129
 130 /* 2430-Ratio Bootm (BYPASS) */
 131 #define RB_CLKSEL_L3                    (1 << 0)
 132 #define RB_CLKSEL_L4                    (1 << 5)
 133 #define RB_CLKSEL_USB                   (1 << 25)
 134 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 135                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 136                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 137 #define RB_CLKSEL_MPU                   (1 << 0)
 138 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 139 #define RB_CLKSEL_DSP                   (1 << 0)
 140 #define RB_CLKSEL_DSP_IF                (1 << 5)
 141 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 142 #define RB_CLKSEL_GFX                   (1 << 0)
 143 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 144 #define RB_CLKSEL_MDM                   (1 << 0)
 145 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 146
 147 /* 2420 Ratio Equivalents */
 148 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 149 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 150
 151 /* 2420-PRCM III 532MHz core */
 152 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 153 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 154 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 155 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 156                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 157                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 158                                         RIII_CLKSEL_L3
 159 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 160 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 161 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 162 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 163 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 164 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 165 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 166 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 167                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 168                                         RIII_CLKSEL_DSP
 169 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 170 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 171
 172 /* 2420-PRCM II 600MHz core */
 173 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 174 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 175 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 176 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 177                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 178                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 179                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 180 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 181 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 182 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 183 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 184 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 185 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 186 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 187 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 188                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 189                                         RII_CLKSEL_DSP
 190 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 191 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 192
 193 /* 2420-PRCM I 660MHz core */
 194 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 195 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 196 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 197 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 198                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 199                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 200                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 201 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 202 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 203 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 204 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 205 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 206 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 207 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 208 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 209                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 210                                         RI_CLKSEL_DSP
 211 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 212 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 213
 214 /* 2420-PRCM VII (boot) */
 215 #define RVII_CLKSEL_L3                  (1 << 0)
 216 #define RVII_CLKSEL_L4                  (1 << 5)
 217 #define RVII_CLKSEL_DSS1                (1 << 8)
 218 #define RVII_CLKSEL_DSS2                (0 << 13)
 219 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 220 #define RVII_CLKSEL_SSI                 (1 << 20)
 221 #define RVII_CLKSEL_USB                 (1 << 25)
 222
 223 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 224                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 225                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 226
 227 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 228 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 229
 230 #define RVII_CLKSEL_DSP                 (1 << 0)
 231 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 232 #define RVII_SYNC_DSP                   (0 << 7)
 233 #define RVII_CLKSEL_IVA                 (1 << 8)
 234 #define RVII_SYNC_IVA                   (0 << 13)
 235 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 236                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 237
 238 #define RVII_CLKSEL_GFX                 (1 << 0)
 239 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 240
 241 /*-------------------------------------------------------------------------
 242  * 2430 Target modes: Along with each configuration the CPU has several
 243  * modes which goes along with them. Modes mainly are the addition of
 244  * describe DPLL combinations to go along with a ratio.
 245  *-------------------------------------------------------------------------*/
 246
 247 /* Hardware governed */
 248 #define MX_48M_SRC                      (0 << 3)
 249 #define MX_54M_SRC                      (0 << 5)
 250 #define MX_APLLS_CLIKIN_12              (3 << 23)
 251 #define MX_APLLS_CLIKIN_13              (2 << 23)
 252 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 253
 254 /*
 255  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 256  * #2   (ratio1) baseport-target
 257  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 258  */
 259 #define M5A_DPLL_MULT_12                (133 << 12)
 260 #define M5A_DPLL_DIV_12                 (5 << 8)
 261 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 262                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 263                                         MX_APLLS_CLIKIN_12
 264 #define M5A_DPLL_MULT_13                (266 << 12)
 265 #define M5A_DPLL_DIV_13                 (12 << 8)
 266 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 267                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 268                                         MX_APLLS_CLIKIN_13
 269 #define M5A_DPLL_MULT_19                (180 << 12)
 270 #define M5A_DPLL_DIV_19                 (12 << 8)
 271 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 272                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 273                                         MX_APLLS_CLIKIN_19_2
 274 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 275 #define M5B_DPLL_MULT_12                (50 << 12)
 276 #define M5B_DPLL_DIV_12                 (2 << 8)
 277 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 278                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 279                                         MX_APLLS_CLIKIN_12
 280 #define M5B_DPLL_MULT_13                (200 << 12)
 281 #define M5B_DPLL_DIV_13                 (12 << 8)
 282
 283 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 284                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 285                                         MX_APLLS_CLIKIN_13
 286 #define M5B_DPLL_MULT_19                (125 << 12)
 287 #define M5B_DPLL_DIV_19                 (31 << 8)
 288 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 289                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 290                                         MX_APLLS_CLIKIN_19_2
 291 /*
 292  * #4   (ratio2)
 293  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 294  */
 295 #define M3_DPLL_MULT_12                 (55 << 12)
 296 #define M3_DPLL_DIV_12                  (1 << 8)
 297 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 298                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 299                                         MX_APLLS_CLIKIN_12
 300 #define M3_DPLL_MULT_13                 (330 << 12)
 301 #define M3_DPLL_DIV_13                  (12 << 8)
 302 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 303                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 304                                         MX_APLLS_CLIKIN_13
 305 #define M3_DPLL_MULT_19                 (275 << 12)
 306 #define M3_DPLL_DIV_19                  (15 << 8)
 307 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 308                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 309                                         MX_APLLS_CLIKIN_19_2
 310 /* boot (boot) */
 311 #define MB_DPLL_MULT                    (1 << 12)
 312 #define MB_DPLL_DIV                     (0 << 8)
 313 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 314                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 315
 316 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 317                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 318
 319 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 320                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 321
 322 /*
 323  * 2430 - chassis (sedna)
 324  * 165 (ratio1) same as above #2
 325  * 150 (ratio1)
 326  * 133 (ratio2) same as above #4
 327  * 110 (ratio2) same as above #3
 328  * 104 (ratio2)
 329  * boot (boot)
 330  */
 331
 332 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 333 #define MI_DPLL_MULT_12                 (55 << 12)
 334 #define MI_DPLL_DIV_12                  (1 << 8)
 335 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 336                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 337                                         MX_APLLS_CLIKIN_12
 338
 339 /*
 340  * 2420 Equivalent - mode registers
 341  * PRCM II , target DPLL = 2*300MHz = 600MHz
 342  */
 343 #define MII_DPLL_MULT_12                (50 << 12)
 344 #define MII_DPLL_DIV_12                 (1 << 8)
 345 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 346                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 347                                         MX_APLLS_CLIKIN_12
 348 #define MII_DPLL_MULT_13                (300 << 12)
 349 #define MII_DPLL_DIV_13                 (12 << 8)
 350 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 351                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 352                                         MX_APLLS_CLIKIN_13
 353
 354 /* PRCM III target DPLL = 2*266 = 532MHz*/
 355 #define MIII_DPLL_MULT_12               (133 << 12)
 356 #define MIII_DPLL_DIV_12                (5 << 8)
 357 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 358                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 359                                         MX_APLLS_CLIKIN_12
 360 #define MIII_DPLL_MULT_13               (266 << 12)
 361 #define MIII_DPLL_DIV_13                (12 << 8)
 362 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 363                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 364                                         MX_APLLS_CLIKIN_13
 365
 366 /* PRCM VII (boot bypass) */
 367 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 368 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 369
 370 /* High and low operation value */
 371 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 372 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 373
 374 /*
 375  * These represent optimal values for common parts, it won't work for all.
 376  * As long as you scale down, most parameters are still work, they just
 377  * become sub-optimal. The RFR value goes in the opposite direction. If you
 378  * don't adjust it down as your clock period increases the refresh interval
 379  * will not be met. Setting all parameters for complete worst case may work,
 380  * but may cut memory performance by 2x. Due to errata the DLLs need to be
 381  * unlocked and their value needs run time calibration. A dynamic call is
 382  * need for that as no single right value exists acorss production samples.
 383  *
 384  * Only the FULL speed values are given. Current code is such that rate
 385  * changes must be made at DPLLoutx2. The actual value adjustment for low
 386  * frequency operation will be handled by omap_set_performance()
 387  *
 388  * By having the boot loader boot up in the fastest L4 speed available likely
 389  * will result in something which you can switch between.
 390  */
 391 #define V24XX_SDRC_RFR_CTRL_165MHz      (0x00044c00 | 1)
 392 #define V24XX_SDRC_RFR_CTRL_133MHz      (0x0003de00 | 1)
 393 #define V24XX_SDRC_RFR_CTRL_100MHz      (0x0002da01 | 1)
 394 #define V24XX_SDRC_RFR_CTRL_110MHz      (0x0002da01 | 1) /* Need to calc */
 395 #define V24XX_SDRC_RFR_CTRL_BYPASS      (0x00005000 | 1) /* Need to calc */
 396
 397 /* MPU speed defines */
 398 #define S12M    12000000
 399 #define S13M    13000000
 400 #define S19M    19200000
 401 #define S26M    26000000
 402 #define S100M   100000000
 403 #define S133M   133000000
 404 #define S150M   150000000
 405 #define S165M   165000000
 406 #define S200M   200000000
 407 #define S266M   266000000
 408 #define S300M   300000000
 409 #define S330M   330000000
 410 #define S400M   400000000
 411 #define S532M   532000000
 412 #define S600M   600000000
 413 #define S660M   660000000
 414
 415 /*-------------------------------------------------------------------------
 416  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 417  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 418  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 419  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 420  *
 421  * Filling in table based on H4 boards and 2430-SDPs variants available.
 422  * There are quite a few more rates combinations which could be defined.
 423  *
 424  * When multiple values are defined the start up will try and choose the
 425  * fastest one. If a 'fast' value is defined, then automatically, the /2
 426  * one should be included as it can be used.    Generally having more that
 427  * one fast set does not make sense, as static timings need to be changed
 428  * to change the set.    The exception is the bypass setting which is
 429  * availble for low power bypass.
 430  *
 431  * Note: This table needs to be sorted, fastest to slowest.
 432  *-------------------------------------------------------------------------*/
 433 static struct prcm_config rate_table[] = {
 434         /* PRCM I - FAST */
 435         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 436                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 437                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 438                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_165MHz,
 439                 RATE_IN_242X},
 440
 441         /* PRCM II - FAST */
 442         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 443                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 444                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 445                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 446                 RATE_IN_242X},
 447
 448         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 449                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 450                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 451                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 452                 RATE_IN_242X},
 453
 454         /* PRCM III - FAST */
 455         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 456                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 457                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 458                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 459                 RATE_IN_242X},
 460
 461         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 462                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 463                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 464                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 465                 RATE_IN_242X},
 466
 467         /* PRCM II - SLOW */
 468         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 469                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 470                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 471                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 472                 RATE_IN_242X},
 473
 474         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 475                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 476                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 477                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 478                 RATE_IN_242X},
 479
 480         /* PRCM III - SLOW */
 481         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 482                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 483                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 484                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 485                 RATE_IN_242X},
 486
 487         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 488                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 489                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 490                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 491                 RATE_IN_242X},
 492
 493         /* PRCM-VII (boot-bypass) */
 494         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 495                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 496                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 497                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
 498                 RATE_IN_242X},
 499
 500         /* PRCM-VII (boot-bypass) */
 501         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 502                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 503                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 504                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
 505                 RATE_IN_242X},
 506
 507         /* PRCM #3 - ratio2 (ES2) - FAST */
 508         {S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 509                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 510                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 511                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 512                 V24XX_SDRC_RFR_CTRL_110MHz,
 513                 RATE_IN_243X},
 514
 515         /* PRCM #5a - ratio1 - FAST */
 516         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 517                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 518                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 519                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 520                 V24XX_SDRC_RFR_CTRL_133MHz,
 521                 RATE_IN_243X},
 522
 523         /* PRCM #5b - ratio1 - FAST */
 524         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 525                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 526                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 527                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 528                 V24XX_SDRC_RFR_CTRL_100MHz,
 529                 RATE_IN_243X},
 530
 531         /* PRCM #3 - ratio2 (ES2) - SLOW */
 532         {S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 533                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 534                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 535                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 536                 V24XX_SDRC_RFR_CTRL_110MHz,
 537                 RATE_IN_243X},
 538
 539         /* PRCM #5a - ratio1 - SLOW */
 540         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 541                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 542                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 543                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 544                 V24XX_SDRC_RFR_CTRL_133MHz,
 545                 RATE_IN_243X},
 546
 547         /* PRCM #5b - ratio1 - SLOW*/
 548         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 549                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 550                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 551                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 552                 V24XX_SDRC_RFR_CTRL_100MHz,
 553                 RATE_IN_243X},
 554
 555         /* PRCM-boot/bypass */
 556         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 557                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 558                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 559                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 560                 V24XX_SDRC_RFR_CTRL_BYPASS,
 561                 RATE_IN_243X},
 562
 563         /* PRCM-boot/bypass */
 564         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 565                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 566                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 567                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 568                 V24XX_SDRC_RFR_CTRL_BYPASS,
 569                 RATE_IN_243X},
 570
 571         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 572 };
 573
 574 /*-------------------------------------------------------------------------
 575  * 24xx clock tree.
 576  *
 577  * NOTE:In many cases here we are assigning a 'default' parent. In many
 578  *      cases the parent is selectable. The get/set parent calls will also
 579  *      switch sources.
 580  *
 581  *      Many some clocks say always_enabled, but they can be auto idled for
 582  *      power savings. They will always be available upon clock request.
 583  *
 584  *      Several sources are given initial rates which may be wrong, this will
 585  *      be fixed up in the init func.
 586  *
 587  *      Things are broadly separated below by clock domains. It is
 588  *      noteworthy that most periferals have dependencies on multiple clock
 589  *      domains. Many get their interface clocks from the L4 domain, but get
 590  *      functional clocks from fixed sources or other core domain derived
 591  *      clocks.
 592  *-------------------------------------------------------------------------*/
 593
 594 /* Base external input clocks */
 595 static struct clk func_32k_ck = {
 596         .name           = "func_32k_ck",
 597         .rate           = 32000,
 598         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 599                                 RATE_FIXED | ALWAYS_ENABLED,
 600 };
 601
 602 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 603 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 604         .name           = "osc_ck",
 605         .rate           = 26000000,             /* fixed up in clock init */
 606         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 607                                 RATE_FIXED | RATE_PROPAGATES,
 608 };
 609
 610 /* With out modem likely 12MHz, with modem likely 13MHz */
 611 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 612         .name           = "sys_ck",             /* ~ ref_clk also */
 613         .parent         = &osc_ck,
 614         .rate           = 13000000,
 615         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 616                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 617         .rate_offset    = 6, /* sysclkdiv 1 or 2, already handled or no boot */
 618         .recalc         = &omap2_sys_clk_recalc,
 619 };
 620
 621 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 622         .name           = "alt_ck",
 623         .rate           = 54000000,
 624         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 625                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 626         .recalc         = &omap2_propagate_rate,
 627 };
 628
 629 /*
 630  * Analog domain root source clocks
 631  */
 632
 633 /* dpll_ck, is broken out in to special cases through clksel */
 634 static struct clk dpll_ck = {
 635         .name           = "dpll_ck",
 636         .parent         = &sys_ck,              /* Can be func_32k also */
 637         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 638                                 RATE_PROPAGATES | RATE_CKCTL | CM_PLL_SEL1,
 639         .recalc         = &omap2_clksel_recalc,
 640 };
 641
 642 static struct clk apll96_ck = {
 643         .name           = "apll96_ck",
 644         .parent         = &sys_ck,
 645         .rate           = 96000000,
 646         .flags          = CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X |
 647                                 RATE_FIXED | RATE_PROPAGATES,
 648         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 649         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 650         .recalc         = &omap2_propagate_rate,
 651 };
 652
 653 static struct clk apll54_ck = {
 654         .name           = "apll54_ck",
 655         .parent         = &sys_ck,
 656         .rate           = 54000000,
 657         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 658                                 RATE_FIXED | RATE_PROPAGATES,
 659         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 660         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 661         .recalc         = &omap2_propagate_rate,
 662 };
 663
 664 /*
 665  * PRCM digital base sources
 666  */
 667 static struct clk func_54m_ck = {
 668         .name           = "func_54m_ck",
 669         .parent         = &apll54_ck,   /* can also be alt_clk */
 670         .rate           = 54000000,
 671         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 672                                 RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
 673         .src_offset     = 5,
 674         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 675         .enable_bit     = PARENT_CONTROLS_CLOCK,
 676         .recalc         = &omap2_propagate_rate,
 677 };
 678
 679 static struct clk core_ck = {
 680         .name           = "core_ck",
 681         .parent         = &dpll_ck,             /* can also be 32k */
 682         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 683                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 684         .recalc         = &omap2_propagate_rate,
 685 };
 686
 687 static struct clk func_96m_ck = {
 688         .name           = "func_96m_ck",
 689         .parent         = &apll96_ck,
 690         .rate           = 96000000,
 691         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 692                                 RATE_FIXED | RATE_PROPAGATES,
 693         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 694         .enable_bit     = PARENT_CONTROLS_CLOCK,
 695         .recalc         = &omap2_propagate_rate,
 696 };
 697
 698 static struct clk func_48m_ck = {
 699         .name           = "func_48m_ck",
 700         .parent         = &apll96_ck,    /* 96M or Alt */
 701         .rate           = 48000000,
 702         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 703                                 RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
 704         .src_offset     = 3,
 705         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 706         .enable_bit     = PARENT_CONTROLS_CLOCK,
 707         .recalc         = &omap2_propagate_rate,
 708 };
 709
 710 static struct clk func_12m_ck = {
 711         .name           = "func_12m_ck",
 712         .parent         = &func_48m_ck,
 713         .rate           = 12000000,
 714         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 715                                 RATE_FIXED | RATE_PROPAGATES,
 716         .recalc         = &omap2_propagate_rate,
 717         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 718         .enable_bit     = PARENT_CONTROLS_CLOCK,
 719 };
 720
 721 /* Secure timer, only available in secure mode */
 722 static struct clk wdt1_osc_ck = {
 723         .name           = "ck_wdt1_osc",
 724         .parent         = &osc_ck,
 725         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 726         .recalc         = &omap2_followparent_recalc,
 727 };
 728
 729 static struct clk sys_clkout = {
 730         .name           = "sys_clkout",
 731         .parent         = &func_54m_ck,
 732         .rate           = 54000000,
 733         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 734                                 CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
 735         .src_offset     = 0,
 736         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 737         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 738         .rate_offset    = 3,
 739         .recalc         = &omap2_clksel_recalc,
 740 };
 741
 742 /* In 2430, new in 2420 ES2 */
 743 static struct clk sys_clkout2 = {
 744         .name           = "sys_clkout2",
 745         .parent         = &func_54m_ck,
 746         .rate           = 54000000,
 747         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 748                                 CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
 749         .src_offset     = 8,
 750         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 751         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 752         .rate_offset    = 11,
 753         .recalc         = &omap2_clksel_recalc,
 754 };
 755
 756 static struct clk emul_ck = {
 757         .name           = "emul_ck",
 758         .parent         = &func_54m_ck,
 759         .flags          = CLOCK_IN_OMAP242X,
 760         .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL,
 761         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 762         .recalc         = &omap2_propagate_rate,
 763
 764 };
 765
 766 /*
 767  * MPU clock domain
 768  *      Clocks:
 769  *              MPU_FCLK, MPU_ICLK
 770  *              INT_M_FCLK, INT_M_I_CLK
 771  *
 772  * - Individual clocks are hardware managed.
 773  * - Base divider comes from: CM_CLKSEL_MPU
 774  *
 775  */
 776 static struct clk mpu_ck = {    /* Control cpu */
 777         .name           = "mpu_ck",
 778         .parent         = &core_ck,
 779         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL |
 780                                 ALWAYS_ENABLED | CM_MPU_SEL1 | DELAYED_APP |
 781                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
 782         .rate_offset    = 0,    /* bits 0-4 */
 783         .recalc         = &omap2_clksel_recalc,
 784 };
 785
 786 /*
 787  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
 788  * Clocks:
 789  *      2430: IVA2.1_FCLK, IVA2.1_ICLK
 790  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
 791  */
 792 static struct clk iva2_1_fck = {
 793         .name           = "iva2_1_fck",
 794         .parent         = &core_ck,
 795         .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
 796                                 DELAYED_APP | RATE_PROPAGATES |
 797                                 CONFIG_PARTICIPANT,
 798         .rate_offset    = 0,
 799         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 800         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
 801         .recalc         = &omap2_clksel_recalc,
 802 };
 803
 804 static struct clk iva2_1_ick = {
 805         .name           = "iva2_1_ick",
 806         .parent         = &iva2_1_fck,
 807         .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
 808                                 DELAYED_APP | CONFIG_PARTICIPANT,
 809         .rate_offset    = 5,
 810         .recalc         = &omap2_clksel_recalc,
 811 };
 812
 813 /*
 814  * Won't be too specific here. The core clock comes into this block
 815  * it is divided then tee'ed. One branch goes directly to xyz enable
 816  * controls. The other branch gets further divided by 2 then possibly
 817  * routed into a synchronizer and out of clocks abc.
 818  */
 819 static struct clk dsp_fck = {
 820         .name           = "dsp_fck",
 821         .parent         = &core_ck,
 822         .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
 823                         DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
 824         .rate_offset    = 0,
 825         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 826         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
 827         .recalc         = &omap2_clksel_recalc,
 828 };
 829
 830 static struct clk dsp_ick = {
 831         .name           = "dsp_ick",     /* apparently ipi and isp */
 832         .parent         = &dsp_fck,
 833         .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
 834                                 DELAYED_APP | CONFIG_PARTICIPANT,
 835         .rate_offset    = 5,
 836         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
 837         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,            /* for ipi */
 838         .recalc         = &omap2_clksel_recalc,
 839 };
 840
 841 static struct clk iva1_ifck = {
 842         .name           = "iva1_ifck",
 843         .parent         = &core_ck,
 844         .flags          = CLOCK_IN_OMAP242X | CM_DSP_SEL1 | RATE_CKCTL |
 845                         CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
 846         .rate_offset    = 8,
 847         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 848         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
 849         .recalc         = &omap2_clksel_recalc,
 850 };
 851
 852 /* IVA1 mpu/int/i/f clocks are /2 of parent */
 853 static struct clk iva1_mpu_int_ifck = {
 854         .name           = "iva1_mpu_int_ifck",
 855         .parent         = &iva1_ifck,
 856         .flags          = CLOCK_IN_OMAP242X,
 857         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 858         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
 859         .recalc         = &omap2_clksel_recalc,
 860 };
 861
 862 /*
 863  * L3 clock domain
 864  * L3 clocks are used for both interface and functional clocks to
 865  * multiple entities. Some of these clocks are completely managed
 866  * by hardware, and some others allow software control. Hardware
 867  * managed ones general are based on directly CLK_REQ signals and
 868  * various auto idle settings. The functional spec sets many of these
 869  * as 'tie-high' for their enables.
 870  *
 871  * I-CLOCKS:
 872  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
 873  *      CAM, HS-USB.
 874  * F-CLOCK
 875  *      SSI.
 876  *
 877  * GPMC memories and SDRC have timing and clock sensitive registers which
 878  * may very well need notification when the clock changes. Currently for low
 879  * operating points, these are taken care of in sleep.S.
 880  */
 881 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
 882         .name           = "core_l3_ck",
 883         .parent         = &core_ck,
 884         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 885                                 RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
 886                                 DELAYED_APP | CONFIG_PARTICIPANT |
 887                                 RATE_PROPAGATES,
 888         .rate_offset    = 0,
 889         .recalc         = &omap2_clksel_recalc,
 890 };
 891
 892 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
 893         .name           = "usb_l4_ick",
 894         .parent         = &core_l3_ck,
 895         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 896                                 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP |
 897                                 CONFIG_PARTICIPANT,
 898         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 899         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
 900         .rate_offset    = 25,
 901         .recalc         = &omap2_clksel_recalc,
 902 };
 903
 904 /*
 905  * SSI is in L3 management domain, its direct parent is core not l3,
 906  * many core power domain entities are grouped into the L3 clock
 907  * domain.
 908  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
 909  *
 910  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
 911  */
 912 static struct clk ssi_ssr_sst_fck = {
 913         .name           = "ssi_fck",
 914         .parent         = &core_ck,
 915         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 916                                 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
 917         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),       /* bit 1 */
 918         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
 919         .rate_offset    = 20,
 920         .recalc         = &omap2_clksel_recalc,
 921 };
 922
 923 /*
 924  * GFX clock domain
 925  *      Clocks:
 926  * GFX_FCLK, GFX_ICLK
 927  * GFX_CG1(2d), GFX_CG2(3d)
 928  *
 929  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
 930  * The 2d and 3d clocks run at a hardware determined
 931  * divided value of fclk.
 932  *
 933  */
 934 static struct clk gfx_3d_fck = {
 935         .name           = "gfx_3d_fck",
 936         .parent         = &core_l3_ck,
 937         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 938                                 RATE_CKCTL | CM_GFX_SEL1,
 939         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
 940         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
 941         .rate_offset    = 0,
 942         .recalc         = &omap2_clksel_recalc,
 943 };
 944
 945 static struct clk gfx_2d_fck = {
 946         .name           = "gfx_2d_fck",
 947         .parent         = &core_l3_ck,
 948         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 949                                 RATE_CKCTL | CM_GFX_SEL1,
 950         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
 951         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
 952         .rate_offset    = 0,
 953         .recalc         = &omap2_clksel_recalc,
 954 };
 955
 956 static struct clk gfx_ick = {
 957         .name           = "gfx_ick",            /* From l3 */
 958         .parent         = &core_l3_ck,
 959         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 960         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),  /* bit 0 */
 961         .enable_bit     = OMAP_EN_GFX_SHIFT,
 962         .recalc         = &omap2_followparent_recalc,
 963 };
 964
 965 /*
 966  * Modem clock domain (2430)
 967  *      CLOCKS:
 968  *              MDM_OSC_CLK
 969  *              MDM_ICLK
 970  */
 971 static struct clk mdm_ick = {           /* used both as a ick and fck */
 972         .name           = "mdm_ick",
 973         .parent         = &core_ck,
 974         .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_MODEM_SEL1 |
 975                                 DELAYED_APP | CONFIG_PARTICIPANT,
 976         .rate_offset    = 0,
 977         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
 978         .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
 979         .recalc         = &omap2_clksel_recalc,
 980 };
 981
 982 static struct clk mdm_osc_ck = {
 983         .name           = "mdm_osc_ck",
 984         .rate           = 26000000,
 985         .parent         = &osc_ck,
 986         .flags          = CLOCK_IN_OMAP243X | RATE_FIXED,
 987         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, OMAP24XX_CM_FCLKEN),
 988         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
 989         .recalc         = &omap2_followparent_recalc,
 990 };
 991
 992 /*
 993  * L4 clock management domain
 994  *
 995  * This domain contains lots of interface clocks from the L4 interface, some
 996  * functional clocks.   Fixed APLL functional source clocks are managed in
 997  * this domain.
 998  */
 999 static struct clk l4_ck = {             /* used both as an ick and fck */
1000         .name           = "l4_ck",
1001         .parent         = &core_l3_ck,
1002         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1003                                 RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
1004                                 DELAYED_APP | RATE_PROPAGATES,
1005         .rate_offset    = 5,
1006         .recalc         = &omap2_clksel_recalc,
1007 };
1008
1009 static struct clk ssi_l4_ick = {
1010         .name           = "ssi_l4_ick",
1011         .parent         = &l4_ck,
1012         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1013         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),        /* bit 1 */
1014         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1015         .recalc         = &omap2_followparent_recalc,
1016 };
1017
1018 /*
1019  * DSS clock domain
1020  * CLOCKs:
1021  * DSS_L4_ICLK, DSS_L3_ICLK,
1022  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1023  *
1024  * DSS is both initiator and target.
1025  */
1026 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1027         .name           = "dss_ick",
1028         .parent         = &l4_ck,       /* really both l3 and l4 */
1029         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1030         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1031         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1032         .recalc         = &omap2_followparent_recalc,
1033 };
1034
1035 static struct clk dss1_fck = {
1036         .name           = "dss1_fck",
1037         .parent         = &core_ck,             /* Core or sys */
1038         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1039                                 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
1040         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1041         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1042         .rate_offset    = 8,
1043         .src_offset     = 8,
1044         .recalc         = &omap2_clksel_recalc,
1045 };
1046
1047 static struct clk dss2_fck = {          /* Alt clk used in power management */
1048         .name           = "dss2_fck",
1049         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1050         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1051                                 RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED |
1052                                 DELAYED_APP,
1053         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1054         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
1055         .src_offset     = 13,
1056         .recalc         = &omap2_followparent_recalc,
1057 };
1058
1059 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1060         .name           = "dss_54m_fck",        /* 54m tv clk */
1061         .parent         = &func_54m_ck,
1062         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1063         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1064         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
1065         .recalc         = &omap2_followparent_recalc,
1066 };
1067
1068 /*
1069  * CORE power domain ICLK & FCLK defines.
1070  * Many of the these can have more than one possible parent. Entries
1071  * here will likely have an L4 interface parent, and may have multiple
1072  * functional clock parents.
1073  */
1074 static struct clk gpt1_ick = {
1075         .name           = "gpt1_ick",
1076         .parent         = &l4_ck,
1077         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1078         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), /* Bit0 */
1079         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1080         .recalc         = &omap2_followparent_recalc,
1081 };
1082
1083 static struct clk gpt1_fck = {
1084         .name           = "gpt1_fck",
1085         .parent         = &func_32k_ck,
1086         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1087                                 CM_WKUP_SEL1,
1088         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),        /* Bit0 */
1089         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1090         .src_offset     = 0,
1091         .recalc         = &omap2_followparent_recalc,
1092 };
1093
1094 static struct clk gpt2_ick = {
1095         .name           = "gpt2_ick",
1096         .parent         = &l4_ck,
1097         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1098         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit4 */
1099         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1100         .recalc         = &omap2_followparent_recalc,
1101 };
1102
1103 static struct clk gpt2_fck = {
1104         .name           = "gpt2_fck",
1105         .parent         = &func_32k_ck,
1106         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1107                                 CM_CORE_SEL2,
1108         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1109         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1110         .src_offset     = 2,
1111         .recalc         = &omap2_followparent_recalc,
1112 };
1113
1114 static struct clk gpt3_ick = {
1115         .name           = "gpt3_ick",
1116         .parent         = &l4_ck,
1117         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1118         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit5 */
1119         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1120         .recalc         = &omap2_followparent_recalc,
1121 };
1122
1123 static struct clk gpt3_fck = {
1124         .name           = "gpt3_fck",
1125         .parent         = &func_32k_ck,
1126         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1127                                 CM_CORE_SEL2,
1128         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1129         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1130         .src_offset     = 4,
1131         .recalc         = &omap2_followparent_recalc,
1132 };
1133
1134 static struct clk gpt4_ick = {
1135         .name           = "gpt4_ick",
1136         .parent         = &l4_ck,
1137         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1138         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit6 */
1139         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1140         .recalc         = &omap2_followparent_recalc,
1141 };
1142
1143 static struct clk gpt4_fck = {
1144         .name           = "gpt4_fck",
1145         .parent         = &func_32k_ck,
1146         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1147                                 CM_CORE_SEL2,
1148         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1149         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1150         .src_offset     = 6,
1151         .recalc         = &omap2_followparent_recalc,
1152 };
1153
1154 static struct clk gpt5_ick = {
1155         .name           = "gpt5_ick",
1156         .parent         = &l4_ck,
1157         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1158         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* Bit7 */
1159         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1160         .recalc         = &omap2_followparent_recalc,
1161 };
1162
1163 static struct clk gpt5_fck = {
1164         .name           = "gpt5_fck",
1165         .parent         = &func_32k_ck,
1166         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1167                                 CM_CORE_SEL2,
1168         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1169         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1170         .src_offset     = 8,
1171         .recalc         = &omap2_followparent_recalc,
1172 };
1173
1174 static struct clk gpt6_ick = {
1175         .name           = "gpt6_ick",
1176         .parent         = &l4_ck,
1177         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1178         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1179         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit8 */
1180         .recalc         = &omap2_followparent_recalc,
1181 };
1182
1183 static struct clk gpt6_fck = {
1184         .name           = "gpt6_fck",
1185         .parent         = &func_32k_ck,
1186         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1187                                 CM_CORE_SEL2,
1188         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1189         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1190         .src_offset     = 10,
1191         .recalc         = &omap2_followparent_recalc,
1192 };
1193
1194 static struct clk gpt7_ick = {
1195         .name           = "gpt7_ick",
1196         .parent         = &l4_ck,
1197         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1198         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit9 */
1199         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1200         .recalc         = &omap2_followparent_recalc,
1201 };
1202
1203 static struct clk gpt7_fck = {
1204         .name           = "gpt7_fck",
1205         .parent         = &func_32k_ck,
1206         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1207                                 CM_CORE_SEL2,
1208         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1209         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1210         .src_offset     = 12,
1211         .recalc         = &omap2_followparent_recalc,
1212 };
1213
1214 static struct clk gpt8_ick = {
1215         .name           = "gpt8_ick",
1216         .parent         = &l4_ck,
1217         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1218         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit10 */
1219         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1220         .recalc         = &omap2_followparent_recalc,
1221 };
1222
1223 static struct clk gpt8_fck = {
1224         .name           = "gpt8_fck",
1225         .parent         = &func_32k_ck,
1226         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1227                                 CM_CORE_SEL2,
1228         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1229         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1230         .src_offset     = 14,
1231         .recalc         = &omap2_followparent_recalc,
1232 };
1233
1234 static struct clk gpt9_ick = {
1235         .name           = "gpt9_ick",
1236         .parent         = &l4_ck,
1237         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1238         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1239         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1240         .recalc         = &omap2_followparent_recalc,
1241 };
1242
1243 static struct clk gpt9_fck = {
1244         .name           = "gpt9_fck",
1245         .parent         = &func_32k_ck,
1246         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1247                                         CM_CORE_SEL2,
1248         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1249         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1250         .src_offset     = 16,
1251         .recalc         = &omap2_followparent_recalc,
1252 };
1253
1254 static struct clk gpt10_ick = {
1255         .name           = "gpt10_ick",
1256         .parent         = &l4_ck,
1257         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1258         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1259         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1260         .recalc         = &omap2_followparent_recalc,
1261 };
1262
1263 static struct clk gpt10_fck = {
1264         .name           = "gpt10_fck",
1265         .parent         = &func_32k_ck,
1266         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1267                                         CM_CORE_SEL2,
1268         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1269         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1270         .src_offset     = 18,
1271         .recalc         = &omap2_followparent_recalc,
1272 };
1273
1274 static struct clk gpt11_ick = {
1275         .name           = "gpt11_ick",
1276         .parent         = &l4_ck,
1277         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1278         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1279         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1280         .recalc         = &omap2_followparent_recalc,
1281 };
1282
1283 static struct clk gpt11_fck = {
1284         .name           = "gpt11_fck",
1285         .parent         = &func_32k_ck,
1286         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1287                                         CM_CORE_SEL2,
1288         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1289         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1290         .src_offset     = 20,
1291         .recalc         = &omap2_followparent_recalc,
1292 };
1293
1294 static struct clk gpt12_ick = {
1295         .name           = "gpt12_ick",
1296         .parent         = &l4_ck,
1297         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1298         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit14 */
1299         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1300         .recalc         = &omap2_followparent_recalc,
1301 };
1302
1303 static struct clk gpt12_fck = {
1304         .name           = "gpt12_fck",
1305         .parent         = &func_32k_ck,
1306         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1307                                         CM_CORE_SEL2,
1308         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1309         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1310         .src_offset     = 22,
1311         .recalc         = &omap2_followparent_recalc,
1312 };
1313
1314 /* REVISIT: bit comment below wrong? */
1315 static struct clk mcbsp1_ick = {
1316         .name           = "mcbsp1_ick",
1317         .parent         = &l4_ck,
1318         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1319         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit16 */
1320         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1321         .recalc         = &omap2_followparent_recalc,
1322 };
1323
1324 static struct clk mcbsp1_fck = {
1325         .name           = "mcbsp1_fck",
1326         .parent         = &func_96m_ck,
1327         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1328         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1329         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1330         .recalc         = &omap2_followparent_recalc,
1331 };
1332
1333 static struct clk mcbsp2_ick = {
1334         .name           = "mcbsp2_ick",
1335         .parent         = &l4_ck,
1336         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1337         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1338         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1339         .recalc         = &omap2_followparent_recalc,
1340 };
1341
1342 static struct clk mcbsp2_fck = {
1343         .name           = "mcbsp2_fck",
1344         .parent         = &func_96m_ck,
1345         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1346         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1347         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1348         .recalc         = &omap2_followparent_recalc,
1349 };
1350
1351 static struct clk mcbsp3_ick = {
1352         .name           = "mcbsp3_ick",
1353         .parent         = &l4_ck,
1354         .flags          = CLOCK_IN_OMAP243X,
1355         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1356         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1357         .recalc         = &omap2_followparent_recalc,
1358 };
1359
1360 static struct clk mcbsp3_fck = {
1361         .name           = "mcbsp3_fck",
1362         .parent         = &func_96m_ck,
1363         .flags          = CLOCK_IN_OMAP243X,
1364         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1365         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1366         .recalc         = &omap2_followparent_recalc,
1367 };
1368
1369 static struct clk mcbsp4_ick = {
1370         .name           = "mcbsp4_ick",
1371         .parent         = &l4_ck,
1372         .flags          = CLOCK_IN_OMAP243X,
1373         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1374         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1375         .recalc         = &omap2_followparent_recalc,
1376 };
1377
1378 static struct clk mcbsp4_fck = {
1379         .name           = "mcbsp4_fck",
1380         .parent         = &func_96m_ck,
1381         .flags          = CLOCK_IN_OMAP243X,
1382         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1383         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1384         .recalc         = &omap2_followparent_recalc,
1385 };
1386
1387 static struct clk mcbsp5_ick = {
1388         .name           = "mcbsp5_ick",
1389         .parent         = &l4_ck,
1390         .flags          = CLOCK_IN_OMAP243X,
1391         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1392         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1393         .recalc         = &omap2_followparent_recalc,
1394 };
1395
1396 static struct clk mcbsp5_fck = {
1397         .name           = "mcbsp5_fck",
1398         .parent         = &func_96m_ck,
1399         .flags          = CLOCK_IN_OMAP243X,
1400         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1401         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1402         .recalc         = &omap2_followparent_recalc,
1403 };
1404
1405 static struct clk mcspi1_ick = {
1406         .name           = "mcspi_ick",
1407         .id             = 1,
1408         .parent         = &l4_ck,
1409         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1410         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1411         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1412         .recalc         = &omap2_followparent_recalc,
1413 };
1414
1415 static struct clk mcspi1_fck = {
1416         .name           = "mcspi_fck",
1417         .id             = 1,
1418         .parent         = &func_48m_ck,
1419         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1420         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1421         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1422         .recalc         = &omap2_followparent_recalc,
1423 };
1424
1425 static struct clk mcspi2_ick = {
1426         .name           = "mcspi_ick",
1427         .id             = 2,
1428         .parent         = &l4_ck,
1429         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1430         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1431         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1432         .recalc         = &omap2_followparent_recalc,
1433 };
1434
1435 static struct clk mcspi2_fck = {
1436         .name           = "mcspi_fck",
1437         .id             = 2,
1438         .parent         = &func_48m_ck,
1439         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1440         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1441         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1442         .recalc         = &omap2_followparent_recalc,
1443 };
1444
1445 static struct clk mcspi3_ick = {
1446         .name           = "mcspi_ick",
1447         .id             = 3,
1448         .parent         = &l4_ck,
1449         .flags          = CLOCK_IN_OMAP243X,
1450         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1451         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1452         .recalc         = &omap2_followparent_recalc,
1453 };
1454
1455 static struct clk mcspi3_fck = {
1456         .name           = "mcspi_fck",
1457         .id             = 3,
1458         .parent         = &func_48m_ck,
1459         .flags          = CLOCK_IN_OMAP243X,
1460         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1461         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1462         .recalc         = &omap2_followparent_recalc,
1463 };
1464
1465 static struct clk uart1_ick = {
1466         .name           = "uart1_ick",
1467         .parent         = &l4_ck,
1468         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1469         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1470         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1471         .recalc         = &omap2_followparent_recalc,
1472 };
1473
1474 static struct clk uart1_fck = {
1475         .name           = "uart1_fck",
1476         .parent         = &func_48m_ck,
1477         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1478         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1479         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1480         .recalc         = &omap2_followparent_recalc,
1481 };
1482
1483 static struct clk uart2_ick = {
1484         .name           = "uart2_ick",
1485         .parent         = &l4_ck,
1486         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1487         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1488         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1489         .recalc         = &omap2_followparent_recalc,
1490 };
1491
1492 static struct clk uart2_fck = {
1493         .name           = "uart2_fck",
1494         .parent         = &func_48m_ck,
1495         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1496         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1497         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1498         .recalc         = &omap2_followparent_recalc,
1499 };
1500
1501 static struct clk uart3_ick = {
1502         .name           = "uart3_ick",
1503         .parent         = &l4_ck,
1504         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1505         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1506         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1507         .recalc         = &omap2_followparent_recalc,
1508 };
1509
1510 static struct clk uart3_fck = {
1511         .name           = "uart3_fck",
1512         .parent         = &func_48m_ck,
1513         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1514         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1515         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1516         .recalc         = &omap2_followparent_recalc,
1517 };
1518
1519 static struct clk gpios_ick = {
1520         .name           = "gpios_ick",
1521         .parent         = &l4_ck,
1522         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1523         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1524         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1525         .recalc         = &omap2_followparent_recalc,
1526 };
1527
1528 static struct clk gpios_fck = {
1529         .name           = "gpios_fck",
1530         .parent         = &func_32k_ck,
1531         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1532         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
1533         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1534         .recalc         = &omap2_followparent_recalc,
1535 };
1536
1537 static struct clk mpu_wdt_ick = {
1538         .name           = "mpu_wdt_ick",
1539         .parent         = &l4_ck,
1540         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1541         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1542         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
1543         .recalc         = &omap2_followparent_recalc,
1544 };
1545
1546 static struct clk mpu_wdt_fck = {
1547         .name           = "mpu_wdt_fck",
1548         .parent         = &func_32k_ck,
1549         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1550         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
1551         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
1552         .recalc         = &omap2_followparent_recalc,
1553 };
1554
1555 static struct clk sync_32k_ick = {
1556         .name           = "sync_32k_ick",
1557         .parent         = &l4_ck,
1558         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1559         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1560         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
1561         .recalc         = &omap2_followparent_recalc,
1562 };
1563 static struct clk wdt1_ick = {
1564         .name           = "wdt1_ick",
1565         .parent         = &l4_ck,
1566         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1567         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1568         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
1569         .recalc         = &omap2_followparent_recalc,
1570 };
1571 static struct clk omapctrl_ick = {
1572         .name           = "omapctrl_ick",
1573         .parent         = &l4_ck,
1574         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1575         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1576         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
1577         .recalc         = &omap2_followparent_recalc,
1578 };
1579 static struct clk icr_ick = {
1580         .name           = "icr_ick",
1581         .parent         = &l4_ck,
1582         .flags          = CLOCK_IN_OMAP243X,
1583         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1584         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
1585         .recalc         = &omap2_followparent_recalc,
1586 };
1587
1588 static struct clk cam_ick = {
1589         .name           = "cam_ick",
1590         .parent         = &l4_ck,
1591         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1592         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1593         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
1594         .recalc         = &omap2_followparent_recalc,
1595 };
1596
1597 static struct clk cam_fck = {
1598         .name           = "cam_fck",
1599         .parent         = &func_96m_ck,
1600         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1601         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1602         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
1603         .recalc         = &omap2_followparent_recalc,
1604 };
1605
1606 static struct clk mailboxes_ick = {
1607         .name           = "mailboxes_ick",
1608         .parent         = &l4_ck,
1609         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1610         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1611         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
1612         .recalc         = &omap2_followparent_recalc,
1613 };
1614
1615 static struct clk wdt4_ick = {
1616         .name           = "wdt4_ick",
1617         .parent         = &l4_ck,
1618         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1619         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1620         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
1621         .recalc         = &omap2_followparent_recalc,
1622 };
1623
1624 static struct clk wdt4_fck = {
1625         .name           = "wdt4_fck",
1626         .parent         = &func_32k_ck,
1627         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1628         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1629         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
1630         .recalc         = &omap2_followparent_recalc,
1631 };
1632
1633 static struct clk wdt3_ick = {
1634         .name           = "wdt3_ick",
1635         .parent         = &l4_ck,
1636         .flags          = CLOCK_IN_OMAP242X,
1637         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1638         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
1639         .recalc         = &omap2_followparent_recalc,
1640 };
1641
1642 static struct clk wdt3_fck = {
1643         .name           = "wdt3_fck",
1644         .parent         = &func_32k_ck,
1645         .flags          = CLOCK_IN_OMAP242X,
1646         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1647         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
1648         .recalc         = &omap2_followparent_recalc,
1649 };
1650
1651 static struct clk mspro_ick = {
1652         .name           = "mspro_ick",
1653         .parent         = &l4_ck,
1654         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1655         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1656         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
1657         .recalc         = &omap2_followparent_recalc,
1658 };
1659
1660 static struct clk mspro_fck = {
1661         .name           = "mspro_fck",
1662         .parent         = &func_96m_ck,
1663         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1664         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1665         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
1666         .recalc         = &omap2_followparent_recalc,
1667 };
1668
1669 static struct clk mmc_ick = {
1670         .name           = "mmc_ick",
1671         .parent         = &l4_ck,
1672         .flags          = CLOCK_IN_OMAP242X,
1673         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1674         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
1675         .recalc         = &omap2_followparent_recalc,
1676 };
1677
1678 static struct clk mmc_fck = {
1679         .name           = "mmc_fck",
1680         .parent         = &func_96m_ck,
1681         .flags          = CLOCK_IN_OMAP242X,
1682         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1683         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
1684         .recalc         = &omap2_followparent_recalc,
1685 };
1686
1687 static struct clk fac_ick = {
1688         .name           = "fac_ick",
1689         .parent         = &l4_ck,
1690         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1691         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1692         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
1693         .recalc         = &omap2_followparent_recalc,
1694 };
1695
1696 static struct clk fac_fck = {
1697         .name           = "fac_fck",
1698         .parent         = &func_12m_ck,
1699         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1700         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1701         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
1702         .recalc         = &omap2_followparent_recalc,
1703 };
1704
1705 static struct clk eac_ick = {
1706         .name           = "eac_ick",
1707         .parent         = &l4_ck,
1708         .flags          = CLOCK_IN_OMAP242X,
1709         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1710         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
1711         .recalc         = &omap2_followparent_recalc,
1712 };
1713
1714 static struct clk eac_fck = {
1715         .name           = "eac_fck",
1716         .parent         = &func_96m_ck,
1717         .flags          = CLOCK_IN_OMAP242X,
1718         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1719         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
1720         .recalc         = &omap2_followparent_recalc,
1721 };
1722
1723 static struct clk hdq_ick = {
1724         .name           = "hdq_ick",
1725         .parent         = &l4_ck,
1726         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1727         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1728         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
1729         .recalc         = &omap2_followparent_recalc,
1730 };
1731
1732 static struct clk hdq_fck = {
1733         .name           = "hdq_fck",
1734         .parent         = &func_12m_ck,
1735         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1736         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1737         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
1738         .recalc         = &omap2_followparent_recalc,
1739 };
1740
1741 static struct clk i2c2_ick = {
1742         .name           = "i2c_ick",
1743         .id             = 2,
1744         .parent         = &l4_ck,
1745         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1746         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1747         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
1748         .recalc         = &omap2_followparent_recalc,
1749 };
1750
1751 static struct clk i2c2_fck = {
1752         .name           = "i2c_fck",
1753         .id             = 2,
1754         .parent         = &func_12m_ck,
1755         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1756         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1757         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
1758         .recalc         = &omap2_followparent_recalc,
1759 };
1760
1761 static struct clk i2chs2_fck = {
1762         .name           = "i2chs_fck",
1763         .id             = 2,
1764         .parent         = &func_96m_ck,
1765         .flags          = CLOCK_IN_OMAP243X,
1766         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1767         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
1768         .recalc         = &omap2_followparent_recalc,
1769 };
1770
1771 static struct clk i2c1_ick = {
1772         .name           = "i2c_ick",
1773         .id             = 1,
1774         .parent         = &l4_ck,
1775         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1776         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1777         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
1778         .recalc         = &omap2_followparent_recalc,
1779 };
1780
1781 static struct clk i2c1_fck = {
1782         .name           = "i2c_fck",
1783         .id             = 1,
1784         .parent         = &func_12m_ck,
1785         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1786         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1787         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
1788         .recalc         = &omap2_followparent_recalc,
1789 };
1790
1791 static struct clk i2chs1_fck = {
1792         .name           = "i2chs_fck",
1793         .id             = 1,
1794         .parent         = &func_96m_ck,
1795         .flags          = CLOCK_IN_OMAP243X,
1796         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1797         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
1798         .recalc         = &omap2_followparent_recalc,
1799 };
1800
1801 static struct clk vlynq_ick = {
1802         .name           = "vlynq_ick",
1803         .parent         = &core_l3_ck,
1804         .flags          = CLOCK_IN_OMAP242X,
1805         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1806         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
1807         .recalc         = &omap2_followparent_recalc,
1808 };
1809
1810 static struct clk vlynq_fck = {
1811         .name           = "vlynq_fck",
1812         .parent         = &func_96m_ck,
1813         .flags          = CLOCK_IN_OMAP242X  | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
1814         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1815         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
1816         .src_offset     = 15,
1817         .recalc         = &omap2_clksel_recalc,
1818 };
1819
1820 static struct clk sdrc_ick = {
1821         .name           = "sdrc_ick",
1822         .parent         = &l4_ck,
1823         .flags          = CLOCK_IN_OMAP243X,
1824         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP2430_CM_ICLKEN3),
1825         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
1826         .recalc         = &omap2_followparent_recalc,
1827 };
1828
1829 static struct clk des_ick = {
1830         .name           = "des_ick",
1831         .parent         = &l4_ck,
1832         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1833         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1834         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
1835         .recalc         = &omap2_followparent_recalc,
1836 };
1837
1838 static struct clk sha_ick = {
1839         .name           = "sha_ick",
1840         .parent         = &l4_ck,
1841         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1842         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1843         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
1844         .recalc         = &omap2_followparent_recalc,
1845 };
1846
1847 static struct clk rng_ick = {
1848         .name           = "rng_ick",
1849         .parent         = &l4_ck,
1850         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1851         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1852         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
1853         .recalc         = &omap2_followparent_recalc,
1854 };
1855
1856 static struct clk aes_ick = {
1857         .name           = "aes_ick",
1858         .parent         = &l4_ck,
1859         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1860         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1861         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
1862         .recalc         = &omap2_followparent_recalc,
1863 };
1864
1865 static struct clk pka_ick = {
1866         .name           = "pka_ick",
1867         .parent         = &l4_ck,
1868         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1869         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1870         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
1871         .recalc         = &omap2_followparent_recalc,
1872 };
1873
1874 static struct clk usb_fck = {
1875         .name           = "usb_fck",
1876         .parent         = &func_48m_ck,
1877         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1878         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1879         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1880         .recalc         = &omap2_followparent_recalc,
1881 };
1882
1883 static struct clk usbhs_ick = {
1884         .name           = "usbhs_ick",
1885         .parent         = &core_l3_ck,
1886         .flags          = CLOCK_IN_OMAP243X,
1887         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1888         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
1889         .recalc         = &omap2_followparent_recalc,
1890 };
1891
1892 static struct clk mmchs1_ick = {
1893         .name           = "mmchs1_ick",
1894         .parent         = &l4_ck,
1895         .flags          = CLOCK_IN_OMAP243X,
1896         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1897         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
1898         .recalc         = &omap2_followparent_recalc,
1899 };
1900
1901 static struct clk mmchs1_fck = {
1902         .name           = "mmchs1_fck",
1903         .parent         = &func_96m_ck,
1904         .flags          = CLOCK_IN_OMAP243X,
1905         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1906         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
1907         .recalc         = &omap2_followparent_recalc,
1908 };
1909
1910 static struct clk mmchs2_ick = {
1911         .name           = "mmchs2_ick",
1912         .parent         = &l4_ck,
1913         .flags          = CLOCK_IN_OMAP243X,
1914         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1915         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
1916         .recalc         = &omap2_followparent_recalc,
1917 };
1918
1919 static struct clk mmchs2_fck = {
1920         .name           = "mmchs2_fck",
1921         .parent         = &func_96m_ck,
1922         .flags          = CLOCK_IN_OMAP243X,
1923         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1924         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
1925         .recalc         = &omap2_followparent_recalc,
1926 };
1927
1928 static struct clk gpio5_ick = {
1929         .name           = "gpio5_ick",
1930         .parent         = &l4_ck,
1931         .flags          = CLOCK_IN_OMAP243X,
1932         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1933         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
1934         .recalc         = &omap2_followparent_recalc,
1935 };
1936
1937 static struct clk gpio5_fck = {
1938         .name           = "gpio5_fck",
1939         .parent         = &func_32k_ck,
1940         .flags          = CLOCK_IN_OMAP243X,
1941         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1942         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
1943         .recalc         = &omap2_followparent_recalc,
1944 };
1945
1946 static struct clk mdm_intc_ick = {
1947         .name           = "mdm_intc_ick",
1948         .parent         = &l4_ck,
1949         .flags          = CLOCK_IN_OMAP243X,
1950         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1951         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
1952         .recalc         = &omap2_followparent_recalc,
1953 };
1954
1955 static struct clk mmchsdb1_fck = {
1956         .name           = "mmchsdb1_fck",
1957         .parent         = &func_32k_ck,
1958         .flags          = CLOCK_IN_OMAP243X,
1959         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1960         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
1961         .recalc         = &omap2_followparent_recalc,
1962 };
1963
1964 static struct clk mmchsdb2_fck = {
1965         .name           = "mmchsdb2_fck",
1966         .parent         = &func_32k_ck,
1967         .flags          = CLOCK_IN_OMAP243X,
1968         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1969         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
1970         .recalc         = &omap2_followparent_recalc,
1971 };
1972
1973 /*
1974  * This clock is a composite clock which does entire set changes then
1975  * forces a rebalance. It keys on the MPU speed, but it really could
1976  * be any key speed part of a set in the rate table.
1977  *
1978  * to really change a set, you need memory table sets which get changed
1979  * in sram, pre-notifiers & post notifiers, changing the top set, without
1980  * having low level display recalc's won't work... this is why dpm notifiers
1981  * work, isr's off, walk a list of clocks already _off_ and not messing with
1982  * the bus.
1983  *
1984  * This clock should have no parent. It embodies the entire upper level
1985  * active set. A parent will mess up some of the init also.
1986  */
1987 static struct clk virt_prcm_set = {
1988         .name           = "virt_prcm_set",
1989         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1990                                 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
1991         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
1992         .recalc         = &omap2_mpu_recalc,    /* sets are keyed on mpu rate */
1993         .set_rate       = &omap2_select_table_rate,
1994         .round_rate     = &omap2_round_to_table_rate,
1995 };
1996
1997 static struct clk *onchip_clks[] = {
1998         /* external root sources */
1999         &func_32k_ck,
2000         &osc_ck,
2001         &sys_ck,
2002         &alt_ck,
2003         /* internal analog sources */
2004         &dpll_ck,
2005         &apll96_ck,
2006         &apll54_ck,
2007         /* internal prcm root sources */
2008         &func_54m_ck,
2009         &core_ck,
2010         &func_96m_ck,
2011         &func_48m_ck,
2012         &func_12m_ck,
2013         &wdt1_osc_ck,
2014         &sys_clkout,
2015         &sys_clkout2,
2016         &emul_ck,
2017         /* mpu domain clocks */
2018         &mpu_ck,
2019         /* dsp domain clocks */
2020         &iva2_1_fck,            /* 2430 */
2021         &iva2_1_ick,
2022         &dsp_ick,               /* 2420 */
2023         &dsp_fck,
2024         &iva1_ifck,
2025         &iva1_mpu_int_ifck,
2026         /* GFX domain clocks */
2027         &gfx_3d_fck,
2028         &gfx_2d_fck,
2029         &gfx_ick,
2030         /* Modem domain clocks */
2031         &mdm_ick,
2032         &mdm_osc_ck,
2033         /* DSS domain clocks */
2034         &dss_ick,
2035         &dss1_fck,
2036         &dss2_fck,
2037         &dss_54m_fck,
2038         /* L3 domain clocks */
2039         &core_l3_ck,
2040         &ssi_ssr_sst_fck,
2041         &usb_l4_ick,
2042         /* L4 domain clocks */
2043         &l4_ck,                 /* used as both core_l4 and wu_l4 */
2044         &ssi_l4_ick,
2045         /* virtual meta-group clock */
2046         &virt_prcm_set,
2047         /* general l4 interface ck, multi-parent functional clk */
2048         &gpt1_ick,
2049         &gpt1_fck,
2050         &gpt2_ick,
2051         &gpt2_fck,
2052         &gpt3_ick,
2053         &gpt3_fck,
2054         &gpt4_ick,
2055         &gpt4_fck,
2056         &gpt5_ick,
2057         &gpt5_fck,
2058         &gpt6_ick,
2059         &gpt6_fck,
2060         &gpt7_ick,
2061         &gpt7_fck,
2062         &gpt8_ick,
2063         &gpt8_fck,
2064         &gpt9_ick,
2065         &gpt9_fck,
2066         &gpt10_ick,
2067         &gpt10_fck,
2068         &gpt11_ick,
2069         &gpt11_fck,
2070         &gpt12_ick,
2071         &gpt12_fck,
2072         &mcbsp1_ick,
2073         &mcbsp1_fck,
2074         &mcbsp2_ick,
2075         &mcbsp2_fck,
2076         &mcbsp3_ick,
2077         &mcbsp3_fck,
2078         &mcbsp4_ick,
2079         &mcbsp4_fck,
2080         &mcbsp5_ick,
2081         &mcbsp5_fck,
2082         &mcspi1_ick,
2083         &mcspi1_fck,
2084         &mcspi2_ick,
2085         &mcspi2_fck,
2086         &mcspi3_ick,
2087         &mcspi3_fck,
2088         &uart1_ick,
2089         &uart1_fck,
2090         &uart2_ick,
2091         &uart2_fck,
2092         &uart3_ick,
2093         &uart3_fck,
2094         &gpios_ick,
2095         &gpios_fck,
2096         &mpu_wdt_ick,
2097         &mpu_wdt_fck,
2098         &sync_32k_ick,
2099         &wdt1_ick,
2100         &omapctrl_ick,
2101         &icr_ick,
2102         &cam_fck,
2103         &cam_ick,
2104         &mailboxes_ick,
2105         &wdt4_ick,
2106         &wdt4_fck,
2107         &wdt3_ick,
2108         &wdt3_fck,
2109         &mspro_ick,
2110         &mspro_fck,
2111         &mmc_ick,
2112         &mmc_fck,
2113         &fac_ick,
2114         &fac_fck,
2115         &eac_ick,
2116         &eac_fck,
2117         &hdq_ick,
2118         &hdq_fck,
2119         &i2c1_ick,
2120         &i2c1_fck,
2121         &i2chs1_fck,
2122         &i2c2_ick,
2123         &i2c2_fck,
2124         &i2chs2_fck,
2125         &vlynq_ick,
2126         &vlynq_fck,
2127         &sdrc_ick,
2128         &des_ick,
2129         &sha_ick,
2130         &rng_ick,
2131         &aes_ick,
2132         &pka_ick,
2133         &usb_fck,
2134         &usbhs_ick,
2135         &mmchs1_ick,
2136         &mmchs1_fck,
2137         &mmchs2_ick,
2138         &mmchs2_fck,
2139         &gpio5_ick,
2140         &gpio5_fck,
2141         &mdm_intc_ick,
2142         &mmchsdb1_fck,
2143         &mmchsdb2_fck,
2144 };
2145
2146 #endif