arch/arm/mach-omap2/clock.h

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock.h
   3  *
   4  *  Copyright (C) 2005 Texas Instruments Inc.
   5  *  Richard Woodruff <r-woodruff2@ti.com>
   6  *  Created for OMAP2.
   7  *
   8  *  Copyright (C) 2004 Nokia corporation
   9  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  10  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
  11  *
  12  *  Copyright (C) 2007 Texas Instruments, Inc.
  13  *  Copyright (C) 2007 Nokia Corporation
  14  *  Paul Walmsley
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
  22 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
  23
  24 #include "prm.h"
  25 #include "cm.h"
  26 #include "prm_regbits_24xx.h"
  27 #include "cm_regbits_24xx.h"
  28
  29 static void omap2_clksel_recalc(struct clk * clk);
  30 static void omap2_table_mpu_recalc(struct clk *clk);
  31 static int omap2_select_table_rate(struct clk * clk, unsigned long rate);
  32 static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate);
  33 static void omap2_clk_disable(struct clk *clk);
  34 static void omap2_sys_clk_recalc(struct clk * clk);
  35 static void omap2_init_clksel_parent(struct clk *clk);
  36 static u32 omap2_clksel_get_divisor(struct clk *clk);
  37 static u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val);
  38 static u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
  39 static void omap2_osc_clk_recalc(struct clk *clk);
  40 static void omap2_sys_clk_recalc(struct clk *clk);
  41 static void omap2_dpll_recalc(struct clk *clk);
  42 static void omap2_fixed_divisor_recalc(struct clk *clk);
  43 static int omap2_clk_fixed_enable(struct clk *clk);
  44 static void omap2_clk_fixed_disable(struct clk *clk);
  45 static long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
  46 static int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
  47 static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate);
  48 static int omap2_enable_osc_ck(struct clk *clk);
  49 static void omap2_disable_osc_ck(struct clk *clk);
  50
  51 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  52  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  53  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  54  */
  55 struct prcm_config {
  56         unsigned long xtal_speed;       /* crystal rate */
  57         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  58         unsigned long mpu_speed;        /* speed of MPU */
  59         unsigned long cm_clksel_mpu;    /* mpu divider */
  60         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  61         unsigned long cm_clksel_gfx;    /* gfx dividers */
  62         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  63         unsigned long cm_clksel1_pll;   /* m,n */
  64         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  65         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  66         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  67         unsigned char flags;
  68 };
  69
  70 /*
  71  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  72  * These configurations are characterized by voltage and speed for clocks.
  73  * The device is only validated for certain combinations. One way to express
  74  * these combinations is via the 'ratio's' which the clocks operate with
  75  * respect to each other. These ratio sets are for a given voltage/DPLL
  76  * setting. All configurations can be described by a DPLL setting and a ratio
  77  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  78  *
  79  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  80  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  81  * 2430 (iva2.1, NOdsp, mdm)
  82  */
  83
  84 /* Core fields for cm_clksel, not ratio governed */
  85 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  86 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  87 #define RX_CLKSEL_SSI                   (0x5 << 20)
  88
  89 /*-------------------------------------------------------------------------
  90  * Voltage/DPLL ratios
  91  *-------------------------------------------------------------------------*/
  92
  93 /* 2430 Ratio's, 2430-Ratio Config 1 */
  94 #define R1_CLKSEL_L3                    (4 << 0)
  95 #define R1_CLKSEL_L4                    (2 << 5)
  96 #define R1_CLKSEL_USB                   (4 << 25)
  97 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
  98                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  99                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
 100 #define R1_CLKSEL_MPU                   (2 << 0)
 101 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
 102 #define R1_CLKSEL_DSP                   (2 << 0)
 103 #define R1_CLKSEL_DSP_IF                (2 << 5)
 104 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
 105 #define R1_CLKSEL_GFX                   (2 << 0)
 106 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
 107 #define R1_CLKSEL_MDM                   (4 << 0)
 108 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
 109
 110 /* 2430-Ratio Config 2 */
 111 #define R2_CLKSEL_L3                    (6 << 0)
 112 #define R2_CLKSEL_L4                    (2 << 5)
 113 #define R2_CLKSEL_USB                   (2 << 25)
 114 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
 115                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 116                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
 117 #define R2_CLKSEL_MPU                   (2 << 0)
 118 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 119 #define R2_CLKSEL_DSP                   (2 << 0)
 120 #define R2_CLKSEL_DSP_IF                (3 << 5)
 121 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 122 #define R2_CLKSEL_GFX                   (2 << 0)
 123 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 124 #define R2_CLKSEL_MDM                   (6 << 0)
 125 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 126
 127 /* 2430-Ratio Bootm (BYPASS) */
 128 #define RB_CLKSEL_L3                    (1 << 0)
 129 #define RB_CLKSEL_L4                    (1 << 5)
 130 #define RB_CLKSEL_USB                   (1 << 25)
 131 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 132                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 133                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 134 #define RB_CLKSEL_MPU                   (1 << 0)
 135 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 136 #define RB_CLKSEL_DSP                   (1 << 0)
 137 #define RB_CLKSEL_DSP_IF                (1 << 5)
 138 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 139 #define RB_CLKSEL_GFX                   (1 << 0)
 140 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 141 #define RB_CLKSEL_MDM                   (1 << 0)
 142 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 143
 144 /* 2420 Ratio Equivalents */
 145 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 146 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 147
 148 /* 2420-PRCM III 532MHz core */
 149 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 150 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 151 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 152 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 153                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 154                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 155                                         RIII_CLKSEL_L3
 156 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 157 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 158 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 159 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 160 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 161 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 162 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 163 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 164                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 165                                         RIII_CLKSEL_DSP
 166 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 167 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 168
 169 /* 2420-PRCM II 600MHz core */
 170 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 171 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 172 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 173 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 174                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 175                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 176                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 177 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 178 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 179 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 180 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 181 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 182 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 183 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 184 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 185                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 186                                         RII_CLKSEL_DSP
 187 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 188 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 189
 190 /* 2420-PRCM I 660MHz core */
 191 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 192 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 193 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 194 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 195                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 196                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 197                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 198 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 199 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 200 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 201 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 202 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 203 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 204 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 205 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 206                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 207                                         RI_CLKSEL_DSP
 208 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 209 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 210
 211 /* 2420-PRCM VII (boot) */
 212 #define RVII_CLKSEL_L3                  (1 << 0)
 213 #define RVII_CLKSEL_L4                  (1 << 5)
 214 #define RVII_CLKSEL_DSS1                (1 << 8)
 215 #define RVII_CLKSEL_DSS2                (0 << 13)
 216 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 217 #define RVII_CLKSEL_SSI                 (1 << 20)
 218 #define RVII_CLKSEL_USB                 (1 << 25)
 219
 220 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 221                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 222                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 223
 224 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 225 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 226
 227 #define RVII_CLKSEL_DSP                 (1 << 0)
 228 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 229 #define RVII_SYNC_DSP                   (0 << 7)
 230 #define RVII_CLKSEL_IVA                 (1 << 8)
 231 #define RVII_SYNC_IVA                   (0 << 13)
 232 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 233                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 234
 235 #define RVII_CLKSEL_GFX                 (1 << 0)
 236 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 237
 238 /*-------------------------------------------------------------------------
 239  * 2430 Target modes: Along with each configuration the CPU has several
 240  * modes which goes along with them. Modes mainly are the addition of
 241  * describe DPLL combinations to go along with a ratio.
 242  *-------------------------------------------------------------------------*/
 243
 244 /* Hardware governed */
 245 #define MX_48M_SRC                      (0 << 3)
 246 #define MX_54M_SRC                      (0 << 5)
 247 #define MX_APLLS_CLIKIN_12              (3 << 23)
 248 #define MX_APLLS_CLIKIN_13              (2 << 23)
 249 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 250
 251 /*
 252  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 253  * #2   (ratio1) baseport-target
 254  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 255  */
 256 #define M5A_DPLL_MULT_12                (133 << 12)
 257 #define M5A_DPLL_DIV_12                 (5 << 8)
 258 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 259                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 260                                         MX_APLLS_CLIKIN_12
 261 #define M5A_DPLL_MULT_13                (266 << 12)
 262 #define M5A_DPLL_DIV_13                 (12 << 8)
 263 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 264                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 265                                         MX_APLLS_CLIKIN_13
 266 #define M5A_DPLL_MULT_19                (180 << 12)
 267 #define M5A_DPLL_DIV_19                 (12 << 8)
 268 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 269                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 270                                         MX_APLLS_CLIKIN_19_2
 271 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 272 #define M5B_DPLL_MULT_12                (50 << 12)
 273 #define M5B_DPLL_DIV_12                 (2 << 8)
 274 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 275                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 276                                         MX_APLLS_CLIKIN_12
 277 #define M5B_DPLL_MULT_13                (200 << 12)
 278 #define M5B_DPLL_DIV_13                 (12 << 8)
 279
 280 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 281                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 282                                         MX_APLLS_CLIKIN_13
 283 #define M5B_DPLL_MULT_19                (125 << 12)
 284 #define M5B_DPLL_DIV_19                 (31 << 8)
 285 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 286                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 287                                         MX_APLLS_CLIKIN_19_2
 288 /*
 289  * #4   (ratio2)
 290  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 291  */
 292 #define M3_DPLL_MULT_12                 (55 << 12)
 293 #define M3_DPLL_DIV_12                  (1 << 8)
 294 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 295                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 296                                         MX_APLLS_CLIKIN_12
 297 #define M3_DPLL_MULT_13                 (330 << 12)
 298 #define M3_DPLL_DIV_13                  (12 << 8)
 299 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 300                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 301                                         MX_APLLS_CLIKIN_13
 302 #define M3_DPLL_MULT_19                 (275 << 12)
 303 #define M3_DPLL_DIV_19                  (15 << 8)
 304 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 305                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 306                                         MX_APLLS_CLIKIN_19_2
 307 /* boot (boot) */
 308 #define MB_DPLL_MULT                    (1 << 12)
 309 #define MB_DPLL_DIV                     (0 << 8)
 310 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 311                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 312
 313 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 314                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 315
 316 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 317                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 318
 319 /*
 320  * 2430 - chassis (sedna)
 321  * 165 (ratio1) same as above #2
 322  * 150 (ratio1)
 323  * 133 (ratio2) same as above #4
 324  * 110 (ratio2) same as above #3
 325  * 104 (ratio2)
 326  * boot (boot)
 327  */
 328
 329 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 330 #define MI_DPLL_MULT_12                 (55 << 12)
 331 #define MI_DPLL_DIV_12                  (1 << 8)
 332 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 333                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 334                                         MX_APLLS_CLIKIN_12
 335
 336 /*
 337  * 2420 Equivalent - mode registers
 338  * PRCM II , target DPLL = 2*300MHz = 600MHz
 339  */
 340 #define MII_DPLL_MULT_12                (50 << 12)
 341 #define MII_DPLL_DIV_12                 (1 << 8)
 342 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 343                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 344                                         MX_APLLS_CLIKIN_12
 345 #define MII_DPLL_MULT_13                (300 << 12)
 346 #define MII_DPLL_DIV_13                 (12 << 8)
 347 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 348                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 349                                         MX_APLLS_CLIKIN_13
 350
 351 /* PRCM III target DPLL = 2*266 = 532MHz*/
 352 #define MIII_DPLL_MULT_12               (133 << 12)
 353 #define MIII_DPLL_DIV_12                (5 << 8)
 354 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 355                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 356                                         MX_APLLS_CLIKIN_12
 357 #define MIII_DPLL_MULT_13               (266 << 12)
 358 #define MIII_DPLL_DIV_13                (12 << 8)
 359 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 360                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 361                                         MX_APLLS_CLIKIN_13
 362
 363 /* PRCM VII (boot bypass) */
 364 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 365 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 366
 367 /* High and low operation value */
 368 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 369 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 370
 371 /*
 372  * These represent optimal values for common parts, it won't work for all.
 373  * As long as you scale down, most parameters are still work, they just
 374  * become sub-optimal. The RFR value goes in the opposite direction. If you
 375  * don't adjust it down as your clock period increases the refresh interval
 376  * will not be met. Setting all parameters for complete worst case may work,
 377  * but may cut memory performance by 2x. Due to errata the DLLs need to be
 378  * unlocked and their value needs run time calibration. A dynamic call is
 379  * need for that as no single right value exists acorss production samples.
 380  *
 381  * Only the FULL speed values are given. Current code is such that rate
 382  * changes must be made at DPLLoutx2. The actual value adjustment for low
 383  * frequency operation will be handled by omap_set_performance()
 384  *
 385  * By having the boot loader boot up in the fastest L4 speed available likely
 386  * will result in something which you can switch between.
 387  */
 388 #define V24XX_SDRC_RFR_CTRL_165MHz      (0x00044c00 | 1)
 389 #define V24XX_SDRC_RFR_CTRL_133MHz      (0x0003de00 | 1)
 390 #define V24XX_SDRC_RFR_CTRL_100MHz      (0x0002da01 | 1)
 391 #define V24XX_SDRC_RFR_CTRL_110MHz      (0x0002da01 | 1) /* Need to calc */
 392 #define V24XX_SDRC_RFR_CTRL_BYPASS      (0x00005000 | 1) /* Need to calc */
 393
 394 /* MPU speed defines */
 395 #define S12M    12000000
 396 #define S13M    13000000
 397 #define S19M    19200000
 398 #define S26M    26000000
 399 #define S100M   100000000
 400 #define S133M   133000000
 401 #define S150M   150000000
 402 #define S165M   165000000
 403 #define S200M   200000000
 404 #define S266M   266000000
 405 #define S300M   300000000
 406 #define S330M   330000000
 407 #define S400M   400000000
 408 #define S532M   532000000
 409 #define S600M   600000000
 410 #define S660M   660000000
 411
 412 /*-------------------------------------------------------------------------
 413  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 414  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 415  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 416  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 417  *
 418  * Filling in table based on H4 boards and 2430-SDPs variants available.
 419  * There are quite a few more rates combinations which could be defined.
 420  *
 421  * When multiple values are defined the start up will try and choose the
 422  * fastest one. If a 'fast' value is defined, then automatically, the /2
 423  * one should be included as it can be used.    Generally having more that
 424  * one fast set does not make sense, as static timings need to be changed
 425  * to change the set.    The exception is the bypass setting which is
 426  * availble for low power bypass.
 427  *
 428  * Note: This table needs to be sorted, fastest to slowest.
 429  *-------------------------------------------------------------------------*/
 430 static struct prcm_config rate_table[] = {
 431         /* PRCM I - FAST */
 432         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 433                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 434                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 435                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_165MHz,
 436                 RATE_IN_242X},
 437
 438         /* PRCM II - FAST */
 439         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 440                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 441                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 442                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 443                 RATE_IN_242X},
 444
 445         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 446                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 447                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 448                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 449                 RATE_IN_242X},
 450
 451         /* PRCM III - FAST */
 452         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 453                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 454                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 455                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 456                 RATE_IN_242X},
 457
 458         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 459                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 460                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 461                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 462                 RATE_IN_242X},
 463
 464         /* PRCM II - SLOW */
 465         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 466                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 467                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 468                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 469                 RATE_IN_242X},
 470
 471         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 472                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 473                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 474                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 475                 RATE_IN_242X},
 476
 477         /* PRCM III - SLOW */
 478         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 479                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 480                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 481                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 482                 RATE_IN_242X},
 483
 484         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 485                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 486                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 487                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 488                 RATE_IN_242X},
 489
 490         /* PRCM-VII (boot-bypass) */
 491         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 492                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 493                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 494                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
 495                 RATE_IN_242X},
 496
 497         /* PRCM-VII (boot-bypass) */
 498         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 499                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 500                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 501                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
 502                 RATE_IN_242X},
 503
 504         /* PRCM #3 - ratio2 (ES2) - FAST */
 505         {S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 506                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 507                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 508                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 509                 V24XX_SDRC_RFR_CTRL_110MHz,
 510                 RATE_IN_243X},
 511
 512         /* PRCM #5a - ratio1 - FAST */
 513         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 514                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 515                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 516                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 517                 V24XX_SDRC_RFR_CTRL_133MHz,
 518                 RATE_IN_243X},
 519
 520         /* PRCM #5b - ratio1 - FAST */
 521         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 522                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 523                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 524                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 525                 V24XX_SDRC_RFR_CTRL_100MHz,
 526                 RATE_IN_243X},
 527
 528         /* PRCM #3 - ratio2 (ES2) - SLOW */
 529         {S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 530                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 531                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 532                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 533                 V24XX_SDRC_RFR_CTRL_110MHz,
 534                 RATE_IN_243X},
 535
 536         /* PRCM #5a - ratio1 - SLOW */
 537         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 538                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 539                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 540                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 541                 V24XX_SDRC_RFR_CTRL_133MHz,
 542                 RATE_IN_243X},
 543
 544         /* PRCM #5b - ratio1 - SLOW*/
 545         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 546                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 547                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 548                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 549                 V24XX_SDRC_RFR_CTRL_100MHz,
 550                 RATE_IN_243X},
 551
 552         /* PRCM-boot/bypass */
 553         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 554                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 555                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 556                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 557                 V24XX_SDRC_RFR_CTRL_BYPASS,
 558                 RATE_IN_243X},
 559
 560         /* PRCM-boot/bypass */
 561         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 562                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 563                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 564                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 565                 V24XX_SDRC_RFR_CTRL_BYPASS,
 566                 RATE_IN_243X},
 567
 568         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 569 };
 570
 571 /*-------------------------------------------------------------------------
 572  * 24xx clock tree.
 573  *
 574  * NOTE:In many cases here we are assigning a 'default' parent. In many
 575  *      cases the parent is selectable. The get/set parent calls will also
 576  *      switch sources.
 577  *
 578  *      Many some clocks say always_enabled, but they can be auto idled for
 579  *      power savings. They will always be available upon clock request.
 580  *
 581  *      Several sources are given initial rates which may be wrong, this will
 582  *      be fixed up in the init func.
 583  *
 584  *      Things are broadly separated below by clock domains. It is
 585  *      noteworthy that most periferals have dependencies on multiple clock
 586  *      domains. Many get their interface clocks from the L4 domain, but get
 587  *      functional clocks from fixed sources or other core domain derived
 588  *      clocks.
 589  *-------------------------------------------------------------------------*/
 590
 591 /* Base external input clocks */
 592 static struct clk func_32k_ck = {
 593         .name           = "func_32k_ck",
 594         .rate           = 32000,
 595         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 596                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 597         .recalc         = &propagate_rate,
 598 };
 599
 600 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 601 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 602         .name           = "osc_ck",
 603         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 604                                 RATE_PROPAGATES,
 605         .enable         = &omap2_enable_osc_ck,
 606         .disable        = &omap2_disable_osc_ck,
 607         .recalc         = &omap2_osc_clk_recalc,
 608 };
 609
 610 /* With out modem likely 12MHz, with modem likely 13MHz */
 611 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 612         .name           = "sys_ck",             /* ~ ref_clk also */
 613         .parent         = &osc_ck,
 614         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 615                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 616         .recalc         = &omap2_sys_clk_recalc,
 617 };
 618
 619 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 620         .name           = "alt_ck",
 621         .rate           = 54000000,
 622         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 623                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 624         .recalc         = &propagate_rate,
 625 };
 626
 627 /*
 628  * Analog domain root source clocks
 629  */
 630
 631 /* dpll_ck, is broken out in to special cases through clksel */
 632 /* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
 633  * deal with this
 634  */
 635
 636 static const struct dpll_data dpll_dd = {
 637         .mult_div1_reg          = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 638         .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
 639         .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
 640         .auto_idle_mask         = OMAP24XX_AUTO_DPLL_MASK,
 641         .auto_idle_val          = 0x3, /* stop DPLL upon idle */
 642 };
 643
 644 static struct clk dpll_ck = {
 645         .name           = "dpll_ck",
 646         .parent         = &sys_ck,              /* Can be func_32k also */
 647         .dpll_data      = &dpll_dd,
 648         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 649                                 RATE_PROPAGATES | ALWAYS_ENABLED,
 650         .recalc         = &omap2_dpll_recalc,
 651         .set_rate       = &omap2_reprogram_dpll,
 652 };
 653
 654 static struct clk apll96_ck = {
 655         .name           = "apll96_ck",
 656         .parent         = &sys_ck,
 657         .rate           = 96000000,
 658         .flags          = CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X |
 659                                 RATE_FIXED | RATE_PROPAGATES,
 660         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 661         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 662         .enable         = &omap2_clk_fixed_enable,
 663         .disable        = &omap2_clk_fixed_disable,
 664         .recalc         = &propagate_rate,
 665 };
 666
 667 static struct clk apll54_ck = {
 668         .name           = "apll54_ck",
 669         .parent         = &sys_ck,
 670         .rate           = 54000000,
 671         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 672                                 RATE_FIXED | RATE_PROPAGATES,
 673         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 674         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 675         .enable         = &omap2_clk_fixed_enable,
 676         .disable        = &omap2_clk_fixed_disable,
 677         .recalc         = &propagate_rate,
 678 };
 679
 680 /*
 681  * PRCM digital base sources
 682  */
 683
 684 /* func_54m_ck */
 685
 686 static const struct clksel_rate func_54m_apll54_rates[] = {
 687         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 688         { .div = 0 },
 689 };
 690
 691 static const struct clksel_rate func_54m_alt_rates[] = {
 692         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 693         { .div = 0 },
 694 };
 695
 696 static const struct clksel func_54m_clksel[] = {
 697         { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
 698         { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
 699         { .parent = NULL },
 700 };
 701
 702 static struct clk func_54m_ck = {
 703         .name           = "func_54m_ck",
 704         .parent         = &apll54_ck,   /* can also be alt_clk */
 705         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 706                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 707         .init           = &omap2_init_clksel_parent,
 708         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 709         .clksel_mask    = OMAP24XX_54M_SOURCE,
 710         .clksel         = func_54m_clksel,
 711         .recalc         = &omap2_clksel_recalc,
 712 };
 713
 714 static struct clk core_ck = {
 715         .name           = "core_ck",
 716         .parent         = &dpll_ck,             /* can also be 32k */
 717         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 718                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 719         .recalc         = &followparent_recalc,
 720 };
 721
 722 /* func_96m_ck */
 723 static const struct clksel_rate func_96m_apll96_rates[] = {
 724         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 725         { .div = 0 },
 726 };
 727
 728 static const struct clksel_rate func_96m_alt_rates[] = {
 729         { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
 730         { .div = 0 },
 731 };
 732
 733 static const struct clksel func_96m_clksel[] = {
 734         { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
 735         { .parent = &alt_ck,    .rates = func_96m_alt_rates },
 736         { .parent = NULL }
 737 };
 738
 739 /* The parent of this clock is not selectable on 2420. */
 740 static struct clk func_96m_ck = {
 741         .name           = "func_96m_ck",
 742         .parent         = &apll96_ck,
 743         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 744                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 745         .init           = &omap2_init_clksel_parent,
 746         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 747         .clksel_mask    = OMAP2430_96M_SOURCE,
 748         .clksel         = func_96m_clksel,
 749         .recalc         = &omap2_clksel_recalc,
 750         .round_rate     = &omap2_clksel_round_rate,
 751         .set_rate       = &omap2_clksel_set_rate
 752 };
 753
 754 /* func_48m_ck */
 755
 756 static const struct clksel_rate func_48m_apll96_rates[] = {
 757         { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 758         { .div = 0 },
 759 };
 760
 761 static const struct clksel_rate func_48m_alt_rates[] = {
 762         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 763         { .div = 0 },
 764 };
 765
 766 static const struct clksel func_48m_clksel[] = {
 767         { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
 768         { .parent = &alt_ck, .rates = func_48m_alt_rates },
 769         { .parent = NULL }
 770 };
 771
 772 static struct clk func_48m_ck = {
 773         .name           = "func_48m_ck",
 774         .parent         = &apll96_ck,    /* 96M or Alt */
 775         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 776                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 777         .init           = &omap2_init_clksel_parent,
 778         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 779         .clksel_mask    = OMAP24XX_48M_SOURCE,
 780         .clksel         = func_48m_clksel,
 781         .recalc         = &omap2_clksel_recalc,
 782         .round_rate     = &omap2_clksel_round_rate,
 783         .set_rate       = &omap2_clksel_set_rate
 784 };
 785
 786 static struct clk func_12m_ck = {
 787         .name           = "func_12m_ck",
 788         .parent         = &func_48m_ck,
 789         .fixed_div      = 4,
 790         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 791                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 792         .recalc         = &omap2_fixed_divisor_recalc,
 793 };
 794
 795 /* Secure timer, only available in secure mode */
 796 static struct clk wdt1_osc_ck = {
 797         .name           = "ck_wdt1_osc",
 798         .parent         = &osc_ck,
 799         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 800         .recalc         = &followparent_recalc,
 801 };
 802
 803 /*
 804  * The common_clkout* clksel_rate structs are common to
 805  * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
 806  * sys_clkout2_* are 2420-only, so the
 807  * clksel_rate flags fields are inaccurate for those clocks. This is
 808  * harmless since access to those clocks are gated by the struct clk
 809  * flags fields, which mark them as 2420-only.
 810  */
 811 static const struct clksel_rate common_clkout_src_core_rates[] = {
 812         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 813         { .div = 0 }
 814 };
 815
 816 static const struct clksel_rate common_clkout_src_sys_rates[] = {
 817         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 818         { .div = 0 }
 819 };
 820
 821 static const struct clksel_rate common_clkout_src_96m_rates[] = {
 822         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 823         { .div = 0 }
 824 };
 825
 826 static const struct clksel_rate common_clkout_src_54m_rates[] = {
 827         { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
 828         { .div = 0 }
 829 };
 830
 831 static const struct clksel common_clkout_src_clksel[] = {
 832         { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
 833         { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
 834         { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
 835         { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
 836         { .parent = NULL }
 837 };
 838
 839 static struct clk sys_clkout_src = {
 840         .name           = "sys_clkout_src",
 841         .parent         = &func_54m_ck,
 842         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 843                                 RATE_PROPAGATES,
 844         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 845         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 846         .init           = &omap2_init_clksel_parent,
 847         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 848         .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
 849         .clksel         = common_clkout_src_clksel,
 850         .recalc         = &omap2_clksel_recalc,
 851         .round_rate     = &omap2_clksel_round_rate,
 852         .set_rate       = &omap2_clksel_set_rate
 853 };
 854
 855 static const struct clksel_rate common_clkout_rates[] = {
 856         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 857         { .div = 2, .val = 1, .flags = RATE_IN_24XX },
 858         { .div = 4, .val = 2, .flags = RATE_IN_24XX },
 859         { .div = 8, .val = 3, .flags = RATE_IN_24XX },
 860         { .div = 16, .val = 4, .flags = RATE_IN_24XX },
 861         { .div = 0 },
 862 };
 863
 864 static const struct clksel sys_clkout_clksel[] = {
 865         { .parent = &sys_clkout_src, .rates = common_clkout_rates },
 866         { .parent = NULL }
 867 };
 868
 869 static struct clk sys_clkout = {
 870         .name           = "sys_clkout",
 871         .parent         = &sys_clkout_src,
 872         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 873                                 PARENT_CONTROLS_CLOCK,
 874         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 875         .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
 876         .clksel         = sys_clkout_clksel,
 877         .recalc         = &omap2_clksel_recalc,
 878         .round_rate     = &omap2_clksel_round_rate,
 879         .set_rate       = &omap2_clksel_set_rate
 880 };
 881
 882 /* In 2430, new in 2420 ES2 */
 883 static struct clk sys_clkout2_src = {
 884         .name           = "sys_clkout2_src",
 885         .parent         = &func_54m_ck,
 886         .flags          = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
 887         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 888         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 889         .init           = &omap2_init_clksel_parent,
 890         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 891         .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
 892         .clksel         = common_clkout_src_clksel,
 893         .recalc         = &omap2_clksel_recalc,
 894         .round_rate     = &omap2_clksel_round_rate,
 895         .set_rate       = &omap2_clksel_set_rate
 896 };
 897
 898 static const struct clksel sys_clkout2_clksel[] = {
 899         { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
 900         { .parent = NULL }
 901 };
 902
 903 /* In 2430, new in 2420 ES2 */
 904 static struct clk sys_clkout2 = {
 905         .name           = "sys_clkout2",
 906         .parent         = &sys_clkout2_src,
 907         .flags          = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
 908         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 909         .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
 910         .clksel         = sys_clkout2_clksel,
 911         .recalc         = &omap2_clksel_recalc,
 912         .round_rate     = &omap2_clksel_round_rate,
 913         .set_rate       = &omap2_clksel_set_rate
 914 };
 915
 916 static struct clk emul_ck = {
 917         .name           = "emul_ck",
 918         .parent         = &func_54m_ck,
 919         .flags          = CLOCK_IN_OMAP242X,
 920         .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL,
 921         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 922         .recalc         = &followparent_recalc,
 923
 924 };
 925
 926 /*
 927  * MPU clock domain
 928  *      Clocks:
 929  *              MPU_FCLK, MPU_ICLK
 930  *              INT_M_FCLK, INT_M_I_CLK
 931  *
 932  * - Individual clocks are hardware managed.
 933  * - Base divider comes from: CM_CLKSEL_MPU
 934  *
 935  */
 936 static const struct clksel_rate mpu_core_rates[] = {
 937         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 938         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 939         { .div = 4, .val = 4, .flags = RATE_IN_242X },
 940         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 941         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 942         { .div = 0 },
 943 };
 944
 945 static const struct clksel mpu_clksel[] = {
 946         { .parent = &core_ck, .rates = mpu_core_rates },
 947         { .parent = NULL }
 948 };
 949
 950 static struct clk mpu_ck = {    /* Control cpu */
 951         .name           = "mpu_ck",
 952         .parent         = &core_ck,
 953         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 954                                 ALWAYS_ENABLED | DELAYED_APP |
 955                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
 956         .init           = &omap2_init_clksel_parent,
 957         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
 958         .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
 959         .clksel         = mpu_clksel,
 960         .recalc         = &omap2_clksel_recalc,
 961         .round_rate     = &omap2_clksel_round_rate,
 962         .set_rate       = &omap2_clksel_set_rate
 963 };
 964
 965 /*
 966  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
 967  * Clocks:
 968  *      2430: IVA2.1_FCLK, IVA2.1_ICLK
 969  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
 970  */
 971 /* XXX Okay, this is dumb.  iva2_1fck and dsp_fck are the same clock.
 972  * they should just be treated as such.
 973  */
 974
 975 /* iva2_1_fck */
 976 static const struct clksel_rate iva2_1_fck_core_rates[] = {
 977         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 978         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 979         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
 980         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
 981         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 982         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 983         { .div = 12, .val = 12, .flags = RATE_IN_242X },
 984         { .div = 0 },
 985 };
 986
 987 static const struct clksel iva2_1_fck_clksel[] = {
 988         { .parent = &core_ck, .rates = iva2_1_fck_core_rates },
 989         { .parent = NULL }
 990 };
 991
 992 static struct clk iva2_1_fck = {
 993         .name           = "iva2_1_fck",
 994         .parent         = &core_ck,
 995         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | RATE_PROPAGATES |
 996                                 CONFIG_PARTICIPANT,
 997         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 998         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
 999         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1000         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
1001         .clksel         = iva2_1_fck_clksel,
1002         .recalc         = &omap2_clksel_recalc,
1003         .round_rate     = &omap2_clksel_round_rate,
1004         .set_rate       = &omap2_clksel_set_rate
1005 };
1006
1007 /* iva2_1_ick */
1008 static const struct clksel_rate iva2_1_ick_core_rates[] = {
1009         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1010         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1011         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1012         { .div = 0 },
1013 };
1014
1015 static const struct clksel iva2_1_ick_clksel[] = {
1016         { .parent = &core_ck, .rates = iva2_1_ick_core_rates },
1017         { .parent = NULL }
1018 };
1019
1020 static struct clk iva2_1_ick = {
1021         .name           = "iva2_1_ick",
1022         .parent         = &iva2_1_fck,
1023         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1024         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1025         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1026         .clksel         = iva2_1_ick_clksel,
1027         .recalc         = &omap2_clksel_recalc,
1028         .round_rate     = &omap2_clksel_round_rate,
1029         .set_rate       = &omap2_clksel_set_rate
1030 };
1031
1032 /*
1033  * Won't be too specific here. The core clock comes into this block
1034  * it is divided then tee'ed. One branch goes directly to xyz enable
1035  * controls. The other branch gets further divided by 2 then possibly
1036  * routed into a synchronizer and out of clocks abc.
1037  */
1038 static const struct clksel_rate dsp_fck_core_rates[] = {
1039         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1040         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1041         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1042         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1043         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1044         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1045         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1046         { .div = 0 },
1047 };
1048
1049 static const struct clksel dsp_fck_clksel[] = {
1050         { .parent = &core_ck, .rates = dsp_fck_core_rates },
1051         { .parent = NULL }
1052 };
1053
1054 static struct clk dsp_fck = {
1055         .name           = "dsp_fck",
1056         .parent         = &core_ck,
1057         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP |
1058                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1059         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
1060         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1061         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1062         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
1063         .clksel         = dsp_fck_clksel,
1064         .recalc         = &omap2_clksel_recalc,
1065         .round_rate     = &omap2_clksel_round_rate,
1066         .set_rate       = &omap2_clksel_set_rate
1067 };
1068
1069 static const struct clksel_rate dsp_ick_core_rates[] = {
1070         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1071         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1072         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1073         { .div = 0 },
1074 };
1075
1076 static const struct clksel dsp_ick_clksel[] = {
1077         { .parent = &core_ck, .rates = dsp_ick_core_rates },
1078         { .parent = NULL }
1079 };
1080
1081 static struct clk dsp_ick = {
1082         .name           = "dsp_ick",     /* apparently ipi and isp */
1083         .parent         = &core_ck,
1084         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
1085         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
1086         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,            /* for ipi */
1087         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1088         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1089         .clksel         = dsp_ick_clksel,
1090         .recalc         = &omap2_clksel_recalc,
1091 };
1092
1093 static const struct clksel_rate iva1_ifck_core_rates[] = {
1094         { .div = 1, .val = 1, .flags = RATE_IN_242X | DEFAULT_RATE },
1095         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1096         { .div = 3, .val = 3, .flags = RATE_IN_242X },
1097         { .div = 4, .val = 4, .flags = RATE_IN_242X },
1098         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1099         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1100         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1101         { .div = 0 },
1102 };
1103
1104 static const struct clksel iva1_ifck_clksel[] = {
1105         { .parent = &core_ck, .rates = iva1_ifck_core_rates },
1106         { .parent = NULL }
1107 };
1108
1109 static struct clk iva1_ifck = {
1110         .name           = "iva1_ifck",
1111         .parent         = &core_ck,
1112         .flags          = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
1113                                 RATE_PROPAGATES | DELAYED_APP,
1114         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
1115         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
1116         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1117         .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
1118         .clksel         = iva1_ifck_clksel,
1119         .recalc         = &omap2_clksel_recalc,
1120         .round_rate     = &omap2_clksel_round_rate,
1121         .set_rate       = &omap2_clksel_set_rate
1122 };
1123
1124 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1125 static struct clk iva1_mpu_int_ifck = {
1126         .name           = "iva1_mpu_int_ifck",
1127         .parent         = &iva1_ifck,
1128         .flags          = CLOCK_IN_OMAP242X,
1129         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
1130         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
1131         .fixed_div      = 2,
1132         .recalc         = &omap2_fixed_divisor_recalc,
1133 };
1134
1135 /*
1136  * L3 clock domain
1137  * L3 clocks are used for both interface and functional clocks to
1138  * multiple entities. Some of these clocks are completely managed
1139  * by hardware, and some others allow software control. Hardware
1140  * managed ones general are based on directly CLK_REQ signals and
1141  * various auto idle settings. The functional spec sets many of these
1142  * as 'tie-high' for their enables.
1143  *
1144  * I-CLOCKS:
1145  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1146  *      CAM, HS-USB.
1147  * F-CLOCK
1148  *      SSI.
1149  *
1150  * GPMC memories and SDRC have timing and clock sensitive registers which
1151  * may very well need notification when the clock changes. Currently for low
1152  * operating points, these are taken care of in sleep.S.
1153  */
1154 static const struct clksel_rate core_l3_core_rates[] = {
1155         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1156         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1157         { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1158         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1159         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1160         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1161         { .div = 16, .val = 16, .flags = RATE_IN_242X },
1162         { .div = 0 }
1163 };
1164
1165 static const struct clksel core_l3_clksel[] = {
1166         { .parent = &core_ck, .rates = core_l3_core_rates },
1167         { .parent = NULL }
1168 };
1169
1170 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
1171         .name           = "core_l3_ck",
1172         .parent         = &core_ck,
1173         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1174                                 ALWAYS_ENABLED | DELAYED_APP |
1175                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1176         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1177         .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
1178         .clksel         = core_l3_clksel,
1179         .recalc         = &omap2_clksel_recalc,
1180         .round_rate     = &omap2_clksel_round_rate,
1181         .set_rate       = &omap2_clksel_set_rate
1182 };
1183
1184 /* usb_l4_ick */
1185 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1186         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1187         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1188         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1189         { .div = 0 }
1190 };
1191
1192 static const struct clksel usb_l4_ick_clksel[] = {
1193         { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1194         { .parent = NULL },
1195 };
1196
1197 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
1198         .name           = "usb_l4_ick",
1199         .parent         = &core_l3_ck,
1200         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1201                                 DELAYED_APP | CONFIG_PARTICIPANT,
1202         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1203         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1204         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1205         .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
1206         .clksel         = usb_l4_ick_clksel,
1207         .recalc         = &omap2_clksel_recalc,
1208         .round_rate     = &omap2_clksel_round_rate,
1209         .set_rate       = &omap2_clksel_set_rate
1210 };
1211
1212 /*
1213  * SSI is in L3 management domain, its direct parent is core not l3,
1214  * many core power domain entities are grouped into the L3 clock
1215  * domain.
1216  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
1217  *
1218  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1219  */
1220 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1221         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1222         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1223         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1224         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1225         { .div = 5, .val = 5, .flags = RATE_IN_243X },
1226         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1227         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1228         { .div = 0 }
1229 };
1230
1231 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1232         { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1233         { .parent = NULL }
1234 };
1235
1236 static struct clk ssi_ssr_sst_fck = {
1237         .name           = "ssi_fck",
1238         .parent         = &core_ck,
1239         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1240                                 DELAYED_APP,
1241         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),       /* bit 1 */
1242         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1243         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1244         .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
1245         .clksel         = ssi_ssr_sst_fck_clksel,
1246         .recalc         = &omap2_clksel_recalc,
1247         .round_rate     = &omap2_clksel_round_rate,
1248         .set_rate       = &omap2_clksel_set_rate
1249 };
1250
1251 /*
1252  * GFX clock domain
1253  *      Clocks:
1254  * GFX_FCLK, GFX_ICLK
1255  * GFX_CG1(2d), GFX_CG2(3d)
1256  *
1257  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1258  * The 2d and 3d clocks run at a hardware determined
1259  * divided value of fclk.
1260  *
1261  */
1262 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1263
1264 /*
1265  * These clksel_rate/clksel structs are shared between gfx_3d_fck and
1266  * gfx_2d_fck
1267  */
1268 static const struct clksel_rate gfx_fck_core_l3_rates[] = {
1269         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1270         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1271         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1272         { .div = 4, .val = 4, .flags = RATE_IN_243X },
1273         { .div = 0 }
1274 };
1275
1276 static const struct clksel gfx_fck_clksel[] = {
1277         { .parent = &core_l3_ck, .rates = gfx_fck_core_l3_rates },
1278         { .parent = NULL },
1279 };
1280
1281 static struct clk gfx_3d_fck = {
1282         .name           = "gfx_3d_fck",
1283         .parent         = &core_l3_ck,
1284         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1285         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
1286         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
1287         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1288         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1289         .clksel         = gfx_fck_clksel,
1290         .recalc         = &omap2_clksel_recalc,
1291         .round_rate     = &omap2_clksel_round_rate,
1292         .set_rate       = &omap2_clksel_set_rate
1293 };
1294
1295 static struct clk gfx_2d_fck = {
1296         .name           = "gfx_2d_fck",
1297         .parent         = &core_l3_ck,
1298         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1299         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
1300         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
1301         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1302         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1303         .clksel         = gfx_fck_clksel,
1304         .recalc         = &omap2_clksel_recalc,
1305         .round_rate     = &omap2_clksel_round_rate,
1306         .set_rate       = &omap2_clksel_set_rate
1307 };
1308
1309 static struct clk gfx_ick = {
1310         .name           = "gfx_ick",            /* From l3 */
1311         .parent         = &core_l3_ck,
1312         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1313         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),  /* bit 0 */
1314         .enable_bit     = OMAP_EN_GFX_SHIFT,
1315         .recalc         = &followparent_recalc,
1316 };
1317
1318 /*
1319  * Modem clock domain (2430)
1320  *      CLOCKS:
1321  *              MDM_OSC_CLK
1322  *              MDM_ICLK
1323  * These clocks are usable in chassis mode only.
1324  */
1325 static const struct clksel_rate mdm_ick_core_rates[] = {
1326         { .div = 1, .val = 1, .flags = RATE_IN_243X },
1327         { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1328         { .div = 6, .val = 6, .flags = RATE_IN_243X },
1329         { .div = 9, .val = 9, .flags = RATE_IN_243X },
1330         { .div = 0 }
1331 };
1332
1333 static const struct clksel mdm_ick_clksel[] = {
1334         { .parent = &core_ck, .rates = mdm_ick_core_rates },
1335         { .parent = NULL }
1336 };
1337
1338 static struct clk mdm_ick = {           /* used both as a ick and fck */
1339         .name           = "mdm_ick",
1340         .parent         = &core_ck,
1341         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1342         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1343         .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1344         .clksel_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
1345         .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
1346         .clksel         = mdm_ick_clksel,
1347         .recalc         = &omap2_clksel_recalc,
1348         .round_rate     = &omap2_clksel_round_rate,
1349         .set_rate       = &omap2_clksel_set_rate
1350 };
1351
1352 static struct clk mdm_osc_ck = {
1353         .name           = "mdm_osc_ck",
1354         .parent         = &osc_ck,
1355         .flags          = CLOCK_IN_OMAP243X,
1356         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, OMAP24XX_CM_FCLKEN),
1357         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
1358         .recalc         = &followparent_recalc,
1359 };
1360
1361 /*
1362  * L4 clock management domain
1363  *
1364  * This domain contains lots of interface clocks from the L4 interface, some
1365  * functional clocks.   Fixed APLL functional source clocks are managed in
1366  * this domain.
1367  */
1368 static const struct clksel_rate l4_core_l3_rates[] = {
1369         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1370         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1371         { .div = 0 }
1372 };
1373
1374 static const struct clksel l4_clksel[] = {
1375         { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1376         { .parent = NULL }
1377 };
1378
1379 static struct clk l4_ck = {             /* used both as an ick and fck */
1380         .name           = "l4_ck",
1381         .parent         = &core_l3_ck,
1382         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1383                                 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1384         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1385         .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
1386         .clksel         = l4_clksel,
1387         .recalc         = &omap2_clksel_recalc,
1388         .round_rate     = &omap2_clksel_round_rate,
1389         .set_rate       = &omap2_clksel_set_rate
1390 };
1391
1392 static struct clk ssi_l4_ick = {
1393         .name           = "ssi_l4_ick",
1394         .parent         = &l4_ck,
1395         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1396         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),        /* bit 1 */
1397         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1398         .recalc         = &followparent_recalc,
1399 };
1400
1401 /*
1402  * DSS clock domain
1403  * CLOCKs:
1404  * DSS_L4_ICLK, DSS_L3_ICLK,
1405  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1406  *
1407  * DSS is both initiator and target.
1408  */
1409 /* XXX Add RATE_NOT_VALIDATED */
1410
1411 static const struct clksel_rate dss1_fck_sys_rates[] = {
1412         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1413         { .div = 0 }
1414 };
1415
1416 static const struct clksel_rate dss1_fck_core_rates[] = {
1417         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1418         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1419         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1420         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1421         { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1422         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1423         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1424         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1425         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1426         { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1427         { .div = 0 }
1428 };
1429
1430 static const struct clksel dss1_fck_clksel[] = {
1431         { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
1432         { .parent = &core_ck, .rates = dss1_fck_core_rates },
1433         { .parent = NULL },
1434 };
1435
1436 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1437         .name           = "dss_ick",
1438         .parent         = &l4_ck,       /* really both l3 and l4 */
1439         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1440         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1441         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1442         .recalc         = &followparent_recalc,
1443 };
1444
1445 static struct clk dss1_fck = {
1446         .name           = "dss1_fck",
1447         .parent         = &core_ck,             /* Core or sys */
1448         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1449                                 DELAYED_APP,
1450         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1451         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1452         .init           = &omap2_init_clksel_parent,
1453         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1454         .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
1455         .clksel         = dss1_fck_clksel,
1456         .recalc         = &omap2_clksel_recalc,
1457         .round_rate     = &omap2_clksel_round_rate,
1458         .set_rate       = &omap2_clksel_set_rate
1459 };
1460
1461 static const struct clksel_rate dss2_fck_sys_rates[] = {
1462         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1463         { .div = 0 }
1464 };
1465
1466 static const struct clksel_rate dss2_fck_48m_rates[] = {
1467         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1468         { .div = 0 }
1469 };
1470
1471 static const struct clksel dss2_fck_clksel[] = {
1472         { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
1473         { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1474         { .parent = NULL }
1475 };
1476
1477 static struct clk dss2_fck = {          /* Alt clk used in power management */
1478         .name           = "dss2_fck",
1479         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1480         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1481                                 DELAYED_APP,
1482         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1483         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
1484         .init           = &omap2_init_clksel_parent,
1485         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1486         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
1487         .clksel         = dss2_fck_clksel,
1488         .recalc         = &followparent_recalc,
1489 };
1490
1491 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1492         .name           = "dss_54m_fck",        /* 54m tv clk */
1493         .parent         = &func_54m_ck,
1494         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1495         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1496         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
1497         .recalc         = &followparent_recalc,
1498 };
1499
1500 /*
1501  * CORE power domain ICLK & FCLK defines.
1502  * Many of the these can have more than one possible parent. Entries
1503  * here will likely have an L4 interface parent, and may have multiple
1504  * functional clock parents.
1505  */
1506 static const struct clksel_rate gpt_32k_rates[] = {
1507         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1508         { .div = 0 }
1509 };
1510
1511 static const struct clksel_rate gpt_sys_rates[] = {
1512         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1513         { .div = 0 }
1514 };
1515
1516 static const struct clksel_rate gpt_alt_rates[] = {
1517         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1518         { .div = 0 }
1519 };
1520
1521 static const struct clksel gpt_clksel[] = {
1522         { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1523         { .parent = &sys_ck,      .rates = gpt_sys_rates },
1524         { .parent = &alt_ck,      .rates = gpt_alt_rates },
1525         { .parent = NULL },
1526 };
1527
1528 static struct clk gpt1_ick = {
1529         .name           = "gpt1_ick",
1530         .parent         = &l4_ck,
1531         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1532         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), /* Bit0 */
1533         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1534         .recalc         = &followparent_recalc,
1535 };
1536
1537 static struct clk gpt1_fck = {
1538         .name           = "gpt1_fck",
1539         .parent         = &func_32k_ck,
1540         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1541         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),        /* Bit0 */
1542         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1543         .init           = &omap2_init_clksel_parent,
1544         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1545         .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
1546         .clksel         = gpt_clksel,
1547         .recalc         = &omap2_clksel_recalc,
1548         .round_rate     = &omap2_clksel_round_rate,
1549         .set_rate       = &omap2_clksel_set_rate
1550 };
1551
1552 static struct clk gpt2_ick = {
1553         .name           = "gpt2_ick",
1554         .parent         = &l4_ck,
1555         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1556         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit4 */
1557         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1558         .recalc         = &followparent_recalc,
1559 };
1560
1561 static struct clk gpt2_fck = {
1562         .name           = "gpt2_fck",
1563         .parent         = &func_32k_ck,
1564         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1565         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1566         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1567         .init           = &omap2_init_clksel_parent,
1568         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1569         .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
1570         .clksel         = gpt_clksel,
1571         .recalc         = &omap2_clksel_recalc,
1572 };
1573
1574 static struct clk gpt3_ick = {
1575         .name           = "gpt3_ick",
1576         .parent         = &l4_ck,
1577         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1578         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit5 */
1579         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1580         .recalc         = &followparent_recalc,
1581 };
1582
1583 static struct clk gpt3_fck = {
1584         .name           = "gpt3_fck",
1585         .parent         = &func_32k_ck,
1586         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1587         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1588         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1589         .init           = &omap2_init_clksel_parent,
1590         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1591         .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
1592         .clksel         = gpt_clksel,
1593         .recalc         = &omap2_clksel_recalc,
1594 };
1595
1596 static struct clk gpt4_ick = {
1597         .name           = "gpt4_ick",
1598         .parent         = &l4_ck,
1599         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1600         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit6 */
1601         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1602         .recalc         = &followparent_recalc,
1603 };
1604
1605 static struct clk gpt4_fck = {
1606         .name           = "gpt4_fck",
1607         .parent         = &func_32k_ck,
1608         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1609         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1610         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1611         .init           = &omap2_init_clksel_parent,
1612         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1613         .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
1614         .clksel         = gpt_clksel,
1615         .recalc         = &omap2_clksel_recalc,
1616 };
1617
1618 static struct clk gpt5_ick = {
1619         .name           = "gpt5_ick",
1620         .parent         = &l4_ck,
1621         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1622         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* Bit7 */
1623         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1624         .recalc         = &followparent_recalc,
1625 };
1626
1627 static struct clk gpt5_fck = {
1628         .name           = "gpt5_fck",
1629         .parent         = &func_32k_ck,
1630         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1631         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1632         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1633         .init           = &omap2_init_clksel_parent,
1634         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1635         .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
1636         .clksel         = gpt_clksel,
1637         .recalc         = &omap2_clksel_recalc,
1638 };
1639
1640 static struct clk gpt6_ick = {
1641         .name           = "gpt6_ick",
1642         .parent         = &l4_ck,
1643         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1644         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit8 */
1645         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1646         .recalc         = &followparent_recalc,
1647 };
1648
1649 static struct clk gpt6_fck = {
1650         .name           = "gpt6_fck",
1651         .parent         = &func_32k_ck,
1652         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1653         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1654         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1655         .init           = &omap2_init_clksel_parent,
1656         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1657         .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
1658         .clksel         = gpt_clksel,
1659         .recalc         = &omap2_clksel_recalc,
1660 };
1661
1662 static struct clk gpt7_ick = {
1663         .name           = "gpt7_ick",
1664         .parent         = &l4_ck,
1665         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1666         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit9 */
1667         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1668         .recalc         = &followparent_recalc,
1669 };
1670
1671 static struct clk gpt7_fck = {
1672         .name           = "gpt7_fck",
1673         .parent         = &func_32k_ck,
1674         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1675         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1676         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1677         .init           = &omap2_init_clksel_parent,
1678         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1679         .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
1680         .clksel         = gpt_clksel,
1681         .recalc         = &omap2_clksel_recalc,
1682 };
1683
1684 static struct clk gpt8_ick = {
1685         .name           = "gpt8_ick",
1686         .parent         = &l4_ck,
1687         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1688         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit10 */
1689         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1690         .recalc         = &followparent_recalc,
1691 };
1692
1693 static struct clk gpt8_fck = {
1694         .name           = "gpt8_fck",
1695         .parent         = &func_32k_ck,
1696         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1697         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1698         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1699         .init           = &omap2_init_clksel_parent,
1700         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1701         .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
1702         .clksel         = gpt_clksel,
1703         .recalc         = &omap2_clksel_recalc,
1704 };
1705
1706 static struct clk gpt9_ick = {
1707         .name           = "gpt9_ick",
1708         .parent         = &l4_ck,
1709         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1710         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1711         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1712         .recalc         = &followparent_recalc,
1713 };
1714
1715 static struct clk gpt9_fck = {
1716         .name           = "gpt9_fck",
1717         .parent         = &func_32k_ck,
1718         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1719         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1720         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1721         .init           = &omap2_init_clksel_parent,
1722         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1723         .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
1724         .clksel         = gpt_clksel,
1725         .recalc         = &omap2_clksel_recalc,
1726 };
1727
1728 static struct clk gpt10_ick = {
1729         .name           = "gpt10_ick",
1730         .parent         = &l4_ck,
1731         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1732         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1733         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1734         .recalc         = &followparent_recalc,
1735 };
1736
1737 static struct clk gpt10_fck = {
1738         .name           = "gpt10_fck",
1739         .parent         = &func_32k_ck,
1740         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1741         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1742         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1743         .init           = &omap2_init_clksel_parent,
1744         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1745         .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
1746         .clksel         = gpt_clksel,
1747         .recalc         = &omap2_clksel_recalc,
1748 };
1749
1750 static struct clk gpt11_ick = {
1751         .name           = "gpt11_ick",
1752         .parent         = &l4_ck,
1753         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1754         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1755         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1756         .recalc         = &followparent_recalc,
1757 };
1758
1759 static struct clk gpt11_fck = {
1760         .name           = "gpt11_fck",
1761         .parent         = &func_32k_ck,
1762         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1763         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1764         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1765         .init           = &omap2_init_clksel_parent,
1766         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1767         .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
1768         .clksel         = gpt_clksel,
1769         .recalc         = &omap2_clksel_recalc,
1770 };
1771
1772 static struct clk gpt12_ick = {
1773         .name           = "gpt12_ick",
1774         .parent         = &l4_ck,
1775         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1776         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit14 */
1777         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1778         .recalc         = &followparent_recalc,
1779 };
1780
1781 static struct clk gpt12_fck = {
1782         .name           = "gpt12_fck",
1783         .parent         = &func_32k_ck,
1784         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1785         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1786         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1787         .init           = &omap2_init_clksel_parent,
1788         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1789         .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
1790         .clksel         = gpt_clksel,
1791         .recalc         = &omap2_clksel_recalc,
1792 };
1793
1794 static struct clk mcbsp1_ick = {
1795         .name           = "mcbsp1_ick",
1796         .parent         = &l4_ck,
1797         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1798         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1799         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1800         .recalc         = &followparent_recalc,
1801 };
1802
1803 static struct clk mcbsp1_fck = {
1804         .name           = "mcbsp1_fck",
1805         .parent         = &func_96m_ck,
1806         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1807         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1808         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1809         .recalc         = &followparent_recalc,
1810 };
1811
1812 static struct clk mcbsp2_ick = {
1813         .name           = "mcbsp2_ick",
1814         .parent         = &l4_ck,
1815         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1816         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1817         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1818         .recalc         = &followparent_recalc,
1819 };
1820
1821 static struct clk mcbsp2_fck = {
1822         .name           = "mcbsp2_fck",
1823         .parent         = &func_96m_ck,
1824         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1825         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1826         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1827         .recalc         = &followparent_recalc,
1828 };
1829
1830 static struct clk mcbsp3_ick = {
1831         .name           = "mcbsp3_ick",
1832         .parent         = &l4_ck,
1833         .flags          = CLOCK_IN_OMAP243X,
1834         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1835         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1836         .recalc         = &followparent_recalc,
1837 };
1838
1839 static struct clk mcbsp3_fck = {
1840         .name           = "mcbsp3_fck",
1841         .parent         = &func_96m_ck,
1842         .flags          = CLOCK_IN_OMAP243X,
1843         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1844         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1845         .recalc         = &followparent_recalc,
1846 };
1847
1848 static struct clk mcbsp4_ick = {
1849         .name           = "mcbsp4_ick",
1850         .parent         = &l4_ck,
1851         .flags          = CLOCK_IN_OMAP243X,
1852         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1853         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1854         .recalc         = &followparent_recalc,
1855 };
1856
1857 static struct clk mcbsp4_fck = {
1858         .name           = "mcbsp4_fck",
1859         .parent         = &func_96m_ck,
1860         .flags          = CLOCK_IN_OMAP243X,
1861         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1862         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1863         .recalc         = &followparent_recalc,
1864 };
1865
1866 static struct clk mcbsp5_ick = {
1867         .name           = "mcbsp5_ick",
1868         .parent         = &l4_ck,
1869         .flags          = CLOCK_IN_OMAP243X,
1870         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1871         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1872         .recalc         = &followparent_recalc,
1873 };
1874
1875 static struct clk mcbsp5_fck = {
1876         .name           = "mcbsp5_fck",
1877         .parent         = &func_96m_ck,
1878         .flags          = CLOCK_IN_OMAP243X,
1879         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1880         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1881         .recalc         = &followparent_recalc,
1882 };
1883
1884 static struct clk mcspi1_ick = {
1885         .name           = "mcspi_ick",
1886         .id             = 1,
1887         .parent         = &l4_ck,
1888         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1889         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1890         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1891         .recalc         = &followparent_recalc,
1892 };
1893
1894 static struct clk mcspi1_fck = {
1895         .name           = "mcspi_fck",
1896         .id             = 1,
1897         .parent         = &func_48m_ck,
1898         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1899         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1900         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1901         .recalc         = &followparent_recalc,
1902 };
1903
1904 static struct clk mcspi2_ick = {
1905         .name           = "mcspi_ick",
1906         .id             = 2,
1907         .parent         = &l4_ck,
1908         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1909         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1910         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1911         .recalc         = &followparent_recalc,
1912 };
1913
1914 static struct clk mcspi2_fck = {
1915         .name           = "mcspi_fck",
1916         .id             = 2,
1917         .parent         = &func_48m_ck,
1918         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1919         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1920         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1921         .recalc         = &followparent_recalc,
1922 };
1923
1924 static struct clk mcspi3_ick = {
1925         .name           = "mcspi_ick",
1926         .id             = 3,
1927         .parent         = &l4_ck,
1928         .flags          = CLOCK_IN_OMAP243X,
1929         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1930         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1931         .recalc         = &followparent_recalc,
1932 };
1933
1934 static struct clk mcspi3_fck = {
1935         .name           = "mcspi_fck",
1936         .id             = 3,
1937         .parent         = &func_48m_ck,
1938         .flags          = CLOCK_IN_OMAP243X,
1939         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1940         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1941         .recalc         = &followparent_recalc,
1942 };
1943
1944 static struct clk uart1_ick = {
1945         .name           = "uart1_ick",
1946         .parent         = &l4_ck,
1947         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1948         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1949         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1950         .recalc         = &followparent_recalc,
1951 };
1952
1953 static struct clk uart1_fck = {
1954         .name           = "uart1_fck",
1955         .parent         = &func_48m_ck,
1956         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1957         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1958         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1959         .recalc         = &followparent_recalc,
1960 };
1961
1962 static struct clk uart2_ick = {
1963         .name           = "uart2_ick",
1964         .parent         = &l4_ck,
1965         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1966         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1967         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1968         .recalc         = &followparent_recalc,
1969 };
1970
1971 static struct clk uart2_fck = {
1972         .name           = "uart2_fck",
1973         .parent         = &func_48m_ck,
1974         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1975         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1976         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1977         .recalc         = &followparent_recalc,
1978 };
1979
1980 static struct clk uart3_ick = {
1981         .name           = "uart3_ick",
1982         .parent         = &l4_ck,
1983         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1984         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1985         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1986         .recalc         = &followparent_recalc,
1987 };
1988
1989 static struct clk uart3_fck = {
1990         .name           = "uart3_fck",
1991         .parent         = &func_48m_ck,
1992         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1993         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1994         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1995         .recalc         = &followparent_recalc,
1996 };
1997
1998 static struct clk gpios_ick = {
1999         .name           = "gpios_ick",
2000         .parent         = &l4_ck,
2001         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2002         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2003         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2004         .recalc         = &followparent_recalc,
2005 };
2006
2007 static struct clk gpios_fck = {
2008         .name           = "gpios_fck",
2009         .parent         = &func_32k_ck,
2010         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2011         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
2012         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2013         .recalc         = &followparent_recalc,
2014 };
2015
2016 static struct clk mpu_wdt_ick = {
2017         .name           = "mpu_wdt_ick",
2018         .parent         = &l4_ck,
2019         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2020         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2021         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2022         .recalc         = &followparent_recalc,
2023 };
2024
2025 static struct clk mpu_wdt_fck = {
2026         .name           = "mpu_wdt_fck",
2027         .parent         = &func_32k_ck,
2028         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2029         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
2030         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2031         .recalc         = &followparent_recalc,
2032 };
2033
2034 static struct clk sync_32k_ick = {
2035         .name           = "sync_32k_ick",
2036         .parent         = &l4_ck,
2037         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2038         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2039         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
2040         .recalc         = &followparent_recalc,
2041 };
2042 static struct clk wdt1_ick = {
2043         .name           = "wdt1_ick",
2044         .parent         = &l4_ck,
2045         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2046         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2047         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
2048         .recalc         = &followparent_recalc,
2049 };
2050 static struct clk omapctrl_ick = {
2051         .name           = "omapctrl_ick",
2052         .parent         = &l4_ck,
2053         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2054         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2055         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
2056         .recalc         = &followparent_recalc,
2057 };
2058 static struct clk icr_ick = {
2059         .name           = "icr_ick",
2060         .parent         = &l4_ck,
2061         .flags          = CLOCK_IN_OMAP243X,
2062         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2063         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
2064         .recalc         = &followparent_recalc,
2065 };
2066
2067 static struct clk cam_ick = {
2068         .name           = "cam_ick",
2069         .parent         = &l4_ck,
2070         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2071         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2072         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2073         .recalc         = &followparent_recalc,
2074 };
2075
2076 static struct clk cam_fck = {
2077         .name           = "cam_fck",
2078         .parent         = &func_96m_ck,
2079         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2080         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2081         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2082         .recalc         = &followparent_recalc,
2083 };
2084
2085 static struct clk mailboxes_ick = {
2086         .name           = "mailboxes_ick",
2087         .parent         = &l4_ck,
2088         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2089         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2090         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
2091         .recalc         = &followparent_recalc,
2092 };
2093
2094 static struct clk wdt4_ick = {
2095         .name           = "wdt4_ick",
2096         .parent         = &l4_ck,
2097         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2098         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2099         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2100         .recalc         = &followparent_recalc,
2101 };
2102
2103 static struct clk wdt4_fck = {
2104         .name           = "wdt4_fck",
2105         .parent         = &func_32k_ck,
2106         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2107         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2108         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2109         .recalc         = &followparent_recalc,
2110 };
2111
2112 static struct clk wdt3_ick = {
2113         .name           = "wdt3_ick",
2114         .parent         = &l4_ck,
2115         .flags          = CLOCK_IN_OMAP242X,
2116         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2117         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2118         .recalc         = &followparent_recalc,
2119 };
2120
2121 static struct clk wdt3_fck = {
2122         .name           = "wdt3_fck",
2123         .parent         = &func_32k_ck,
2124         .flags          = CLOCK_IN_OMAP242X,
2125         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2126         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2127         .recalc         = &followparent_recalc,
2128 };
2129
2130 static struct clk mspro_ick = {
2131         .name           = "mspro_ick",
2132         .parent         = &l4_ck,
2133         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2134         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2135         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2136         .recalc         = &followparent_recalc,
2137 };
2138
2139 static struct clk mspro_fck = {
2140         .name           = "mspro_fck",
2141         .parent         = &func_96m_ck,
2142         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2143         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2144         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2145         .recalc         = &followparent_recalc,
2146 };
2147
2148 static struct clk mmc_ick = {
2149         .name           = "mmc_ick",
2150         .parent         = &l4_ck,
2151         .flags          = CLOCK_IN_OMAP242X,
2152         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2153         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2154         .recalc         = &followparent_recalc,
2155 };
2156
2157 static struct clk mmc_fck = {
2158         .name           = "mmc_fck",
2159         .parent         = &func_96m_ck,
2160         .flags          = CLOCK_IN_OMAP242X,
2161         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2162         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2163         .recalc         = &followparent_recalc,
2164 };
2165
2166 static struct clk fac_ick = {
2167         .name           = "fac_ick",
2168         .parent         = &l4_ck,
2169         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2170         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2171         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2172         .recalc         = &followparent_recalc,
2173 };
2174
2175 static struct clk fac_fck = {
2176         .name           = "fac_fck",
2177         .parent         = &func_12m_ck,
2178         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2179         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2180         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2181         .recalc         = &followparent_recalc,
2182 };
2183
2184 static struct clk eac_ick = {
2185         .name           = "eac_ick",
2186         .parent         = &l4_ck,
2187         .flags          = CLOCK_IN_OMAP242X,
2188         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2189         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2190         .recalc         = &followparent_recalc,
2191 };
2192
2193 static struct clk eac_fck = {
2194         .name           = "eac_fck",
2195         .parent         = &func_96m_ck,
2196         .flags          = CLOCK_IN_OMAP242X,
2197         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2198         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2199         .recalc         = &followparent_recalc,
2200 };
2201
2202 static struct clk hdq_ick = {
2203         .name           = "hdq_ick",
2204         .parent         = &l4_ck,
2205         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2206         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2207         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2208         .recalc         = &followparent_recalc,
2209 };
2210
2211 static struct clk hdq_fck = {
2212         .name           = "hdq_fck",
2213         .parent         = &func_12m_ck,
2214         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2215         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2216         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2217         .recalc         = &followparent_recalc,
2218 };
2219
2220 static struct clk i2c2_ick = {
2221         .name           = "i2c_ick",
2222         .id             = 2,
2223         .parent         = &l4_ck,
2224         .flags          = CLOCK_IN_OMAP242X,
2225         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2226         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2227         .recalc         = &followparent_recalc,
2228 };
2229
2230 static struct clk i2c2_fck = {
2231         .name           = "i2c_fck",
2232         .id             = 2,
2233         .parent         = &func_12m_ck,
2234         .flags          = CLOCK_IN_OMAP242X,
2235         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2236         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2237         .recalc         = &followparent_recalc,
2238 };
2239
2240 static struct clk i2chs2_fck = {
2241         .name           = "i2chs_fck",
2242         .id             = 2,
2243         .parent         = &func_96m_ck,
2244         .flags          = CLOCK_IN_OMAP243X,
2245         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2246         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
2247         .recalc         = &followparent_recalc,
2248 };
2249
2250 static struct clk i2c1_ick = {
2251         .name           = "i2c_ick",
2252         .id             = 1,
2253         .parent         = &l4_ck,
2254         .flags          = CLOCK_IN_OMAP242X,
2255         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2256         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2257         .recalc         = &followparent_recalc,
2258 };
2259
2260 static struct clk i2c1_fck = {
2261         .name           = "i2c_fck",
2262         .id             = 1,
2263         .parent         = &func_12m_ck,
2264         .flags          = CLOCK_IN_OMAP242X,
2265         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2266         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2267         .recalc         = &followparent_recalc,
2268 };
2269
2270 static struct clk i2chs1_fck = {
2271         .name           = "i2chs_fck",
2272         .id             = 1,
2273         .parent         = &func_96m_ck,
2274         .flags          = CLOCK_IN_OMAP243X,
2275         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2276         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
2277         .recalc         = &followparent_recalc,
2278 };
2279
2280 static struct clk vlynq_ick = {
2281         .name           = "vlynq_ick",
2282         .parent         = &core_l3_ck,
2283         .flags          = CLOCK_IN_OMAP242X,
2284         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2285         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2286         .recalc         = &followparent_recalc,
2287 };
2288
2289 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2290         { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2291         { .div = 0 }
2292 };
2293
2294 static const struct clksel_rate vlynq_fck_core_rates[] = {
2295         { .div = 1, .val = 1, .flags = RATE_IN_242X },
2296         { .div = 2, .val = 2, .flags = RATE_IN_242X },
2297         { .div = 3, .val = 3, .flags = RATE_IN_242X },
2298         { .div = 4, .val = 4, .flags = RATE_IN_242X },
2299         { .div = 6, .val = 6, .flags = RATE_IN_242X },
2300         { .div = 8, .val = 8, .flags = RATE_IN_242X },
2301         { .div = 9, .val = 9, .flags = RATE_IN_242X },
2302         { .div = 12, .val = 12, .flags = RATE_IN_242X },
2303         { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2304         { .div = 18, .val = 18, .flags = RATE_IN_242X },
2305         { .div = 0 }
2306 };
2307
2308 static const struct clksel vlynq_fck_clksel[] = {
2309         { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2310         { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
2311         { .parent = NULL }
2312 };
2313
2314 static struct clk vlynq_fck = {
2315         .name           = "vlynq_fck",
2316         .parent         = &func_96m_ck,
2317         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP,
2318         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2319         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2320         .init           = &omap2_init_clksel_parent,
2321         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
2322         .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
2323         .clksel         = vlynq_fck_clksel,
2324         .recalc         = &omap2_clksel_recalc,
2325         .round_rate     = &omap2_clksel_round_rate,
2326         .set_rate       = &omap2_clksel_set_rate
2327 };
2328
2329 static struct clk sdrc_ick = {
2330         .name           = "sdrc_ick",
2331         .parent         = &l4_ck,
2332         .flags          = CLOCK_IN_OMAP243X,
2333         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP2430_CM_ICLKEN3),
2334         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
2335         .recalc         = &followparent_recalc,
2336 };
2337
2338 static struct clk des_ick = {
2339         .name           = "des_ick",
2340         .parent         = &l4_ck,
2341         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2342         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2343         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
2344         .recalc         = &followparent_recalc,
2345 };
2346
2347 static struct clk sha_ick = {
2348         .name           = "sha_ick",
2349         .parent         = &l4_ck,
2350         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2351         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2352         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
2353         .recalc         = &followparent_recalc,
2354 };
2355
2356 static struct clk rng_ick = {
2357         .name           = "rng_ick",
2358         .parent         = &l4_ck,
2359         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2360         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2361         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
2362         .recalc         = &followparent_recalc,
2363 };
2364
2365 static struct clk aes_ick = {
2366         .name           = "aes_ick",
2367         .parent         = &l4_ck,
2368         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2369         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2370         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
2371         .recalc         = &followparent_recalc,
2372 };
2373
2374 static struct clk pka_ick = {
2375         .name           = "pka_ick",
2376         .parent         = &l4_ck,
2377         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2378         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2379         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
2380         .recalc         = &followparent_recalc,
2381 };
2382
2383 static struct clk usb_fck = {
2384         .name           = "usb_fck",
2385         .parent         = &func_48m_ck,
2386         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2387         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2388         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
2389         .recalc         = &followparent_recalc,
2390 };
2391
2392 static struct clk usbhs_ick = {
2393         .name           = "usbhs_ick",
2394         .parent         = &core_l3_ck,
2395         .flags          = CLOCK_IN_OMAP243X,
2396         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2397         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
2398         .recalc         = &followparent_recalc,
2399 };
2400
2401 static struct clk mmchs1_ick = {
2402         .name           = "mmchs1_ick",
2403         .parent         = &l4_ck,
2404         .flags          = CLOCK_IN_OMAP243X,
2405         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2406         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2407         .recalc         = &followparent_recalc,
2408 };
2409
2410 static struct clk mmchs1_fck = {
2411         .name           = "mmchs1_fck",
2412         .parent         = &func_96m_ck,
2413         .flags          = CLOCK_IN_OMAP243X,
2414         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2415         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2416         .recalc         = &followparent_recalc,
2417 };
2418
2419 static struct clk mmchs2_ick = {
2420         .name           = "mmchs2_ick",
2421         .parent         = &l4_ck,
2422         .flags          = CLOCK_IN_OMAP243X,
2423         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2424         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2425         .recalc         = &followparent_recalc,
2426 };
2427
2428 static struct clk mmchs2_fck = {
2429         .name           = "mmchs2_fck",
2430         .parent         = &func_96m_ck,
2431         .flags          = CLOCK_IN_OMAP243X,
2432         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2433         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2434         .recalc         = &followparent_recalc,
2435 };
2436
2437 static struct clk gpio5_ick = {
2438         .name           = "gpio5_ick",
2439         .parent         = &l4_ck,
2440         .flags          = CLOCK_IN_OMAP243X,
2441         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2442         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2443         .recalc         = &followparent_recalc,
2444 };
2445
2446 static struct clk gpio5_fck = {
2447         .name           = "gpio5_fck",
2448         .parent         = &func_32k_ck,
2449         .flags          = CLOCK_IN_OMAP243X,
2450         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2451         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2452         .recalc         = &followparent_recalc,
2453 };
2454
2455 static struct clk mdm_intc_ick = {
2456         .name           = "mdm_intc_ick",
2457         .parent         = &l4_ck,
2458         .flags          = CLOCK_IN_OMAP243X,
2459         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2460         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
2461         .recalc         = &followparent_recalc,
2462 };
2463
2464 static struct clk mmchsdb1_fck = {
2465         .name           = "mmchsdb1_fck",
2466         .parent         = &func_32k_ck,
2467         .flags          = CLOCK_IN_OMAP243X,
2468         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2469         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
2470         .recalc         = &followparent_recalc,
2471 };
2472
2473 static struct clk mmchsdb2_fck = {
2474         .name           = "mmchsdb2_fck",
2475         .parent         = &func_32k_ck,
2476         .flags          = CLOCK_IN_OMAP243X,
2477         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2478         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
2479         .recalc         = &followparent_recalc,
2480 };
2481
2482 /*
2483  * This clock is a composite clock which does entire set changes then
2484  * forces a rebalance. It keys on the MPU speed, but it really could
2485  * be any key speed part of a set in the rate table.
2486  *
2487  * to really change a set, you need memory table sets which get changed
2488  * in sram, pre-notifiers & post notifiers, changing the top set, without
2489  * having low level display recalc's won't work... this is why dpm notifiers
2490  * work, isr's off, walk a list of clocks already _off_ and not messing with
2491  * the bus.
2492  *
2493  * This clock should have no parent. It embodies the entire upper level
2494  * active set. A parent will mess up some of the init also.
2495  */
2496 static struct clk virt_prcm_set = {
2497         .name           = "virt_prcm_set",
2498         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2499                                 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
2500         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
2501         .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
2502         .set_rate       = &omap2_select_table_rate,
2503         .round_rate     = &omap2_round_to_table_rate,
2504 };
2505
2506 static struct clk *onchip_clks[] __initdata = {
2507         /* external root sources */
2508         &func_32k_ck,
2509         &osc_ck,
2510         &sys_ck,
2511         &alt_ck,
2512         /* internal analog sources */
2513         &dpll_ck,
2514         &apll96_ck,
2515         &apll54_ck,
2516         /* internal prcm root sources */
2517         &func_54m_ck,
2518         &core_ck,
2519         &func_96m_ck,
2520         &func_48m_ck,
2521         &func_12m_ck,
2522         &wdt1_osc_ck,
2523         &sys_clkout_src,
2524         &sys_clkout,
2525         &sys_clkout2_src,
2526         &sys_clkout2,
2527         &emul_ck,
2528         /* mpu domain clocks */
2529         &mpu_ck,
2530         /* dsp domain clocks */
2531         &iva2_1_fck,            /* 2430 */
2532         &iva2_1_ick,
2533         &dsp_ick,               /* 2420 */
2534         &dsp_fck,
2535         &iva1_ifck,
2536         &iva1_mpu_int_ifck,
2537         /* GFX domain clocks */
2538         &gfx_3d_fck,
2539         &gfx_2d_fck,
2540         &gfx_ick,
2541         /* Modem domain clocks */
2542         &mdm_ick,
2543         &mdm_osc_ck,
2544         /* DSS domain clocks */
2545         &dss_ick,
2546         &dss1_fck,
2547         &dss2_fck,
2548         &dss_54m_fck,
2549         /* L3 domain clocks */
2550         &core_l3_ck,
2551         &ssi_ssr_sst_fck,
2552         &usb_l4_ick,
2553         /* L4 domain clocks */
2554         &l4_ck,                 /* used as both core_l4 and wu_l4 */
2555         &ssi_l4_ick,
2556         /* virtual meta-group clock */
2557         &virt_prcm_set,
2558         /* general l4 interface ck, multi-parent functional clk */
2559         &gpt1_ick,
2560         &gpt1_fck,
2561         &gpt2_ick,
2562         &gpt2_fck,
2563         &gpt3_ick,
2564         &gpt3_fck,
2565         &gpt4_ick,
2566         &gpt4_fck,
2567         &gpt5_ick,
2568         &gpt5_fck,
2569         &gpt6_ick,
2570         &gpt6_fck,
2571         &gpt7_ick,
2572         &gpt7_fck,
2573         &gpt8_ick,
2574         &gpt8_fck,
2575         &gpt9_ick,
2576         &gpt9_fck,
2577         &gpt10_ick,
2578         &gpt10_fck,
2579         &gpt11_ick,
2580         &gpt11_fck,
2581         &gpt12_ick,
2582         &gpt12_fck,
2583         &mcbsp1_ick,
2584         &mcbsp1_fck,
2585         &mcbsp2_ick,
2586         &mcbsp2_fck,
2587         &mcbsp3_ick,
2588         &mcbsp3_fck,
2589         &mcbsp4_ick,
2590         &mcbsp4_fck,
2591         &mcbsp5_ick,
2592         &mcbsp5_fck,
2593         &mcspi1_ick,
2594         &mcspi1_fck,
2595         &mcspi2_ick,
2596         &mcspi2_fck,
2597         &mcspi3_ick,
2598         &mcspi3_fck,
2599         &uart1_ick,
2600         &uart1_fck,
2601         &uart2_ick,
2602         &uart2_fck,
2603         &uart3_ick,
2604         &uart3_fck,
2605         &gpios_ick,
2606         &gpios_fck,
2607         &mpu_wdt_ick,
2608         &mpu_wdt_fck,
2609         &sync_32k_ick,
2610         &wdt1_ick,
2611         &omapctrl_ick,
2612         &icr_ick,
2613         &cam_fck,
2614         &cam_ick,
2615         &mailboxes_ick,
2616         &wdt4_ick,
2617         &wdt4_fck,
2618         &wdt3_ick,
2619         &wdt3_fck,
2620         &mspro_ick,
2621         &mspro_fck,
2622         &mmc_ick,
2623         &mmc_fck,
2624         &fac_ick,
2625         &fac_fck,
2626         &eac_ick,
2627         &eac_fck,
2628         &hdq_ick,
2629         &hdq_fck,
2630         &i2c1_ick,
2631         &i2c1_fck,
2632         &i2chs1_fck,
2633         &i2c2_ick,
2634         &i2c2_fck,
2635         &i2chs2_fck,
2636         &vlynq_ick,
2637         &vlynq_fck,
2638         &sdrc_ick,
2639         &des_ick,
2640         &sha_ick,
2641         &rng_ick,
2642         &aes_ick,
2643         &pka_ick,
2644         &usb_fck,
2645         &usbhs_ick,
2646         &mmchs1_ick,
2647         &mmchs1_fck,
2648         &mmchs2_ick,
2649         &mmchs2_fck,
2650         &gpio5_ick,
2651         &gpio5_fck,
2652         &mdm_intc_ick,
2653         &mmchsdb1_fck,
2654         &mmchsdb2_fck,
2655 };
2656
2657 #endif