arch/arm/mach-omap2/clock.h

   1 /*
   2  *  linux/arch/arm/mach-omap24xx/clock.h
   3  *
   4  *  Copyright (C) 2005 Texas Instruments Inc.
   5  *  Richard Woodruff <r-woodruff2@ti.com>
   6  *  Created for OMAP2.
   7  *
   8  *  Copyright (C) 2004 Nokia corporation
   9  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  10  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
  18 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
  19
  20 #include "prm.h"
  21 #include "cm.h"
  22 #include "prm_regbits_24xx.h"
  23 #include "cm_regbits_24xx.h"
  24
  25 static void omap2_sys_clk_recalc(struct clk * clk);
  26 static void omap2_clksel_recalc(struct clk * clk);
  27 static void omap2_followparent_recalc(struct clk * clk);
  28 static void omap2_propagate_rate(struct clk * clk);
  29 static void omap2_mpu_recalc(struct clk * clk);
  30 static int omap2_select_table_rate(struct clk * clk, unsigned long rate);
  31 static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate);
  32 static void omap2_clk_disable(struct clk *clk);
  33 static void omap2_sys_clk_recalc(struct clk * clk);
  34 static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val);
  35 static u32 omap2_clksel_get_divisor(struct clk *clk);
  36 static void omap2_dpll_recalc(struct clk *clk);
  37
  38 #define RATE_IN_242X    (1 << 0)
  39 #define RATE_IN_243X    (1 << 1)
  40 #define RATE_IN_343X    (1 << 2)
  41
  42 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  43  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  44  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  45  */
  46 struct prcm_config {
  47         unsigned long xtal_speed;       /* crystal rate */
  48         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  49         unsigned long mpu_speed;        /* speed of MPU */
  50         unsigned long cm_clksel_mpu;    /* mpu divider */
  51         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  52         unsigned long cm_clksel_gfx;    /* gfx dividers */
  53         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  54         unsigned long cm_clksel1_pll;   /* m,n */
  55         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  56         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  57         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  58         unsigned char flags;
  59 };
  60
  61 /* Mask for clksel which support parent settign in set_rate */
  62 #define SRC_SEL_MASK (CM_CORE_SEL1 | CM_CORE_SEL2 | CM_WKUP_SEL1 | \
  63                         CM_PLL_SEL1 | CM_PLL_SEL2 | CM_SYSCLKOUT_SEL1)
  64
  65 /* Mask for clksel regs which support rate operations */
  66 #define SRC_RATE_SEL_MASK (SRC_SEL_MASK | CM_MPU_SEL1 | CM_DSP_SEL1 | \
  67                         CM_GFX_SEL1 | CM_MODEM_SEL1)
  68
  69 /*
  70  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  71  * These configurations are characterized by voltage and speed for clocks.
  72  * The device is only validated for certain combinations. One way to express
  73  * these combinations is via the 'ratio's' which the clocks operate with
  74  * respect to each other. These ratio sets are for a given voltage/DPLL
  75  * setting. All configurations can be described by a DPLL setting and a ratio
  76  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  77  *
  78  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  79  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  80  * 2430 (iva2.1, NOdsp, mdm)
  81  */
  82
  83 /* Core fields for cm_clksel, not ratio governed */
  84 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  85 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  86 #define RX_CLKSEL_SSI                   (0x5 << 20)
  87
  88 /*-------------------------------------------------------------------------
  89  * Voltage/DPLL ratios
  90  *-------------------------------------------------------------------------*/
  91
  92 /* 2430 Ratio's, 2430-Ratio Config 1 */
  93 #define R1_CLKSEL_L3                    (4 << 0)
  94 #define R1_CLKSEL_L4                    (2 << 5)
  95 #define R1_CLKSEL_USB                   (4 << 25)
  96 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
  97                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  98                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
  99 #define R1_CLKSEL_MPU                   (2 << 0)
 100 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
 101 #define R1_CLKSEL_DSP                   (2 << 0)
 102 #define R1_CLKSEL_DSP_IF                (2 << 5)
 103 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
 104 #define R1_CLKSEL_GFX                   (2 << 0)
 105 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
 106 #define R1_CLKSEL_MDM                   (4 << 0)
 107 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
 108
 109 /* 2430-Ratio Config 2 */
 110 #define R2_CLKSEL_L3                    (6 << 0)
 111 #define R2_CLKSEL_L4                    (2 << 5)
 112 #define R2_CLKSEL_USB                   (2 << 25)
 113 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
 114                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 115                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
 116 #define R2_CLKSEL_MPU                   (2 << 0)
 117 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 118 #define R2_CLKSEL_DSP                   (2 << 0)
 119 #define R2_CLKSEL_DSP_IF                (3 << 5)
 120 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 121 #define R2_CLKSEL_GFX                   (2 << 0)
 122 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 123 #define R2_CLKSEL_MDM                   (6 << 0)
 124 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 125
 126 /* 2430-Ratio Bootm (BYPASS) */
 127 #define RB_CLKSEL_L3                    (1 << 0)
 128 #define RB_CLKSEL_L4                    (1 << 5)
 129 #define RB_CLKSEL_USB                   (1 << 25)
 130 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 131                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 132                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 133 #define RB_CLKSEL_MPU                   (1 << 0)
 134 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 135 #define RB_CLKSEL_DSP                   (1 << 0)
 136 #define RB_CLKSEL_DSP_IF                (1 << 5)
 137 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 138 #define RB_CLKSEL_GFX                   (1 << 0)
 139 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 140 #define RB_CLKSEL_MDM                   (1 << 0)
 141 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 142
 143 /* 2420 Ratio Equivalents */
 144 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 145 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 146
 147 /* 2420-PRCM III 532MHz core */
 148 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 149 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 150 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 151 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 152                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 153                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 154                                         RIII_CLKSEL_L3
 155 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 156 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 157 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 158 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 159 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 160 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 161 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 162 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 163                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 164                                         RIII_CLKSEL_DSP
 165 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 166 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 167
 168 /* 2420-PRCM II 600MHz core */
 169 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 170 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 171 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 172 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 173                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 174                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 175                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 176 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 177 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 178 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 179 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 180 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 181 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 182 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 183 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 184                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 185                                         RII_CLKSEL_DSP
 186 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 187 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 188
 189 /* 2420-PRCM I 660MHz core */
 190 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 191 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 192 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 193 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 194                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 195                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 196                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 197 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 198 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 199 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 200 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 201 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 202 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 203 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 204 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 205                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 206                                         RI_CLKSEL_DSP
 207 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 208 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 209
 210 /* 2420-PRCM VII (boot) */
 211 #define RVII_CLKSEL_L3                  (1 << 0)
 212 #define RVII_CLKSEL_L4                  (1 << 5)
 213 #define RVII_CLKSEL_DSS1                (1 << 8)
 214 #define RVII_CLKSEL_DSS2                (0 << 13)
 215 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 216 #define RVII_CLKSEL_SSI                 (1 << 20)
 217 #define RVII_CLKSEL_USB                 (1 << 25)
 218
 219 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 220                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 221                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 222
 223 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 224 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 225
 226 #define RVII_CLKSEL_DSP                 (1 << 0)
 227 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 228 #define RVII_SYNC_DSP                   (0 << 7)
 229 #define RVII_CLKSEL_IVA                 (1 << 8)
 230 #define RVII_SYNC_IVA                   (0 << 13)
 231 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 232                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 233
 234 #define RVII_CLKSEL_GFX                 (1 << 0)
 235 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 236
 237 /*-------------------------------------------------------------------------
 238  * 2430 Target modes: Along with each configuration the CPU has several
 239  * modes which goes along with them. Modes mainly are the addition of
 240  * describe DPLL combinations to go along with a ratio.
 241  *-------------------------------------------------------------------------*/
 242
 243 /* Hardware governed */
 244 #define MX_48M_SRC                      (0 << 3)
 245 #define MX_54M_SRC                      (0 << 5)
 246 #define MX_APLLS_CLIKIN_12              (3 << 23)
 247 #define MX_APLLS_CLIKIN_13              (2 << 23)
 248 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 249
 250 /*
 251  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 252  * #2   (ratio1) baseport-target
 253  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 254  */
 255 #define M5A_DPLL_MULT_12                (133 << 12)
 256 #define M5A_DPLL_DIV_12                 (5 << 8)
 257 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 258                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 259                                         MX_APLLS_CLIKIN_12
 260 #define M5A_DPLL_MULT_13                (266 << 12)
 261 #define M5A_DPLL_DIV_13                 (12 << 8)
 262 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 263                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 264                                         MX_APLLS_CLIKIN_13
 265 #define M5A_DPLL_MULT_19                (180 << 12)
 266 #define M5A_DPLL_DIV_19                 (12 << 8)
 267 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 268                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 269                                         MX_APLLS_CLIKIN_19_2
 270 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 271 #define M5B_DPLL_MULT_12                (50 << 12)
 272 #define M5B_DPLL_DIV_12                 (2 << 8)
 273 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 274                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 275                                         MX_APLLS_CLIKIN_12
 276 #define M5B_DPLL_MULT_13                (200 << 12)
 277 #define M5B_DPLL_DIV_13                 (12 << 8)
 278
 279 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 280                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 281                                         MX_APLLS_CLIKIN_13
 282 #define M5B_DPLL_MULT_19                (125 << 12)
 283 #define M5B_DPLL_DIV_19                 (31 << 8)
 284 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 285                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 286                                         MX_APLLS_CLIKIN_19_2
 287 /*
 288  * #4   (ratio2)
 289  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 290  */
 291 #define M3_DPLL_MULT_12                 (55 << 12)
 292 #define M3_DPLL_DIV_12                  (1 << 8)
 293 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 294                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 295                                         MX_APLLS_CLIKIN_12
 296 #define M3_DPLL_MULT_13                 (330 << 12)
 297 #define M3_DPLL_DIV_13                  (12 << 8)
 298 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 299                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 300                                         MX_APLLS_CLIKIN_13
 301 #define M3_DPLL_MULT_19                 (275 << 12)
 302 #define M3_DPLL_DIV_19                  (15 << 8)
 303 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 304                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 305                                         MX_APLLS_CLIKIN_19_2
 306 /* boot (boot) */
 307 #define MB_DPLL_MULT                    (1 << 12)
 308 #define MB_DPLL_DIV                     (0 << 8)
 309 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 310                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 311
 312 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 313                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 314
 315 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 316                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 317
 318 /*
 319  * 2430 - chassis (sedna)
 320  * 165 (ratio1) same as above #2
 321  * 150 (ratio1)
 322  * 133 (ratio2) same as above #4
 323  * 110 (ratio2) same as above #3
 324  * 104 (ratio2)
 325  * boot (boot)
 326  */
 327
 328 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 329 #define MI_DPLL_MULT_12                 (55 << 12)
 330 #define MI_DPLL_DIV_12                  (1 << 8)
 331 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 332                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 333                                         MX_APLLS_CLIKIN_12
 334
 335 /*
 336  * 2420 Equivalent - mode registers
 337  * PRCM II , target DPLL = 2*300MHz = 600MHz
 338  */
 339 #define MII_DPLL_MULT_12                (50 << 12)
 340 #define MII_DPLL_DIV_12                 (1 << 8)
 341 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 342                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 343                                         MX_APLLS_CLIKIN_12
 344 #define MII_DPLL_MULT_13                (300 << 12)
 345 #define MII_DPLL_DIV_13                 (12 << 8)
 346 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 347                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 348                                         MX_APLLS_CLIKIN_13
 349
 350 /* PRCM III target DPLL = 2*266 = 532MHz*/
 351 #define MIII_DPLL_MULT_12               (133 << 12)
 352 #define MIII_DPLL_DIV_12                (5 << 8)
 353 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 354                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 355                                         MX_APLLS_CLIKIN_12
 356 #define MIII_DPLL_MULT_13               (266 << 12)
 357 #define MIII_DPLL_DIV_13                (12 << 8)
 358 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 359                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 360                                         MX_APLLS_CLIKIN_13
 361
 362 /* PRCM VII (boot bypass) */
 363 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 364 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 365
 366 /* High and low operation value */
 367 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 368 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 369
 370 /*
 371  * These represent optimal values for common parts, it won't work for all.
 372  * As long as you scale down, most parameters are still work, they just
 373  * become sub-optimal. The RFR value goes in the opposite direction. If you
 374  * don't adjust it down as your clock period increases the refresh interval
 375  * will not be met. Setting all parameters for complete worst case may work,
 376  * but may cut memory performance by 2x. Due to errata the DLLs need to be
 377  * unlocked and their value needs run time calibration. A dynamic call is
 378  * need for that as no single right value exists acorss production samples.
 379  *
 380  * Only the FULL speed values are given. Current code is such that rate
 381  * changes must be made at DPLLoutx2. The actual value adjustment for low
 382  * frequency operation will be handled by omap_set_performance()
 383  *
 384  * By having the boot loader boot up in the fastest L4 speed available likely
 385  * will result in something which you can switch between.
 386  */
 387 #define V24XX_SDRC_RFR_CTRL_165MHz      (0x00044c00 | 1)
 388 #define V24XX_SDRC_RFR_CTRL_133MHz      (0x0003de00 | 1)
 389 #define V24XX_SDRC_RFR_CTRL_100MHz      (0x0002da01 | 1)
 390 #define V24XX_SDRC_RFR_CTRL_110MHz      (0x0002da01 | 1) /* Need to calc */
 391 #define V24XX_SDRC_RFR_CTRL_BYPASS      (0x00005000 | 1) /* Need to calc */
 392
 393 /* MPU speed defines */
 394 #define S12M    12000000
 395 #define S13M    13000000
 396 #define S19M    19200000
 397 #define S26M    26000000
 398 #define S100M   100000000
 399 #define S133M   133000000
 400 #define S150M   150000000
 401 #define S165M   165000000
 402 #define S200M   200000000
 403 #define S266M   266000000
 404 #define S300M   300000000
 405 #define S330M   330000000
 406 #define S400M   400000000
 407 #define S532M   532000000
 408 #define S600M   600000000
 409 #define S660M   660000000
 410
 411 /*-------------------------------------------------------------------------
 412  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 413  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 414  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 415  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 416  *
 417  * Filling in table based on H4 boards and 2430-SDPs variants available.
 418  * There are quite a few more rates combinations which could be defined.
 419  *
 420  * When multiple values are defined the start up will try and choose the
 421  * fastest one. If a 'fast' value is defined, then automatically, the /2
 422  * one should be included as it can be used.    Generally having more that
 423  * one fast set does not make sense, as static timings need to be changed
 424  * to change the set.    The exception is the bypass setting which is
 425  * availble for low power bypass.
 426  *
 427  * Note: This table needs to be sorted, fastest to slowest.
 428  *-------------------------------------------------------------------------*/
 429 static struct prcm_config rate_table[] = {
 430         /* PRCM I - FAST */
 431         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 432                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 433                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 434                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_165MHz,
 435                 RATE_IN_242X},
 436
 437         /* PRCM II - FAST */
 438         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 439                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 440                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 441                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 442                 RATE_IN_242X},
 443
 444         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 445                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 446                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 447                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 448                 RATE_IN_242X},
 449
 450         /* PRCM III - FAST */
 451         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 452                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 453                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 454                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 455                 RATE_IN_242X},
 456
 457         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 458                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 459                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 460                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 461                 RATE_IN_242X},
 462
 463         /* PRCM II - SLOW */
 464         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 465                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 466                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 467                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 468                 RATE_IN_242X},
 469
 470         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 471                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 472                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 473                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 474                 RATE_IN_242X},
 475
 476         /* PRCM III - SLOW */
 477         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 478                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 479                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 480                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 481                 RATE_IN_242X},
 482
 483         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 484                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 485                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 486                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 487                 RATE_IN_242X},
 488
 489         /* PRCM-VII (boot-bypass) */
 490         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 491                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 492                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 493                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
 494                 RATE_IN_242X},
 495
 496         /* PRCM-VII (boot-bypass) */
 497         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 498                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 499                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 500                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
 501                 RATE_IN_242X},
 502
 503         /* PRCM #3 - ratio2 (ES2) - FAST */
 504         {S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 505                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 506                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 507                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 508                 V24XX_SDRC_RFR_CTRL_110MHz,
 509                 RATE_IN_243X},
 510
 511         /* PRCM #5a - ratio1 - FAST */
 512         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 513                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 514                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 515                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 516                 V24XX_SDRC_RFR_CTRL_133MHz,
 517                 RATE_IN_243X},
 518
 519         /* PRCM #5b - ratio1 - FAST */
 520         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 521                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 522                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 523                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 524                 V24XX_SDRC_RFR_CTRL_100MHz,
 525                 RATE_IN_243X},
 526
 527         /* PRCM #3 - ratio2 (ES2) - SLOW */
 528         {S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 529                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 530                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 531                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 532                 V24XX_SDRC_RFR_CTRL_110MHz,
 533                 RATE_IN_243X},
 534
 535         /* PRCM #5a - ratio1 - SLOW */
 536         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 537                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 538                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 539                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 540                 V24XX_SDRC_RFR_CTRL_133MHz,
 541                 RATE_IN_243X},
 542
 543         /* PRCM #5b - ratio1 - SLOW*/
 544         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 545                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 546                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 547                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 548                 V24XX_SDRC_RFR_CTRL_100MHz,
 549                 RATE_IN_243X},
 550
 551         /* PRCM-boot/bypass */
 552         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 553                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 554                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 555                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 556                 V24XX_SDRC_RFR_CTRL_BYPASS,
 557                 RATE_IN_243X},
 558
 559         /* PRCM-boot/bypass */
 560         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 561                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 562                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 563                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 564                 V24XX_SDRC_RFR_CTRL_BYPASS,
 565                 RATE_IN_243X},
 566
 567         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 568 };
 569
 570 /*-------------------------------------------------------------------------
 571  * 24xx clock tree.
 572  *
 573  * NOTE:In many cases here we are assigning a 'default' parent. In many
 574  *      cases the parent is selectable. The get/set parent calls will also
 575  *      switch sources.
 576  *
 577  *      Many some clocks say always_enabled, but they can be auto idled for
 578  *      power savings. They will always be available upon clock request.
 579  *
 580  *      Several sources are given initial rates which may be wrong, this will
 581  *      be fixed up in the init func.
 582  *
 583  *      Things are broadly separated below by clock domains. It is
 584  *      noteworthy that most periferals have dependencies on multiple clock
 585  *      domains. Many get their interface clocks from the L4 domain, but get
 586  *      functional clocks from fixed sources or other core domain derived
 587  *      clocks.
 588  *-------------------------------------------------------------------------*/
 589
 590 /* Base external input clocks */
 591 static struct clk func_32k_ck = {
 592         .name           = "func_32k_ck",
 593         .rate           = 32000,
 594         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 595                                 RATE_FIXED | ALWAYS_ENABLED,
 596 };
 597
 598 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 599 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 600         .name           = "osc_ck",
 601         .rate           = 26000000,             /* fixed up in clock init */
 602         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 603                                 RATE_FIXED | RATE_PROPAGATES,
 604 };
 605
 606 /* With out modem likely 12MHz, with modem likely 13MHz */
 607 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 608         .name           = "sys_ck",             /* ~ ref_clk also */
 609         .parent         = &osc_ck,
 610         .rate           = 13000000,
 611         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 612                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 613         .rate_offset    = OMAP_SYSCLKDIV_SHIFT, /* sysclkdiv 1 or 2, already handled or no boot */
 614         .recalc         = &omap2_sys_clk_recalc,
 615 };
 616
 617 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 618         .name           = "alt_ck",
 619         .rate           = 54000000,
 620         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 621                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 622         .recalc         = &omap2_propagate_rate,
 623 };
 624
 625 /*
 626  * Analog domain root source clocks
 627  */
 628
 629 /* dpll_ck, is broken out in to special cases through clksel */
 630 static struct clk dpll_ck = {
 631         .name           = "dpll_ck",
 632         .parent         = &sys_ck,              /* Can be func_32k also */
 633         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 634                                 RATE_PROPAGATES | RATE_CKCTL | CM_PLL_SEL1 |
 635                                 ALWAYS_ENABLED,
 636         .recalc         = &omap2_dpll_recalc,
 637 };
 638
 639 static struct clk apll96_ck = {
 640         .name           = "apll96_ck",
 641         .parent         = &sys_ck,
 642         .rate           = 96000000,
 643         .flags          = CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X |
 644                                 RATE_FIXED | RATE_PROPAGATES,
 645         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 646         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 647         .recalc         = &omap2_propagate_rate,
 648 };
 649
 650 static struct clk apll54_ck = {
 651         .name           = "apll54_ck",
 652         .parent         = &sys_ck,
 653         .rate           = 54000000,
 654         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 655                                 RATE_FIXED | RATE_PROPAGATES,
 656         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 657         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 658         .recalc         = &omap2_propagate_rate,
 659 };
 660
 661 /*
 662  * PRCM digital base sources
 663  */
 664 static struct clk func_54m_ck = {
 665         .name           = "func_54m_ck",
 666         .parent         = &apll54_ck,   /* can also be alt_clk */
 667         .rate           = 54000000,
 668         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 669                                 RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES |
 670                                 PARENT_CONTROLS_CLOCK,
 671         .src_offset     = OMAP24XX_54M_SOURCE_SHIFT,
 672         .recalc         = &omap2_propagate_rate,
 673 };
 674
 675 static struct clk core_ck = {
 676         .name           = "core_ck",
 677         .parent         = &dpll_ck,             /* can also be 32k */
 678         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 679                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 680         .recalc         = &omap2_propagate_rate,
 681 };
 682
 683 static struct clk func_96m_ck = {
 684         .name           = "func_96m_ck",
 685         .parent         = &apll96_ck,
 686         .rate           = 96000000,
 687         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 688                                 RATE_FIXED | RATE_PROPAGATES |
 689                                 PARENT_CONTROLS_CLOCK,
 690         .recalc         = &omap2_propagate_rate,
 691 };
 692
 693 static struct clk func_48m_ck = {
 694         .name           = "func_48m_ck",
 695         .parent         = &apll96_ck,    /* 96M or Alt */
 696         .rate           = 48000000,
 697         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 698                                 RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES |
 699                                 PARENT_CONTROLS_CLOCK,
 700         .src_offset     = OMAP24XX_48M_SOURCE_SHIFT,
 701         .recalc         = &omap2_propagate_rate,
 702 };
 703
 704 static struct clk func_12m_ck = {
 705         .name           = "func_12m_ck",
 706         .parent         = &func_48m_ck,
 707         .rate           = 12000000,
 708         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 709                                 RATE_FIXED | RATE_PROPAGATES |
 710                                 PARENT_CONTROLS_CLOCK,
 711         .recalc         = &omap2_propagate_rate,
 712 };
 713
 714 /* Secure timer, only available in secure mode */
 715 static struct clk wdt1_osc_ck = {
 716         .name           = "ck_wdt1_osc",
 717         .parent         = &osc_ck,
 718         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 719         .recalc         = &omap2_followparent_recalc,
 720 };
 721
 722 static struct clk sys_clkout = {
 723         .name           = "sys_clkout",
 724         .parent         = &func_54m_ck,
 725         .rate           = 54000000,
 726         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 727                                 CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
 728         .src_offset     = OMAP24XX_CLKOUT_SOURCE_SHIFT,
 729         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 730         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 731         .rate_offset    = OMAP24XX_CLKOUT_DIV_SHIFT,
 732         .recalc         = &omap2_clksel_recalc,
 733 };
 734
 735 /* In 2430, new in 2420 ES2 */
 736 static struct clk sys_clkout2 = {
 737         .name           = "sys_clkout2",
 738         .parent         = &func_54m_ck,
 739         .rate           = 54000000,
 740         .flags          = CLOCK_IN_OMAP242X | CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
 741         .src_offset     = OMAP2420_CLKOUT2_SOURCE_SHIFT,
 742         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 743         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 744         .rate_offset    = OMAP2420_CLKOUT2_DIV_SHIFT,
 745         .recalc         = &omap2_clksel_recalc,
 746 };
 747
 748 static struct clk emul_ck = {
 749         .name           = "emul_ck",
 750         .parent         = &func_54m_ck,
 751         .flags          = CLOCK_IN_OMAP242X,
 752         .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL,
 753         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 754         .recalc         = &omap2_propagate_rate,
 755
 756 };
 757
 758 /*
 759  * MPU clock domain
 760  *      Clocks:
 761  *              MPU_FCLK, MPU_ICLK
 762  *              INT_M_FCLK, INT_M_I_CLK
 763  *
 764  * - Individual clocks are hardware managed.
 765  * - Base divider comes from: CM_CLKSEL_MPU
 766  *
 767  */
 768 static struct clk mpu_ck = {    /* Control cpu */
 769         .name           = "mpu_ck",
 770         .parent         = &core_ck,
 771         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL |
 772                                 ALWAYS_ENABLED | CM_MPU_SEL1 | DELAYED_APP |
 773                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
 774         .rate_offset    = OMAP24XX_CLKSEL_MPU_SHIFT,    /* bits 0-4 */
 775         .recalc         = &omap2_clksel_recalc,
 776 };
 777
 778 /*
 779  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
 780  * Clocks:
 781  *      2430: IVA2.1_FCLK, IVA2.1_ICLK
 782  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
 783  */
 784 static struct clk iva2_1_fck = {
 785         .name           = "iva2_1_fck",
 786         .parent         = &core_ck,
 787         .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
 788                                 DELAYED_APP | RATE_PROPAGATES |
 789                                 CONFIG_PARTICIPANT,
 790         .rate_offset    = OMAP24XX_CLKSEL_DSP_SHIFT,
 791         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 792         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
 793         .recalc         = &omap2_clksel_recalc,
 794 };
 795
 796 static struct clk iva2_1_ick = {
 797         .name           = "iva2_1_ick",
 798         .parent         = &iva2_1_fck,
 799         .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
 800                                 DELAYED_APP | CONFIG_PARTICIPANT,
 801         .rate_offset    = OMAP24XX_CLKSEL_DSP_IF_SHIFT,
 802         .recalc         = &omap2_clksel_recalc,
 803 };
 804
 805 /*
 806  * Won't be too specific here. The core clock comes into this block
 807  * it is divided then tee'ed. One branch goes directly to xyz enable
 808  * controls. The other branch gets further divided by 2 then possibly
 809  * routed into a synchronizer and out of clocks abc.
 810  */
 811 static struct clk dsp_fck = {
 812         .name           = "dsp_fck",
 813         .parent         = &core_ck,
 814         .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
 815                         DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
 816         .rate_offset    = OMAP24XX_CLKSEL_DSP_SHIFT,
 817         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 818         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
 819         .recalc         = &omap2_clksel_recalc,
 820 };
 821
 822 static struct clk dsp_ick = {
 823         .name           = "dsp_ick",     /* apparently ipi and isp */
 824         .parent         = &dsp_fck,
 825         .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
 826                                 DELAYED_APP | CONFIG_PARTICIPANT,
 827         .rate_offset    = OMAP24XX_CLKSEL_DSP_IF_SHIFT,
 828         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
 829         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,            /* for ipi */
 830         .recalc         = &omap2_clksel_recalc,
 831 };
 832
 833 static struct clk iva1_ifck = {
 834         .name           = "iva1_ifck",
 835         .parent         = &core_ck,
 836         .flags          = CLOCK_IN_OMAP242X | CM_DSP_SEL1 | RATE_CKCTL |
 837                         CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
 838         .rate_offset    = OMAP2420_CLKSEL_IVA_SHIFT,
 839         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 840         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
 841         .recalc         = &omap2_clksel_recalc,
 842 };
 843
 844 /* IVA1 mpu/int/i/f clocks are /2 of parent */
 845 static struct clk iva1_mpu_int_ifck = {
 846         .name           = "iva1_mpu_int_ifck",
 847         .parent         = &iva1_ifck,
 848         .flags          = CLOCK_IN_OMAP242X,
 849         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 850         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
 851         .recalc         = &omap2_clksel_recalc,
 852 };
 853
 854 /*
 855  * L3 clock domain
 856  * L3 clocks are used for both interface and functional clocks to
 857  * multiple entities. Some of these clocks are completely managed
 858  * by hardware, and some others allow software control. Hardware
 859  * managed ones general are based on directly CLK_REQ signals and
 860  * various auto idle settings. The functional spec sets many of these
 861  * as 'tie-high' for their enables.
 862  *
 863  * I-CLOCKS:
 864  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
 865  *      CAM, HS-USB.
 866  * F-CLOCK
 867  *      SSI.
 868  *
 869  * GPMC memories and SDRC have timing and clock sensitive registers which
 870  * may very well need notification when the clock changes. Currently for low
 871  * operating points, these are taken care of in sleep.S.
 872  */
 873 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
 874         .name           = "core_l3_ck",
 875         .parent         = &core_ck,
 876         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 877                                 RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
 878                                 DELAYED_APP | CONFIG_PARTICIPANT |
 879                                 RATE_PROPAGATES,
 880         .rate_offset    = OMAP24XX_CLKSEL_L3_SHIFT,
 881         .recalc         = &omap2_clksel_recalc,
 882 };
 883
 884 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
 885         .name           = "usb_l4_ick",
 886         .parent         = &core_l3_ck,
 887         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 888                                 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP |
 889                                 CONFIG_PARTICIPANT,
 890         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 891         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
 892         .rate_offset    = OMAP24XX_CLKSEL_USB_SHIFT,
 893         .recalc         = &omap2_clksel_recalc,
 894 };
 895
 896 /*
 897  * SSI is in L3 management domain, its direct parent is core not l3,
 898  * many core power domain entities are grouped into the L3 clock
 899  * domain.
 900  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
 901  *
 902  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
 903  */
 904 static struct clk ssi_ssr_sst_fck = {
 905         .name           = "ssi_fck",
 906         .parent         = &core_ck,
 907         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 908                                 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
 909         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),       /* bit 1 */
 910         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
 911         .rate_offset    = OMAP24XX_CLKSEL_SSI_SHIFT,
 912         .recalc         = &omap2_clksel_recalc,
 913 };
 914
 915 /*
 916  * GFX clock domain
 917  *      Clocks:
 918  * GFX_FCLK, GFX_ICLK
 919  * GFX_CG1(2d), GFX_CG2(3d)
 920  *
 921  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
 922  * The 2d and 3d clocks run at a hardware determined
 923  * divided value of fclk.
 924  *
 925  */
 926 static struct clk gfx_3d_fck = {
 927         .name           = "gfx_3d_fck",
 928         .parent         = &core_l3_ck,
 929         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 930                                 RATE_CKCTL | CM_GFX_SEL1,
 931         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
 932         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
 933         .rate_offset    = OMAP_CLKSEL_GFX_SHIFT,
 934         .recalc         = &omap2_clksel_recalc,
 935 };
 936
 937 static struct clk gfx_2d_fck = {
 938         .name           = "gfx_2d_fck",
 939         .parent         = &core_l3_ck,
 940         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 941                                 RATE_CKCTL | CM_GFX_SEL1,
 942         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
 943         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
 944         .rate_offset    = OMAP_CLKSEL_GFX_SHIFT,
 945         .recalc         = &omap2_clksel_recalc,
 946 };
 947
 948 static struct clk gfx_ick = {
 949         .name           = "gfx_ick",            /* From l3 */
 950         .parent         = &core_l3_ck,
 951         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 952         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),  /* bit 0 */
 953         .enable_bit     = OMAP_EN_GFX_SHIFT,
 954         .recalc         = &omap2_followparent_recalc,
 955 };
 956
 957 /*
 958  * Modem clock domain (2430)
 959  *      CLOCKS:
 960  *              MDM_OSC_CLK
 961  *              MDM_ICLK
 962  */
 963 static struct clk mdm_ick = {           /* used both as a ick and fck */
 964         .name           = "mdm_ick",
 965         .parent         = &core_ck,
 966         .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_MODEM_SEL1 |
 967                                 DELAYED_APP | CONFIG_PARTICIPANT,
 968         .rate_offset    = OMAP2430_CLKSEL_MDM_SHIFT,
 969         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
 970         .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
 971         .recalc         = &omap2_clksel_recalc,
 972 };
 973
 974 static struct clk mdm_osc_ck = {
 975         .name           = "mdm_osc_ck",
 976         .rate           = 26000000,
 977         .parent         = &osc_ck,
 978         .flags          = CLOCK_IN_OMAP243X | RATE_FIXED,
 979         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, OMAP24XX_CM_FCLKEN),
 980         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
 981         .recalc         = &omap2_followparent_recalc,
 982 };
 983
 984 /*
 985  * L4 clock management domain
 986  *
 987  * This domain contains lots of interface clocks from the L4 interface, some
 988  * functional clocks.   Fixed APLL functional source clocks are managed in
 989  * this domain.
 990  */
 991 static struct clk l4_ck = {             /* used both as an ick and fck */
 992         .name           = "l4_ck",
 993         .parent         = &core_l3_ck,
 994         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 995                                 RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
 996                                 DELAYED_APP | RATE_PROPAGATES,
 997         .rate_offset    = OMAP24XX_CLKSEL_L4_SHIFT,
 998         .recalc         = &omap2_clksel_recalc,
 999 };
1000
1001 static struct clk ssi_l4_ick = {
1002         .name           = "ssi_l4_ick",
1003         .parent         = &l4_ck,
1004         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1005         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),        /* bit 1 */
1006         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1007         .recalc         = &omap2_followparent_recalc,
1008 };
1009
1010 /*
1011  * DSS clock domain
1012  * CLOCKs:
1013  * DSS_L4_ICLK, DSS_L3_ICLK,
1014  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1015  *
1016  * DSS is both initiator and target.
1017  */
1018 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1019         .name           = "dss_ick",
1020         .parent         = &l4_ck,       /* really both l3 and l4 */
1021         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1022         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1023         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1024         .recalc         = &omap2_followparent_recalc,
1025 };
1026
1027 static struct clk dss1_fck = {
1028         .name           = "dss1_fck",
1029         .parent         = &core_ck,             /* Core or sys */
1030         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1031                                 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
1032         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1033         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1034         .rate_offset    = OMAP24XX_CLKSEL_DSS1_SHIFT,
1035         .src_offset     = OMAP24XX_CLKSEL_DSS1_SHIFT,
1036         .recalc         = &omap2_clksel_recalc,
1037 };
1038
1039 static struct clk dss2_fck = {          /* Alt clk used in power management */
1040         .name           = "dss2_fck",
1041         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1042         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1043                                 RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED |
1044                                 DELAYED_APP,
1045         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1046         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
1047         .src_offset     = OMAP24XX_CLKSEL_DSS2_SHIFT,
1048         .recalc         = &omap2_followparent_recalc,
1049 };
1050
1051 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1052         .name           = "dss_54m_fck",        /* 54m tv clk */
1053         .parent         = &func_54m_ck,
1054         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1055         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1056         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
1057         .recalc         = &omap2_followparent_recalc,
1058 };
1059
1060 /*
1061  * CORE power domain ICLK & FCLK defines.
1062  * Many of the these can have more than one possible parent. Entries
1063  * here will likely have an L4 interface parent, and may have multiple
1064  * functional clock parents.
1065  */
1066 static struct clk gpt1_ick = {
1067         .name           = "gpt1_ick",
1068         .parent         = &l4_ck,
1069         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1070         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), /* Bit0 */
1071         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1072         .recalc         = &omap2_followparent_recalc,
1073 };
1074
1075 static struct clk gpt1_fck = {
1076         .name           = "gpt1_fck",
1077         .parent         = &func_32k_ck,
1078         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1079                                 CM_WKUP_SEL1,
1080         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),        /* Bit0 */
1081         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1082         .src_offset     = OMAP24XX_CLKSEL_GPT1_SHIFT,
1083         .recalc         = &omap2_followparent_recalc,
1084 };
1085
1086 static struct clk gpt2_ick = {
1087         .name           = "gpt2_ick",
1088         .parent         = &l4_ck,
1089         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1090         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit4 */
1091         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1092         .recalc         = &omap2_followparent_recalc,
1093 };
1094
1095 static struct clk gpt2_fck = {
1096         .name           = "gpt2_fck",
1097         .parent         = &func_32k_ck,
1098         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1099                                 CM_CORE_SEL2,
1100         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1101         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1102         .src_offset     = OMAP24XX_CLKSEL_GPT2_SHIFT,
1103         .recalc         = &omap2_followparent_recalc,
1104 };
1105
1106 static struct clk gpt3_ick = {
1107         .name           = "gpt3_ick",
1108         .parent         = &l4_ck,
1109         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1110         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit5 */
1111         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1112         .recalc         = &omap2_followparent_recalc,
1113 };
1114
1115 static struct clk gpt3_fck = {
1116         .name           = "gpt3_fck",
1117         .parent         = &func_32k_ck,
1118         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1119                                 CM_CORE_SEL2,
1120         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1121         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1122         .src_offset     = OMAP24XX_CLKSEL_GPT3_SHIFT,
1123         .recalc         = &omap2_followparent_recalc,
1124 };
1125
1126 static struct clk gpt4_ick = {
1127         .name           = "gpt4_ick",
1128         .parent         = &l4_ck,
1129         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1130         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit6 */
1131         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1132         .recalc         = &omap2_followparent_recalc,
1133 };
1134
1135 static struct clk gpt4_fck = {
1136         .name           = "gpt4_fck",
1137         .parent         = &func_32k_ck,
1138         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1139                                 CM_CORE_SEL2,
1140         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1141         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1142         .src_offset     = OMAP24XX_CLKSEL_GPT4_SHIFT,
1143         .recalc         = &omap2_followparent_recalc,
1144 };
1145
1146 static struct clk gpt5_ick = {
1147         .name           = "gpt5_ick",
1148         .parent         = &l4_ck,
1149         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1150         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* Bit7 */
1151         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1152         .recalc         = &omap2_followparent_recalc,
1153 };
1154
1155 static struct clk gpt5_fck = {
1156         .name           = "gpt5_fck",
1157         .parent         = &func_32k_ck,
1158         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1159                                 CM_CORE_SEL2,
1160         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1161         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1162         .src_offset     = OMAP24XX_CLKSEL_GPT5_SHIFT,
1163         .recalc         = &omap2_followparent_recalc,
1164 };
1165
1166 static struct clk gpt6_ick = {
1167         .name           = "gpt6_ick",
1168         .parent         = &l4_ck,
1169         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1170         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1171         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit8 */
1172         .recalc         = &omap2_followparent_recalc,
1173 };
1174
1175 static struct clk gpt6_fck = {
1176         .name           = "gpt6_fck",
1177         .parent         = &func_32k_ck,
1178         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1179                                 CM_CORE_SEL2,
1180         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1181         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1182         .src_offset     = OMAP24XX_CLKSEL_GPT6_SHIFT,
1183         .recalc         = &omap2_followparent_recalc,
1184 };
1185
1186 static struct clk gpt7_ick = {
1187         .name           = "gpt7_ick",
1188         .parent         = &l4_ck,
1189         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1190         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit9 */
1191         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1192         .recalc         = &omap2_followparent_recalc,
1193 };
1194
1195 static struct clk gpt7_fck = {
1196         .name           = "gpt7_fck",
1197         .parent         = &func_32k_ck,
1198         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1199                                 CM_CORE_SEL2,
1200         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1201         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1202         .src_offset     = OMAP24XX_CLKSEL_GPT7_SHIFT,
1203         .recalc         = &omap2_followparent_recalc,
1204 };
1205
1206 static struct clk gpt8_ick = {
1207         .name           = "gpt8_ick",
1208         .parent         = &l4_ck,
1209         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1210         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit10 */
1211         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1212         .recalc         = &omap2_followparent_recalc,
1213 };
1214
1215 static struct clk gpt8_fck = {
1216         .name           = "gpt8_fck",
1217         .parent         = &func_32k_ck,
1218         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1219                                 CM_CORE_SEL2,
1220         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1221         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1222         .src_offset     = OMAP24XX_CLKSEL_GPT8_SHIFT,
1223         .recalc         = &omap2_followparent_recalc,
1224 };
1225
1226 static struct clk gpt9_ick = {
1227         .name           = "gpt9_ick",
1228         .parent         = &l4_ck,
1229         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1230         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1231         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1232         .recalc         = &omap2_followparent_recalc,
1233 };
1234
1235 static struct clk gpt9_fck = {
1236         .name           = "gpt9_fck",
1237         .parent         = &func_32k_ck,
1238         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1239                                         CM_CORE_SEL2,
1240         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1241         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1242         .src_offset     = OMAP24XX_CLKSEL_GPT9_SHIFT,
1243         .recalc         = &omap2_followparent_recalc,
1244 };
1245
1246 static struct clk gpt10_ick = {
1247         .name           = "gpt10_ick",
1248         .parent         = &l4_ck,
1249         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1250         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1251         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1252         .recalc         = &omap2_followparent_recalc,
1253 };
1254
1255 static struct clk gpt10_fck = {
1256         .name           = "gpt10_fck",
1257         .parent         = &func_32k_ck,
1258         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1259                                         CM_CORE_SEL2,
1260         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1261         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1262         .src_offset     = OMAP24XX_CLKSEL_GPT10_SHIFT,
1263         .recalc         = &omap2_followparent_recalc,
1264 };
1265
1266 static struct clk gpt11_ick = {
1267         .name           = "gpt11_ick",
1268         .parent         = &l4_ck,
1269         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1270         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1271         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1272         .recalc         = &omap2_followparent_recalc,
1273 };
1274
1275 static struct clk gpt11_fck = {
1276         .name           = "gpt11_fck",
1277         .parent         = &func_32k_ck,
1278         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1279                                         CM_CORE_SEL2,
1280         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1281         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1282         .src_offset     = OMAP24XX_CLKSEL_GPT11_SHIFT,
1283         .recalc         = &omap2_followparent_recalc,
1284 };
1285
1286 static struct clk gpt12_ick = {
1287         .name           = "gpt12_ick",
1288         .parent         = &l4_ck,
1289         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1290         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit14 */
1291         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1292         .recalc         = &omap2_followparent_recalc,
1293 };
1294
1295 static struct clk gpt12_fck = {
1296         .name           = "gpt12_fck",
1297         .parent         = &func_32k_ck,
1298         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1299                                         CM_CORE_SEL2,
1300         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1301         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1302         .src_offset     = OMAP24XX_CLKSEL_GPT12_SHIFT,
1303         .recalc         = &omap2_followparent_recalc,
1304 };
1305
1306 /* REVISIT: bit comment below wrong? */
1307 static struct clk mcbsp1_ick = {
1308         .name           = "mcbsp1_ick",
1309         .parent         = &l4_ck,
1310         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1311         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit16 */
1312         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1313         .recalc         = &omap2_followparent_recalc,
1314 };
1315
1316 static struct clk mcbsp1_fck = {
1317         .name           = "mcbsp1_fck",
1318         .parent         = &func_96m_ck,
1319         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1320         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1321         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1322         .recalc         = &omap2_followparent_recalc,
1323 };
1324
1325 static struct clk mcbsp2_ick = {
1326         .name           = "mcbsp2_ick",
1327         .parent         = &l4_ck,
1328         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1329         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1330         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1331         .recalc         = &omap2_followparent_recalc,
1332 };
1333
1334 static struct clk mcbsp2_fck = {
1335         .name           = "mcbsp2_fck",
1336         .parent         = &func_96m_ck,
1337         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1338         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1339         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1340         .recalc         = &omap2_followparent_recalc,
1341 };
1342
1343 static struct clk mcbsp3_ick = {
1344         .name           = "mcbsp3_ick",
1345         .parent         = &l4_ck,
1346         .flags          = CLOCK_IN_OMAP243X,
1347         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1348         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1349         .recalc         = &omap2_followparent_recalc,
1350 };
1351
1352 static struct clk mcbsp3_fck = {
1353         .name           = "mcbsp3_fck",
1354         .parent         = &func_96m_ck,
1355         .flags          = CLOCK_IN_OMAP243X,
1356         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1357         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1358         .recalc         = &omap2_followparent_recalc,
1359 };
1360
1361 static struct clk mcbsp4_ick = {
1362         .name           = "mcbsp4_ick",
1363         .parent         = &l4_ck,
1364         .flags          = CLOCK_IN_OMAP243X,
1365         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1366         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1367         .recalc         = &omap2_followparent_recalc,
1368 };
1369
1370 static struct clk mcbsp4_fck = {
1371         .name           = "mcbsp4_fck",
1372         .parent         = &func_96m_ck,
1373         .flags          = CLOCK_IN_OMAP243X,
1374         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1375         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1376         .recalc         = &omap2_followparent_recalc,
1377 };
1378
1379 static struct clk mcbsp5_ick = {
1380         .name           = "mcbsp5_ick",
1381         .parent         = &l4_ck,
1382         .flags          = CLOCK_IN_OMAP243X,
1383         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1384         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1385         .recalc         = &omap2_followparent_recalc,
1386 };
1387
1388 static struct clk mcbsp5_fck = {
1389         .name           = "mcbsp5_fck",
1390         .parent         = &func_96m_ck,
1391         .flags          = CLOCK_IN_OMAP243X,
1392         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1393         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1394         .recalc         = &omap2_followparent_recalc,
1395 };
1396
1397 static struct clk mcspi1_ick = {
1398         .name           = "mcspi_ick",
1399         .id             = 1,
1400         .parent         = &l4_ck,
1401         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1402         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1403         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1404         .recalc         = &omap2_followparent_recalc,
1405 };
1406
1407 static struct clk mcspi1_fck = {
1408         .name           = "mcspi_fck",
1409         .id             = 1,
1410         .parent         = &func_48m_ck,
1411         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1412         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1413         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1414         .recalc         = &omap2_followparent_recalc,
1415 };
1416
1417 static struct clk mcspi2_ick = {
1418         .name           = "mcspi_ick",
1419         .id             = 2,
1420         .parent         = &l4_ck,
1421         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1422         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1423         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1424         .recalc         = &omap2_followparent_recalc,
1425 };
1426
1427 static struct clk mcspi2_fck = {
1428         .name           = "mcspi_fck",
1429         .id             = 2,
1430         .parent         = &func_48m_ck,
1431         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1432         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1433         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1434         .recalc         = &omap2_followparent_recalc,
1435 };
1436
1437 static struct clk mcspi3_ick = {
1438         .name           = "mcspi_ick",
1439         .id             = 3,
1440         .parent         = &l4_ck,
1441         .flags          = CLOCK_IN_OMAP243X,
1442         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1443         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1444         .recalc         = &omap2_followparent_recalc,
1445 };
1446
1447 static struct clk mcspi3_fck = {
1448         .name           = "mcspi_fck",
1449         .id             = 3,
1450         .parent         = &func_48m_ck,
1451         .flags          = CLOCK_IN_OMAP243X,
1452         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1453         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1454         .recalc         = &omap2_followparent_recalc,
1455 };
1456
1457 static struct clk uart1_ick = {
1458         .name           = "uart1_ick",
1459         .parent         = &l4_ck,
1460         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1461         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1462         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1463         .recalc         = &omap2_followparent_recalc,
1464 };
1465
1466 static struct clk uart1_fck = {
1467         .name           = "uart1_fck",
1468         .parent         = &func_48m_ck,
1469         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1470         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1471         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1472         .recalc         = &omap2_followparent_recalc,
1473 };
1474
1475 static struct clk uart2_ick = {
1476         .name           = "uart2_ick",
1477         .parent         = &l4_ck,
1478         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1479         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1480         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1481         .recalc         = &omap2_followparent_recalc,
1482 };
1483
1484 static struct clk uart2_fck = {
1485         .name           = "uart2_fck",
1486         .parent         = &func_48m_ck,
1487         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1488         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1489         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1490         .recalc         = &omap2_followparent_recalc,
1491 };
1492
1493 static struct clk uart3_ick = {
1494         .name           = "uart3_ick",
1495         .parent         = &l4_ck,
1496         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1497         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1498         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1499         .recalc         = &omap2_followparent_recalc,
1500 };
1501
1502 static struct clk uart3_fck = {
1503         .name           = "uart3_fck",
1504         .parent         = &func_48m_ck,
1505         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1506         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1507         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1508         .recalc         = &omap2_followparent_recalc,
1509 };
1510
1511 static struct clk gpios_ick = {
1512         .name           = "gpios_ick",
1513         .parent         = &l4_ck,
1514         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1515         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1516         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1517         .recalc         = &omap2_followparent_recalc,
1518 };
1519
1520 static struct clk gpios_fck = {
1521         .name           = "gpios_fck",
1522         .parent         = &func_32k_ck,
1523         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1524         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
1525         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1526         .recalc         = &omap2_followparent_recalc,
1527 };
1528
1529 static struct clk mpu_wdt_ick = {
1530         .name           = "mpu_wdt_ick",
1531         .parent         = &l4_ck,
1532         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1533         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1534         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
1535         .recalc         = &omap2_followparent_recalc,
1536 };
1537
1538 static struct clk mpu_wdt_fck = {
1539         .name           = "mpu_wdt_fck",
1540         .parent         = &func_32k_ck,
1541         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1542         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
1543         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
1544         .recalc         = &omap2_followparent_recalc,
1545 };
1546
1547 static struct clk sync_32k_ick = {
1548         .name           = "sync_32k_ick",
1549         .parent         = &l4_ck,
1550         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1551         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1552         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
1553         .recalc         = &omap2_followparent_recalc,
1554 };
1555 static struct clk wdt1_ick = {
1556         .name           = "wdt1_ick",
1557         .parent         = &l4_ck,
1558         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1559         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1560         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
1561         .recalc         = &omap2_followparent_recalc,
1562 };
1563 static struct clk omapctrl_ick = {
1564         .name           = "omapctrl_ick",
1565         .parent         = &l4_ck,
1566         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1567         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1568         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
1569         .recalc         = &omap2_followparent_recalc,
1570 };
1571 static struct clk icr_ick = {
1572         .name           = "icr_ick",
1573         .parent         = &l4_ck,
1574         .flags          = CLOCK_IN_OMAP243X,
1575         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1576         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
1577         .recalc         = &omap2_followparent_recalc,
1578 };
1579
1580 static struct clk cam_ick = {
1581         .name           = "cam_ick",
1582         .parent         = &l4_ck,
1583         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1584         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1585         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
1586         .recalc         = &omap2_followparent_recalc,
1587 };
1588
1589 static struct clk cam_fck = {
1590         .name           = "cam_fck",
1591         .parent         = &func_96m_ck,
1592         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1593         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1594         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
1595         .recalc         = &omap2_followparent_recalc,
1596 };
1597
1598 static struct clk mailboxes_ick = {
1599         .name           = "mailboxes_ick",
1600         .parent         = &l4_ck,
1601         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1602         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1603         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
1604         .recalc         = &omap2_followparent_recalc,
1605 };
1606
1607 static struct clk wdt4_ick = {
1608         .name           = "wdt4_ick",
1609         .parent         = &l4_ck,
1610         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1611         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1612         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
1613         .recalc         = &omap2_followparent_recalc,
1614 };
1615
1616 static struct clk wdt4_fck = {
1617         .name           = "wdt4_fck",
1618         .parent         = &func_32k_ck,
1619         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1620         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1621         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
1622         .recalc         = &omap2_followparent_recalc,
1623 };
1624
1625 static struct clk wdt3_ick = {
1626         .name           = "wdt3_ick",
1627         .parent         = &l4_ck,
1628         .flags          = CLOCK_IN_OMAP242X,
1629         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1630         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
1631         .recalc         = &omap2_followparent_recalc,
1632 };
1633
1634 static struct clk wdt3_fck = {
1635         .name           = "wdt3_fck",
1636         .parent         = &func_32k_ck,
1637         .flags          = CLOCK_IN_OMAP242X,
1638         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1639         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
1640         .recalc         = &omap2_followparent_recalc,
1641 };
1642
1643 static struct clk mspro_ick = {
1644         .name           = "mspro_ick",
1645         .parent         = &l4_ck,
1646         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1647         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1648         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
1649         .recalc         = &omap2_followparent_recalc,
1650 };
1651
1652 static struct clk mspro_fck = {
1653         .name           = "mspro_fck",
1654         .parent         = &func_96m_ck,
1655         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1656         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1657         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
1658         .recalc         = &omap2_followparent_recalc,
1659 };
1660
1661 static struct clk mmc_ick = {
1662         .name           = "mmc_ick",
1663         .parent         = &l4_ck,
1664         .flags          = CLOCK_IN_OMAP242X,
1665         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1666         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
1667         .recalc         = &omap2_followparent_recalc,
1668 };
1669
1670 static struct clk mmc_fck = {
1671         .name           = "mmc_fck",
1672         .parent         = &func_96m_ck,
1673         .flags          = CLOCK_IN_OMAP242X,
1674         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1675         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
1676         .recalc         = &omap2_followparent_recalc,
1677 };
1678
1679 static struct clk fac_ick = {
1680         .name           = "fac_ick",
1681         .parent         = &l4_ck,
1682         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1683         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1684         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
1685         .recalc         = &omap2_followparent_recalc,
1686 };
1687
1688 static struct clk fac_fck = {
1689         .name           = "fac_fck",
1690         .parent         = &func_12m_ck,
1691         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1692         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1693         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
1694         .recalc         = &omap2_followparent_recalc,
1695 };
1696
1697 static struct clk eac_ick = {
1698         .name           = "eac_ick",
1699         .parent         = &l4_ck,
1700         .flags          = CLOCK_IN_OMAP242X,
1701         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1702         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
1703         .recalc         = &omap2_followparent_recalc,
1704 };
1705
1706 static struct clk eac_fck = {
1707         .name           = "eac_fck",
1708         .parent         = &func_96m_ck,
1709         .flags          = CLOCK_IN_OMAP242X,
1710         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1711         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
1712         .recalc         = &omap2_followparent_recalc,
1713 };
1714
1715 static struct clk hdq_ick = {
1716         .name           = "hdq_ick",
1717         .parent         = &l4_ck,
1718         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1719         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1720         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
1721         .recalc         = &omap2_followparent_recalc,
1722 };
1723
1724 static struct clk hdq_fck = {
1725         .name           = "hdq_fck",
1726         .parent         = &func_12m_ck,
1727         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1728         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1729         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
1730         .recalc         = &omap2_followparent_recalc,
1731 };
1732
1733 static struct clk i2c2_ick = {
1734         .name           = "i2c_ick",
1735         .id             = 2,
1736         .parent         = &l4_ck,
1737         .flags          = CLOCK_IN_OMAP242X,
1738         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1739         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
1740         .recalc         = &omap2_followparent_recalc,
1741 };
1742
1743 static struct clk i2c2_fck = {
1744         .name           = "i2c_fck",
1745         .id             = 2,
1746         .parent         = &func_12m_ck,
1747         .flags          = CLOCK_IN_OMAP242X,
1748         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1749         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
1750         .recalc         = &omap2_followparent_recalc,
1751 };
1752
1753 static struct clk i2chs2_fck = {
1754         .name           = "i2chs_fck",
1755         .id             = 2,
1756         .parent         = &func_96m_ck,
1757         .flags          = CLOCK_IN_OMAP243X,
1758         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1759         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
1760         .recalc         = &omap2_followparent_recalc,
1761 };
1762
1763 static struct clk i2c1_ick = {
1764         .name           = "i2c_ick",
1765         .id             = 1,
1766         .parent         = &l4_ck,
1767         .flags          = CLOCK_IN_OMAP242X,
1768         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1769         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
1770         .recalc         = &omap2_followparent_recalc,
1771 };
1772
1773 static struct clk i2c1_fck = {
1774         .name           = "i2c_fck",
1775         .id             = 1,
1776         .parent         = &func_12m_ck,
1777         .flags          = CLOCK_IN_OMAP242X,
1778         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1779         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
1780         .recalc         = &omap2_followparent_recalc,
1781 };
1782
1783 static struct clk i2chs1_fck = {
1784         .name           = "i2chs_fck",
1785         .id             = 1,
1786         .parent         = &func_96m_ck,
1787         .flags          = CLOCK_IN_OMAP243X,
1788         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1789         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
1790         .recalc         = &omap2_followparent_recalc,
1791 };
1792
1793 static struct clk vlynq_ick = {
1794         .name           = "vlynq_ick",
1795         .parent         = &core_l3_ck,
1796         .flags          = CLOCK_IN_OMAP242X,
1797         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1798         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
1799         .recalc         = &omap2_followparent_recalc,
1800 };
1801
1802 static struct clk vlynq_fck = {
1803         .name           = "vlynq_fck",
1804         .parent         = &func_96m_ck,
1805         .flags          = CLOCK_IN_OMAP242X  | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
1806         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1807         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
1808         .src_offset     = OMAP2420_CLKSEL_VLYNQ_SHIFT,
1809         .recalc         = &omap2_clksel_recalc,
1810 };
1811
1812 static struct clk sdrc_ick = {
1813         .name           = "sdrc_ick",
1814         .parent         = &l4_ck,
1815         .flags          = CLOCK_IN_OMAP243X,
1816         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP2430_CM_ICLKEN3),
1817         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
1818         .recalc         = &omap2_followparent_recalc,
1819 };
1820
1821 static struct clk des_ick = {
1822         .name           = "des_ick",
1823         .parent         = &l4_ck,
1824         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1825         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1826         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
1827         .recalc         = &omap2_followparent_recalc,
1828 };
1829
1830 static struct clk sha_ick = {
1831         .name           = "sha_ick",
1832         .parent         = &l4_ck,
1833         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1834         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1835         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
1836         .recalc         = &omap2_followparent_recalc,
1837 };
1838
1839 static struct clk rng_ick = {
1840         .name           = "rng_ick",
1841         .parent         = &l4_ck,
1842         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1843         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1844         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
1845         .recalc         = &omap2_followparent_recalc,
1846 };
1847
1848 static struct clk aes_ick = {
1849         .name           = "aes_ick",
1850         .parent         = &l4_ck,
1851         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1852         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1853         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
1854         .recalc         = &omap2_followparent_recalc,
1855 };
1856
1857 static struct clk pka_ick = {
1858         .name           = "pka_ick",
1859         .parent         = &l4_ck,
1860         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1861         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1862         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
1863         .recalc         = &omap2_followparent_recalc,
1864 };
1865
1866 static struct clk usb_fck = {
1867         .name           = "usb_fck",
1868         .parent         = &func_48m_ck,
1869         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1870         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1871         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1872         .recalc         = &omap2_followparent_recalc,
1873 };
1874
1875 static struct clk usbhs_ick = {
1876         .name           = "usbhs_ick",
1877         .parent         = &core_l3_ck,
1878         .flags          = CLOCK_IN_OMAP243X,
1879         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1880         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
1881         .recalc         = &omap2_followparent_recalc,
1882 };
1883
1884 static struct clk mmchs1_ick = {
1885         .name           = "mmchs1_ick",
1886         .parent         = &l4_ck,
1887         .flags          = CLOCK_IN_OMAP243X,
1888         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1889         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
1890         .recalc         = &omap2_followparent_recalc,
1891 };
1892
1893 static struct clk mmchs1_fck = {
1894         .name           = "mmchs1_fck",
1895         .parent         = &func_96m_ck,
1896         .flags          = CLOCK_IN_OMAP243X,
1897         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1898         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
1899         .recalc         = &omap2_followparent_recalc,
1900 };
1901
1902 static struct clk mmchs2_ick = {
1903         .name           = "mmchs2_ick",
1904         .parent         = &l4_ck,
1905         .flags          = CLOCK_IN_OMAP243X,
1906         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1907         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
1908         .recalc         = &omap2_followparent_recalc,
1909 };
1910
1911 static struct clk mmchs2_fck = {
1912         .name           = "mmchs2_fck",
1913         .parent         = &func_96m_ck,
1914         .flags          = CLOCK_IN_OMAP243X,
1915         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1916         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
1917         .recalc         = &omap2_followparent_recalc,
1918 };
1919
1920 static struct clk gpio5_ick = {
1921         .name           = "gpio5_ick",
1922         .parent         = &l4_ck,
1923         .flags          = CLOCK_IN_OMAP243X,
1924         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1925         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
1926         .recalc         = &omap2_followparent_recalc,
1927 };
1928
1929 static struct clk gpio5_fck = {
1930         .name           = "gpio5_fck",
1931         .parent         = &func_32k_ck,
1932         .flags          = CLOCK_IN_OMAP243X,
1933         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1934         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
1935         .recalc         = &omap2_followparent_recalc,
1936 };
1937
1938 static struct clk mdm_intc_ick = {
1939         .name           = "mdm_intc_ick",
1940         .parent         = &l4_ck,
1941         .flags          = CLOCK_IN_OMAP243X,
1942         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1943         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
1944         .recalc         = &omap2_followparent_recalc,
1945 };
1946
1947 static struct clk mmchsdb1_fck = {
1948         .name           = "mmchsdb1_fck",
1949         .parent         = &func_32k_ck,
1950         .flags          = CLOCK_IN_OMAP243X,
1951         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1952         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
1953         .recalc         = &omap2_followparent_recalc,
1954 };
1955
1956 static struct clk mmchsdb2_fck = {
1957         .name           = "mmchsdb2_fck",
1958         .parent         = &func_32k_ck,
1959         .flags          = CLOCK_IN_OMAP243X,
1960         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1961         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
1962         .recalc         = &omap2_followparent_recalc,
1963 };
1964
1965 /*
1966  * This clock is a composite clock which does entire set changes then
1967  * forces a rebalance. It keys on the MPU speed, but it really could
1968  * be any key speed part of a set in the rate table.
1969  *
1970  * to really change a set, you need memory table sets which get changed
1971  * in sram, pre-notifiers & post notifiers, changing the top set, without
1972  * having low level display recalc's won't work... this is why dpm notifiers
1973  * work, isr's off, walk a list of clocks already _off_ and not messing with
1974  * the bus.
1975  *
1976  * This clock should have no parent. It embodies the entire upper level
1977  * active set. A parent will mess up some of the init also.
1978  */
1979 static struct clk virt_prcm_set = {
1980         .name           = "virt_prcm_set",
1981         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1982                                 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
1983         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
1984         .recalc         = &omap2_mpu_recalc,    /* sets are keyed on mpu rate */
1985         .set_rate       = &omap2_select_table_rate,
1986         .round_rate     = &omap2_round_to_table_rate,
1987 };
1988
1989 static struct clk *onchip_clks[] = {
1990         /* external root sources */
1991         &func_32k_ck,
1992         &osc_ck,
1993         &sys_ck,
1994         &alt_ck,
1995         /* internal analog sources */
1996         &dpll_ck,
1997         &apll96_ck,
1998         &apll54_ck,
1999         /* internal prcm root sources */
2000         &func_54m_ck,
2001         &core_ck,
2002         &func_96m_ck,
2003         &func_48m_ck,
2004         &func_12m_ck,
2005         &wdt1_osc_ck,
2006         &sys_clkout,
2007         &sys_clkout2,
2008         &emul_ck,
2009         /* mpu domain clocks */
2010         &mpu_ck,
2011         /* dsp domain clocks */
2012         &iva2_1_fck,            /* 2430 */
2013         &iva2_1_ick,
2014         &dsp_ick,               /* 2420 */
2015         &dsp_fck,
2016         &iva1_ifck,
2017         &iva1_mpu_int_ifck,
2018         /* GFX domain clocks */
2019         &gfx_3d_fck,
2020         &gfx_2d_fck,
2021         &gfx_ick,
2022         /* Modem domain clocks */
2023         &mdm_ick,
2024         &mdm_osc_ck,
2025         /* DSS domain clocks */
2026         &dss_ick,
2027         &dss1_fck,
2028         &dss2_fck,
2029         &dss_54m_fck,
2030         /* L3 domain clocks */
2031         &core_l3_ck,
2032         &ssi_ssr_sst_fck,
2033         &usb_l4_ick,
2034         /* L4 domain clocks */
2035         &l4_ck,                 /* used as both core_l4 and wu_l4 */
2036         &ssi_l4_ick,
2037         /* virtual meta-group clock */
2038         &virt_prcm_set,
2039         /* general l4 interface ck, multi-parent functional clk */
2040         &gpt1_ick,
2041         &gpt1_fck,
2042         &gpt2_ick,
2043         &gpt2_fck,
2044         &gpt3_ick,
2045         &gpt3_fck,
2046         &gpt4_ick,
2047         &gpt4_fck,
2048         &gpt5_ick,
2049         &gpt5_fck,
2050         &gpt6_ick,
2051         &gpt6_fck,
2052         &gpt7_ick,
2053         &gpt7_fck,
2054         &gpt8_ick,
2055         &gpt8_fck,
2056         &gpt9_ick,
2057         &gpt9_fck,
2058         &gpt10_ick,
2059         &gpt10_fck,
2060         &gpt11_ick,
2061         &gpt11_fck,
2062         &gpt12_ick,
2063         &gpt12_fck,
2064         &mcbsp1_ick,
2065         &mcbsp1_fck,
2066         &mcbsp2_ick,
2067         &mcbsp2_fck,
2068         &mcbsp3_ick,
2069         &mcbsp3_fck,
2070         &mcbsp4_ick,
2071         &mcbsp4_fck,
2072         &mcbsp5_ick,
2073         &mcbsp5_fck,
2074         &mcspi1_ick,
2075         &mcspi1_fck,
2076         &mcspi2_ick,
2077         &mcspi2_fck,
2078         &mcspi3_ick,
2079         &mcspi3_fck,
2080         &uart1_ick,
2081         &uart1_fck,
2082         &uart2_ick,
2083         &uart2_fck,
2084         &uart3_ick,
2085         &uart3_fck,
2086         &gpios_ick,
2087         &gpios_fck,
2088         &mpu_wdt_ick,
2089         &mpu_wdt_fck,
2090         &sync_32k_ick,
2091         &wdt1_ick,
2092         &omapctrl_ick,
2093         &icr_ick,
2094         &cam_fck,
2095         &cam_ick,
2096         &mailboxes_ick,
2097         &wdt4_ick,
2098         &wdt4_fck,
2099         &wdt3_ick,
2100         &wdt3_fck,
2101         &mspro_ick,
2102         &mspro_fck,
2103         &mmc_ick,
2104         &mmc_fck,
2105         &fac_ick,
2106         &fac_fck,
2107         &eac_ick,
2108         &eac_fck,
2109         &hdq_ick,
2110         &hdq_fck,
2111         &i2c1_ick,
2112         &i2c1_fck,
2113         &i2chs1_fck,
2114         &i2c2_ick,
2115         &i2c2_fck,
2116         &i2chs2_fck,
2117         &vlynq_ick,
2118         &vlynq_fck,
2119         &sdrc_ick,
2120         &des_ick,
2121         &sha_ick,
2122         &rng_ick,
2123         &aes_ick,
2124         &pka_ick,
2125         &usb_fck,
2126         &usbhs_ick,
2127         &mmchs1_ick,
2128         &mmchs1_fck,
2129         &mmchs2_ick,
2130         &mmchs2_fck,
2131         &gpio5_ick,
2132         &gpio5_fck,
2133         &mdm_intc_ick,
2134         &mmchsdb1_fck,
2135         &mmchsdb2_fck,
2136 };
2137
2138 #endif