arch/arm/mach-omap2/clock.h

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock.h
   3  *
   4  *  Copyright (C) 2005 Texas Instruments Inc.
   5  *  Richard Woodruff <r-woodruff2@ti.com>
   6  *  Created for OMAP2.
   7  *
   8  *  Copyright (C) 2004 Nokia corporation
   9  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  10  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
  11  *
  12  *  Copyright (C) 2007 Texas Instruments, Inc.
  13  *  Copyright (C) 2007 Nokia Corporation
  14  *  Paul Walmsley
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
  22 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
  23
  24 #include "prm.h"
  25 #include "cm.h"
  26 #include "prm_regbits_24xx.h"
  27 #include "cm_regbits_24xx.h"
  28
  29 static void omap2_clksel_recalc(struct clk * clk);
  30 static void omap2_table_mpu_recalc(struct clk *clk);
  31 static int omap2_select_table_rate(struct clk * clk, unsigned long rate);
  32 static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate);
  33 static void omap2_clk_disable(struct clk *clk);
  34 static void omap2_sys_clk_recalc(struct clk * clk);
  35 static void omap2_init_clksel_parent(struct clk *clk);
  36 static u32 omap2_clksel_get_divisor(struct clk *clk);
  37 static u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val);
  38 static u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
  39 static void omap2_dpll_recalc(struct clk *clk);
  40 static void omap2_fixed_divisor_recalc(struct clk *clk);
  41 static int omap2_clk_fixed_enable(struct clk *clk);
  42 static void omap2_clk_fixed_disable(struct clk *clk);
  43 static long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
  44 static int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
  45 static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate);
  46 static int omap2_enable_osc_ck(struct clk *clk);
  47 static void omap2_disable_osc_ck(struct clk *clk);
  48
  49 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  50  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  51  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  52  */
  53 struct prcm_config {
  54         unsigned long xtal_speed;       /* crystal rate */
  55         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  56         unsigned long mpu_speed;        /* speed of MPU */
  57         unsigned long cm_clksel_mpu;    /* mpu divider */
  58         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  59         unsigned long cm_clksel_gfx;    /* gfx dividers */
  60         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  61         unsigned long cm_clksel1_pll;   /* m,n */
  62         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  63         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  64         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  65         unsigned char flags;
  66 };
  67
  68 /*
  69  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  70  * These configurations are characterized by voltage and speed for clocks.
  71  * The device is only validated for certain combinations. One way to express
  72  * these combinations is via the 'ratio's' which the clocks operate with
  73  * respect to each other. These ratio sets are for a given voltage/DPLL
  74  * setting. All configurations can be described by a DPLL setting and a ratio
  75  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  76  *
  77  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  78  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  79  * 2430 (iva2.1, NOdsp, mdm)
  80  */
  81
  82 /* Core fields for cm_clksel, not ratio governed */
  83 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  84 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  85 #define RX_CLKSEL_SSI                   (0x5 << 20)
  86
  87 /*-------------------------------------------------------------------------
  88  * Voltage/DPLL ratios
  89  *-------------------------------------------------------------------------*/
  90
  91 /* 2430 Ratio's, 2430-Ratio Config 1 */
  92 #define R1_CLKSEL_L3                    (4 << 0)
  93 #define R1_CLKSEL_L4                    (2 << 5)
  94 #define R1_CLKSEL_USB                   (4 << 25)
  95 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
  96                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  97                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
  98 #define R1_CLKSEL_MPU                   (2 << 0)
  99 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
 100 #define R1_CLKSEL_DSP                   (2 << 0)
 101 #define R1_CLKSEL_DSP_IF                (2 << 5)
 102 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
 103 #define R1_CLKSEL_GFX                   (2 << 0)
 104 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
 105 #define R1_CLKSEL_MDM                   (4 << 0)
 106 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
 107
 108 /* 2430-Ratio Config 2 */
 109 #define R2_CLKSEL_L3                    (6 << 0)
 110 #define R2_CLKSEL_L4                    (2 << 5)
 111 #define R2_CLKSEL_USB                   (2 << 25)
 112 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
 113                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 114                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
 115 #define R2_CLKSEL_MPU                   (2 << 0)
 116 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 117 #define R2_CLKSEL_DSP                   (2 << 0)
 118 #define R2_CLKSEL_DSP_IF                (3 << 5)
 119 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 120 #define R2_CLKSEL_GFX                   (2 << 0)
 121 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 122 #define R2_CLKSEL_MDM                   (6 << 0)
 123 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 124
 125 /* 2430-Ratio Bootm (BYPASS) */
 126 #define RB_CLKSEL_L3                    (1 << 0)
 127 #define RB_CLKSEL_L4                    (1 << 5)
 128 #define RB_CLKSEL_USB                   (1 << 25)
 129 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 130                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 131                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 132 #define RB_CLKSEL_MPU                   (1 << 0)
 133 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 134 #define RB_CLKSEL_DSP                   (1 << 0)
 135 #define RB_CLKSEL_DSP_IF                (1 << 5)
 136 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 137 #define RB_CLKSEL_GFX                   (1 << 0)
 138 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 139 #define RB_CLKSEL_MDM                   (1 << 0)
 140 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 141
 142 /* 2420 Ratio Equivalents */
 143 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 144 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 145
 146 /* 2420-PRCM III 532MHz core */
 147 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 148 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 149 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 150 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 151                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 152                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 153                                         RIII_CLKSEL_L3
 154 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 155 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 156 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 157 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 158 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 159 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 160 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 161 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 162                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 163                                         RIII_CLKSEL_DSP
 164 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 165 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 166
 167 /* 2420-PRCM II 600MHz core */
 168 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 169 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 170 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 171 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 172                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 173                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 174                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 175 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 176 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 177 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 178 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 179 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 180 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 181 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 182 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 183                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 184                                         RII_CLKSEL_DSP
 185 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 186 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 187
 188 /* 2420-PRCM I 660MHz core */
 189 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 190 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 191 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 192 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 193                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 194                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 195                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 196 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 197 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 198 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 199 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 200 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 201 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 202 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 203 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 204                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 205                                         RI_CLKSEL_DSP
 206 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 207 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 208
 209 /* 2420-PRCM VII (boot) */
 210 #define RVII_CLKSEL_L3                  (1 << 0)
 211 #define RVII_CLKSEL_L4                  (1 << 5)
 212 #define RVII_CLKSEL_DSS1                (1 << 8)
 213 #define RVII_CLKSEL_DSS2                (0 << 13)
 214 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 215 #define RVII_CLKSEL_SSI                 (1 << 20)
 216 #define RVII_CLKSEL_USB                 (1 << 25)
 217
 218 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 219                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 220                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 221
 222 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 223 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 224
 225 #define RVII_CLKSEL_DSP                 (1 << 0)
 226 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 227 #define RVII_SYNC_DSP                   (0 << 7)
 228 #define RVII_CLKSEL_IVA                 (1 << 8)
 229 #define RVII_SYNC_IVA                   (0 << 13)
 230 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 231                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 232
 233 #define RVII_CLKSEL_GFX                 (1 << 0)
 234 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 235
 236 /*-------------------------------------------------------------------------
 237  * 2430 Target modes: Along with each configuration the CPU has several
 238  * modes which goes along with them. Modes mainly are the addition of
 239  * describe DPLL combinations to go along with a ratio.
 240  *-------------------------------------------------------------------------*/
 241
 242 /* Hardware governed */
 243 #define MX_48M_SRC                      (0 << 3)
 244 #define MX_54M_SRC                      (0 << 5)
 245 #define MX_APLLS_CLIKIN_12              (3 << 23)
 246 #define MX_APLLS_CLIKIN_13              (2 << 23)
 247 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 248
 249 /*
 250  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 251  * #2   (ratio1) baseport-target
 252  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 253  */
 254 #define M5A_DPLL_MULT_12                (133 << 12)
 255 #define M5A_DPLL_DIV_12                 (5 << 8)
 256 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 257                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 258                                         MX_APLLS_CLIKIN_12
 259 #define M5A_DPLL_MULT_13                (266 << 12)
 260 #define M5A_DPLL_DIV_13                 (12 << 8)
 261 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 262                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 263                                         MX_APLLS_CLIKIN_13
 264 #define M5A_DPLL_MULT_19                (180 << 12)
 265 #define M5A_DPLL_DIV_19                 (12 << 8)
 266 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 267                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 268                                         MX_APLLS_CLIKIN_19_2
 269 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 270 #define M5B_DPLL_MULT_12                (50 << 12)
 271 #define M5B_DPLL_DIV_12                 (2 << 8)
 272 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 273                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 274                                         MX_APLLS_CLIKIN_12
 275 #define M5B_DPLL_MULT_13                (200 << 12)
 276 #define M5B_DPLL_DIV_13                 (12 << 8)
 277
 278 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 279                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 280                                         MX_APLLS_CLIKIN_13
 281 #define M5B_DPLL_MULT_19                (125 << 12)
 282 #define M5B_DPLL_DIV_19                 (31 << 8)
 283 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 284                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 285                                         MX_APLLS_CLIKIN_19_2
 286 /*
 287  * #4   (ratio2)
 288  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 289  */
 290 #define M3_DPLL_MULT_12                 (55 << 12)
 291 #define M3_DPLL_DIV_12                  (1 << 8)
 292 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 293                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 294                                         MX_APLLS_CLIKIN_12
 295 #define M3_DPLL_MULT_13                 (330 << 12)
 296 #define M3_DPLL_DIV_13                  (12 << 8)
 297 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 298                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 299                                         MX_APLLS_CLIKIN_13
 300 #define M3_DPLL_MULT_19                 (275 << 12)
 301 #define M3_DPLL_DIV_19                  (15 << 8)
 302 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 303                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 304                                         MX_APLLS_CLIKIN_19_2
 305 /* boot (boot) */
 306 #define MB_DPLL_MULT                    (1 << 12)
 307 #define MB_DPLL_DIV                     (0 << 8)
 308 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 309                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 310
 311 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 312                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 313
 314 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 315                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 316
 317 /*
 318  * 2430 - chassis (sedna)
 319  * 165 (ratio1) same as above #2
 320  * 150 (ratio1)
 321  * 133 (ratio2) same as above #4
 322  * 110 (ratio2) same as above #3
 323  * 104 (ratio2)
 324  * boot (boot)
 325  */
 326
 327 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 328 #define MI_DPLL_MULT_12                 (55 << 12)
 329 #define MI_DPLL_DIV_12                  (1 << 8)
 330 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 331                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 332                                         MX_APLLS_CLIKIN_12
 333
 334 /*
 335  * 2420 Equivalent - mode registers
 336  * PRCM II , target DPLL = 2*300MHz = 600MHz
 337  */
 338 #define MII_DPLL_MULT_12                (50 << 12)
 339 #define MII_DPLL_DIV_12                 (1 << 8)
 340 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 341                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 342                                         MX_APLLS_CLIKIN_12
 343 #define MII_DPLL_MULT_13                (300 << 12)
 344 #define MII_DPLL_DIV_13                 (12 << 8)
 345 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 346                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 347                                         MX_APLLS_CLIKIN_13
 348
 349 /* PRCM III target DPLL = 2*266 = 532MHz*/
 350 #define MIII_DPLL_MULT_12               (133 << 12)
 351 #define MIII_DPLL_DIV_12                (5 << 8)
 352 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 353                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 354                                         MX_APLLS_CLIKIN_12
 355 #define MIII_DPLL_MULT_13               (266 << 12)
 356 #define MIII_DPLL_DIV_13                (12 << 8)
 357 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 358                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 359                                         MX_APLLS_CLIKIN_13
 360
 361 /* PRCM VII (boot bypass) */
 362 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 363 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 364
 365 /* High and low operation value */
 366 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 367 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 368
 369 /*
 370  * These represent optimal values for common parts, it won't work for all.
 371  * As long as you scale down, most parameters are still work, they just
 372  * become sub-optimal. The RFR value goes in the opposite direction. If you
 373  * don't adjust it down as your clock period increases the refresh interval
 374  * will not be met. Setting all parameters for complete worst case may work,
 375  * but may cut memory performance by 2x. Due to errata the DLLs need to be
 376  * unlocked and their value needs run time calibration. A dynamic call is
 377  * need for that as no single right value exists acorss production samples.
 378  *
 379  * Only the FULL speed values are given. Current code is such that rate
 380  * changes must be made at DPLLoutx2. The actual value adjustment for low
 381  * frequency operation will be handled by omap_set_performance()
 382  *
 383  * By having the boot loader boot up in the fastest L4 speed available likely
 384  * will result in something which you can switch between.
 385  */
 386 #define V24XX_SDRC_RFR_CTRL_165MHz      (0x00044c00 | 1)
 387 #define V24XX_SDRC_RFR_CTRL_133MHz      (0x0003de00 | 1)
 388 #define V24XX_SDRC_RFR_CTRL_100MHz      (0x0002da01 | 1)
 389 #define V24XX_SDRC_RFR_CTRL_110MHz      (0x0002da01 | 1) /* Need to calc */
 390 #define V24XX_SDRC_RFR_CTRL_BYPASS      (0x00005000 | 1) /* Need to calc */
 391
 392 /* MPU speed defines */
 393 #define S12M    12000000
 394 #define S13M    13000000
 395 #define S19M    19200000
 396 #define S26M    26000000
 397 #define S100M   100000000
 398 #define S133M   133000000
 399 #define S150M   150000000
 400 #define S165M   165000000
 401 #define S200M   200000000
 402 #define S266M   266000000
 403 #define S300M   300000000
 404 #define S330M   330000000
 405 #define S400M   400000000
 406 #define S532M   532000000
 407 #define S600M   600000000
 408 #define S660M   660000000
 409
 410 /*-------------------------------------------------------------------------
 411  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 412  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 413  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 414  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 415  *
 416  * Filling in table based on H4 boards and 2430-SDPs variants available.
 417  * There are quite a few more rates combinations which could be defined.
 418  *
 419  * When multiple values are defined the start up will try and choose the
 420  * fastest one. If a 'fast' value is defined, then automatically, the /2
 421  * one should be included as it can be used.    Generally having more that
 422  * one fast set does not make sense, as static timings need to be changed
 423  * to change the set.    The exception is the bypass setting which is
 424  * availble for low power bypass.
 425  *
 426  * Note: This table needs to be sorted, fastest to slowest.
 427  *-------------------------------------------------------------------------*/
 428 static struct prcm_config rate_table[] = {
 429         /* PRCM I - FAST */
 430         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 431                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 432                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 433                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_165MHz,
 434                 RATE_IN_242X},
 435
 436         /* PRCM II - FAST */
 437         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 438                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 439                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 440                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 441                 RATE_IN_242X},
 442
 443         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 444                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 445                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 446                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 447                 RATE_IN_242X},
 448
 449         /* PRCM III - FAST */
 450         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 451                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 452                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 453                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 454                 RATE_IN_242X},
 455
 456         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 457                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 458                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 459                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 460                 RATE_IN_242X},
 461
 462         /* PRCM II - SLOW */
 463         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 464                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 465                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 466                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 467                 RATE_IN_242X},
 468
 469         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 470                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 471                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 472                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 473                 RATE_IN_242X},
 474
 475         /* PRCM III - SLOW */
 476         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 477                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 478                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 479                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 480                 RATE_IN_242X},
 481
 482         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 483                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 484                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 485                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 486                 RATE_IN_242X},
 487
 488         /* PRCM-VII (boot-bypass) */
 489         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 490                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 491                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 492                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
 493                 RATE_IN_242X},
 494
 495         /* PRCM-VII (boot-bypass) */
 496         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 497                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 498                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 499                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
 500                 RATE_IN_242X},
 501
 502         /* PRCM #3 - ratio2 (ES2) - FAST */
 503         {S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 504                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 505                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 506                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 507                 V24XX_SDRC_RFR_CTRL_110MHz,
 508                 RATE_IN_243X},
 509
 510         /* PRCM #5a - ratio1 - FAST */
 511         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 512                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 513                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 514                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 515                 V24XX_SDRC_RFR_CTRL_133MHz,
 516                 RATE_IN_243X},
 517
 518         /* PRCM #5b - ratio1 - FAST */
 519         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 520                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 521                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 522                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 523                 V24XX_SDRC_RFR_CTRL_100MHz,
 524                 RATE_IN_243X},
 525
 526         /* PRCM #3 - ratio2 (ES2) - SLOW */
 527         {S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 528                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 529                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 530                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 531                 V24XX_SDRC_RFR_CTRL_110MHz,
 532                 RATE_IN_243X},
 533
 534         /* PRCM #5a - ratio1 - SLOW */
 535         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 536                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 537                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 538                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 539                 V24XX_SDRC_RFR_CTRL_133MHz,
 540                 RATE_IN_243X},
 541
 542         /* PRCM #5b - ratio1 - SLOW*/
 543         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 544                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 545                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 546                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 547                 V24XX_SDRC_RFR_CTRL_100MHz,
 548                 RATE_IN_243X},
 549
 550         /* PRCM-boot/bypass */
 551         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 552                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 553                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 554                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 555                 V24XX_SDRC_RFR_CTRL_BYPASS,
 556                 RATE_IN_243X},
 557
 558         /* PRCM-boot/bypass */
 559         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 560                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 561                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 562                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 563                 V24XX_SDRC_RFR_CTRL_BYPASS,
 564                 RATE_IN_243X},
 565
 566         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 567 };
 568
 569 /*-------------------------------------------------------------------------
 570  * 24xx clock tree.
 571  *
 572  * NOTE:In many cases here we are assigning a 'default' parent. In many
 573  *      cases the parent is selectable. The get/set parent calls will also
 574  *      switch sources.
 575  *
 576  *      Many some clocks say always_enabled, but they can be auto idled for
 577  *      power savings. They will always be available upon clock request.
 578  *
 579  *      Several sources are given initial rates which may be wrong, this will
 580  *      be fixed up in the init func.
 581  *
 582  *      Things are broadly separated below by clock domains. It is
 583  *      noteworthy that most periferals have dependencies on multiple clock
 584  *      domains. Many get their interface clocks from the L4 domain, but get
 585  *      functional clocks from fixed sources or other core domain derived
 586  *      clocks.
 587  *-------------------------------------------------------------------------*/
 588
 589 /* Base external input clocks */
 590 static struct clk func_32k_ck = {
 591         .name           = "func_32k_ck",
 592         .rate           = 32000,
 593         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 594                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 595         .recalc         = &propagate_rate,
 596 };
 597
 598 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 599 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 600         .name           = "osc_ck",
 601         .rate           = 26000000,             /* fixed up in clock init */
 602         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 603                                 RATE_FIXED | RATE_PROPAGATES,
 604         .enable         = &omap2_enable_osc_ck,
 605         .disable        = &omap2_disable_osc_ck,
 606         .recalc         = &propagate_rate,
 607 };
 608
 609 /* With out modem likely 12MHz, with modem likely 13MHz */
 610 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 611         .name           = "sys_ck",             /* ~ ref_clk also */
 612         .parent         = &osc_ck,
 613         .rate           = 13000000,
 614         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 615                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 616         .recalc         = &omap2_sys_clk_recalc,
 617 };
 618
 619 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 620         .name           = "alt_ck",
 621         .rate           = 54000000,
 622         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 623                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 624         .recalc         = &propagate_rate,
 625 };
 626
 627 /*
 628  * Analog domain root source clocks
 629  */
 630
 631 /* dpll_ck, is broken out in to special cases through clksel */
 632 /* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
 633  * deal with this
 634  */
 635 static struct clk dpll_ck = {
 636         .name           = "dpll_ck",
 637         .parent         = &sys_ck,              /* Can be func_32k also */
 638         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 639                                 RATE_PROPAGATES | ALWAYS_ENABLED,
 640         .recalc         = &omap2_dpll_recalc,
 641         .set_rate       = &omap2_reprogram_dpll,
 642 };
 643
 644 static struct clk apll96_ck = {
 645         .name           = "apll96_ck",
 646         .parent         = &sys_ck,
 647         .rate           = 96000000,
 648         .flags          = CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X |
 649                                 RATE_FIXED | RATE_PROPAGATES,
 650         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 651         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 652         .enable         = &omap2_clk_fixed_enable,
 653         .disable        = &omap2_clk_fixed_disable,
 654         .recalc         = &propagate_rate,
 655 };
 656
 657 static struct clk apll54_ck = {
 658         .name           = "apll54_ck",
 659         .parent         = &sys_ck,
 660         .rate           = 54000000,
 661         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 662                                 RATE_FIXED | RATE_PROPAGATES,
 663         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 664         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 665         .enable         = &omap2_clk_fixed_enable,
 666         .disable        = &omap2_clk_fixed_disable,
 667         .recalc         = &propagate_rate,
 668 };
 669
 670 /*
 671  * PRCM digital base sources
 672  */
 673
 674 /* func_54m_ck */
 675
 676 static const struct clksel_rate func_54m_apll54_rates[] = {
 677         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 678         { .div = 0 },
 679 };
 680
 681 static const struct clksel_rate func_54m_alt_rates[] = {
 682         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 683         { .div = 0 },
 684 };
 685
 686 static const struct clksel func_54m_clksel[] = {
 687         { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
 688         { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
 689         { .parent = NULL },
 690 };
 691
 692 static struct clk func_54m_ck = {
 693         .name           = "func_54m_ck",
 694         .parent         = &apll54_ck,   /* can also be alt_clk */
 695         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 696                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 697         .init           = &omap2_init_clksel_parent,
 698         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 699         .clksel_mask    = OMAP24XX_54M_SOURCE,
 700         .clksel         = func_54m_clksel,
 701         .recalc         = &omap2_clksel_recalc,
 702 };
 703
 704 static struct clk core_ck = {
 705         .name           = "core_ck",
 706         .parent         = &dpll_ck,             /* can also be 32k */
 707         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 708                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 709         .recalc         = &followparent_recalc,
 710 };
 711
 712 /* func_96m_ck */
 713 static const struct clksel_rate func_96m_apll96_rates[] = {
 714         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 715         { .div = 0 },
 716 };
 717
 718 static const struct clksel_rate func_96m_alt_rates[] = {
 719         { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
 720         { .div = 0 },
 721 };
 722
 723 static const struct clksel func_96m_clksel[] = {
 724         { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
 725         { .parent = &alt_ck,    .rates = func_96m_alt_rates },
 726         { .parent = NULL }
 727 };
 728
 729 /* The parent of this clock is not selectable on 2420. */
 730 static struct clk func_96m_ck = {
 731         .name           = "func_96m_ck",
 732         .parent         = &apll96_ck,
 733         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 734                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 735         .init           = &omap2_init_clksel_parent,
 736         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 737         .clksel_mask    = OMAP2430_96M_SOURCE,
 738         .clksel         = func_96m_clksel,
 739         .recalc         = &omap2_clksel_recalc,
 740         .round_rate     = &omap2_clksel_round_rate,
 741         .set_rate       = &omap2_clksel_set_rate
 742 };
 743
 744 /* func_48m_ck */
 745
 746 static const struct clksel_rate func_48m_apll96_rates[] = {
 747         { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 748         { .div = 0 },
 749 };
 750
 751 static const struct clksel_rate func_48m_alt_rates[] = {
 752         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 753         { .div = 0 },
 754 };
 755
 756 static const struct clksel func_48m_clksel[] = {
 757         { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
 758         { .parent = &alt_ck, .rates = func_48m_alt_rates },
 759         { .parent = NULL }
 760 };
 761
 762 static struct clk func_48m_ck = {
 763         .name           = "func_48m_ck",
 764         .parent         = &apll96_ck,    /* 96M or Alt */
 765         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 766                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 767         .init           = &omap2_init_clksel_parent,
 768         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 769         .clksel_mask    = OMAP24XX_48M_SOURCE,
 770         .clksel         = func_48m_clksel,
 771         .recalc         = &omap2_clksel_recalc,
 772         .round_rate     = &omap2_clksel_round_rate,
 773         .set_rate       = &omap2_clksel_set_rate
 774 };
 775
 776 static struct clk func_12m_ck = {
 777         .name           = "func_12m_ck",
 778         .parent         = &func_48m_ck,
 779         .fixed_div      = 4,
 780         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 781                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 782         .recalc         = &omap2_fixed_divisor_recalc,
 783 };
 784
 785 /* Secure timer, only available in secure mode */
 786 static struct clk wdt1_osc_ck = {
 787         .name           = "ck_wdt1_osc",
 788         .parent         = &osc_ck,
 789         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 790         .recalc         = &followparent_recalc,
 791 };
 792
 793 /*
 794  * The common_clkout* clksel_rate structs are common to
 795  * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
 796  * sys_clkout2_* are 2420-only, so the
 797  * clksel_rate flags fields are inaccurate for those clocks. This is
 798  * harmless since access to those clocks are gated by the struct clk
 799  * flags fields, which mark them as 2420-only.
 800  */
 801 static const struct clksel_rate common_clkout_src_core_rates[] = {
 802         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 803         { .div = 0 }
 804 };
 805
 806 static const struct clksel_rate common_clkout_src_sys_rates[] = {
 807         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 808         { .div = 0 }
 809 };
 810
 811 static const struct clksel_rate common_clkout_src_96m_rates[] = {
 812         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 813         { .div = 0 }
 814 };
 815
 816 static const struct clksel_rate common_clkout_src_54m_rates[] = {
 817         { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
 818         { .div = 0 }
 819 };
 820
 821 static const struct clksel common_clkout_src_clksel[] = {
 822         { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
 823         { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
 824         { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
 825         { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
 826         { .parent = NULL }
 827 };
 828
 829 static struct clk sys_clkout_src = {
 830         .name           = "sys_clkout_src",
 831         .parent         = &func_54m_ck,
 832         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 833                                 RATE_PROPAGATES,
 834         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 835         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 836         .init           = &omap2_init_clksel_parent,
 837         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 838         .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
 839         .clksel         = common_clkout_src_clksel,
 840         .recalc         = &omap2_clksel_recalc,
 841         .round_rate     = &omap2_clksel_round_rate,
 842         .set_rate       = &omap2_clksel_set_rate
 843 };
 844
 845 static const struct clksel_rate common_clkout_rates[] = {
 846         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 847         { .div = 2, .val = 1, .flags = RATE_IN_24XX },
 848         { .div = 4, .val = 2, .flags = RATE_IN_24XX },
 849         { .div = 8, .val = 3, .flags = RATE_IN_24XX },
 850         { .div = 16, .val = 4, .flags = RATE_IN_24XX },
 851         { .div = 0 },
 852 };
 853
 854 static const struct clksel sys_clkout_clksel[] = {
 855         { .parent = &sys_clkout_src, .rates = common_clkout_rates },
 856         { .parent = NULL }
 857 };
 858
 859 static struct clk sys_clkout = {
 860         .name           = "sys_clkout",
 861         .parent         = &sys_clkout_src,
 862         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 863                                 PARENT_CONTROLS_CLOCK,
 864         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 865         .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
 866         .clksel         = sys_clkout_clksel,
 867         .recalc         = &omap2_clksel_recalc,
 868         .round_rate     = &omap2_clksel_round_rate,
 869         .set_rate       = &omap2_clksel_set_rate
 870 };
 871
 872 /* In 2430, new in 2420 ES2 */
 873 static struct clk sys_clkout2_src = {
 874         .name           = "sys_clkout2_src",
 875         .parent         = &func_54m_ck,
 876         .flags          = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
 877         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 878         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 879         .init           = &omap2_init_clksel_parent,
 880         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 881         .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
 882         .clksel         = common_clkout_src_clksel,
 883         .recalc         = &omap2_clksel_recalc,
 884         .round_rate     = &omap2_clksel_round_rate,
 885         .set_rate       = &omap2_clksel_set_rate
 886 };
 887
 888 static const struct clksel sys_clkout2_clksel[] = {
 889         { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
 890         { .parent = NULL }
 891 };
 892
 893 /* In 2430, new in 2420 ES2 */
 894 static struct clk sys_clkout2 = {
 895         .name           = "sys_clkout2",
 896         .parent         = &sys_clkout2_src,
 897         .flags          = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
 898         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 899         .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
 900         .clksel         = sys_clkout2_clksel,
 901         .recalc         = &omap2_clksel_recalc,
 902         .round_rate     = &omap2_clksel_round_rate,
 903         .set_rate       = &omap2_clksel_set_rate
 904 };
 905
 906 static struct clk emul_ck = {
 907         .name           = "emul_ck",
 908         .parent         = &func_54m_ck,
 909         .flags          = CLOCK_IN_OMAP242X,
 910         .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL,
 911         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 912         .recalc         = &followparent_recalc,
 913
 914 };
 915
 916 /*
 917  * MPU clock domain
 918  *      Clocks:
 919  *              MPU_FCLK, MPU_ICLK
 920  *              INT_M_FCLK, INT_M_I_CLK
 921  *
 922  * - Individual clocks are hardware managed.
 923  * - Base divider comes from: CM_CLKSEL_MPU
 924  *
 925  */
 926 static const struct clksel_rate mpu_core_rates[] = {
 927         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 928         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 929         { .div = 4, .val = 4, .flags = RATE_IN_242X },
 930         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 931         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 932         { .div = 0 },
 933 };
 934
 935 static const struct clksel mpu_clksel[] = {
 936         { .parent = &core_ck, .rates = mpu_core_rates },
 937         { .parent = NULL }
 938 };
 939
 940 static struct clk mpu_ck = {    /* Control cpu */
 941         .name           = "mpu_ck",
 942         .parent         = &core_ck,
 943         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 944                                 ALWAYS_ENABLED | DELAYED_APP |
 945                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
 946         .init           = &omap2_init_clksel_parent,
 947         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
 948         .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
 949         .clksel         = mpu_clksel,
 950         .recalc         = &omap2_clksel_recalc,
 951         .round_rate     = &omap2_clksel_round_rate,
 952         .set_rate       = &omap2_clksel_set_rate
 953 };
 954
 955 /*
 956  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
 957  * Clocks:
 958  *      2430: IVA2.1_FCLK, IVA2.1_ICLK
 959  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
 960  */
 961 /* XXX Okay, this is dumb.  iva2_1fck and dsp_fck are the same clock.
 962  * they should just be treated as such.
 963  */
 964
 965 /* iva2_1_fck */
 966 static const struct clksel_rate iva2_1_fck_core_rates[] = {
 967         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 968         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 969         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
 970         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
 971         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 972         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 973         { .div = 12, .val = 12, .flags = RATE_IN_242X },
 974         { .div = 0 },
 975 };
 976
 977 static const struct clksel iva2_1_fck_clksel[] = {
 978         { .parent = &core_ck, .rates = iva2_1_fck_core_rates },
 979         { .parent = NULL }
 980 };
 981
 982 static struct clk iva2_1_fck = {
 983         .name           = "iva2_1_fck",
 984         .parent         = &core_ck,
 985         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | RATE_PROPAGATES |
 986                                 CONFIG_PARTICIPANT,
 987         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 988         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
 989         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
 990         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
 991         .clksel         = iva2_1_fck_clksel,
 992         .recalc         = &omap2_clksel_recalc,
 993         .round_rate     = &omap2_clksel_round_rate,
 994         .set_rate       = &omap2_clksel_set_rate
 995 };
 996
 997 /* iva2_1_ick */
 998 static const struct clksel_rate iva2_1_ick_core_rates[] = {
 999         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1000         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1001         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1002         { .div = 0 },
1003 };
1004
1005 static const struct clksel iva2_1_ick_clksel[] = {
1006         { .parent = &core_ck, .rates = iva2_1_ick_core_rates },
1007         { .parent = NULL }
1008 };
1009
1010 static struct clk iva2_1_ick = {
1011         .name           = "iva2_1_ick",
1012         .parent         = &iva2_1_fck,
1013         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1014         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1015         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1016         .clksel         = iva2_1_ick_clksel,
1017         .recalc         = &omap2_clksel_recalc,
1018         .round_rate     = &omap2_clksel_round_rate,
1019         .set_rate       = &omap2_clksel_set_rate
1020 };
1021
1022 /*
1023  * Won't be too specific here. The core clock comes into this block
1024  * it is divided then tee'ed. One branch goes directly to xyz enable
1025  * controls. The other branch gets further divided by 2 then possibly
1026  * routed into a synchronizer and out of clocks abc.
1027  */
1028 static const struct clksel_rate dsp_fck_core_rates[] = {
1029         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1030         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1031         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1032         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1033         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1034         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1035         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1036         { .div = 0 },
1037 };
1038
1039 static const struct clksel dsp_fck_clksel[] = {
1040         { .parent = &core_ck, .rates = dsp_fck_core_rates },
1041         { .parent = NULL }
1042 };
1043
1044 static struct clk dsp_fck = {
1045         .name           = "dsp_fck",
1046         .parent         = &core_ck,
1047         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP |
1048                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1049         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
1050         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1051         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1052         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
1053         .clksel         = dsp_fck_clksel,
1054         .recalc         = &omap2_clksel_recalc,
1055         .round_rate     = &omap2_clksel_round_rate,
1056         .set_rate       = &omap2_clksel_set_rate
1057 };
1058
1059 static const struct clksel_rate dsp_ick_core_rates[] = {
1060         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1061         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1062         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1063         { .div = 0 },
1064 };
1065
1066 static const struct clksel dsp_ick_clksel[] = {
1067         { .parent = &core_ck, .rates = dsp_ick_core_rates },
1068         { .parent = NULL }
1069 };
1070
1071 static struct clk dsp_ick = {
1072         .name           = "dsp_ick",     /* apparently ipi and isp */
1073         .parent         = &core_ck,
1074         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
1075         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
1076         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,            /* for ipi */
1077         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1078         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1079         .clksel         = dsp_ick_clksel,
1080         .recalc         = &omap2_clksel_recalc,
1081 };
1082
1083 static const struct clksel_rate iva1_ifck_core_rates[] = {
1084         { .div = 1, .val = 1, .flags = RATE_IN_242X | DEFAULT_RATE },
1085         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1086         { .div = 3, .val = 3, .flags = RATE_IN_242X },
1087         { .div = 4, .val = 4, .flags = RATE_IN_242X },
1088         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1089         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1090         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1091         { .div = 0 },
1092 };
1093
1094 static const struct clksel iva1_ifck_clksel[] = {
1095         { .parent = &core_ck, .rates = iva1_ifck_core_rates },
1096         { .parent = NULL }
1097 };
1098
1099 static struct clk iva1_ifck = {
1100         .name           = "iva1_ifck",
1101         .parent         = &core_ck,
1102         .flags          = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
1103                                 RATE_PROPAGATES | DELAYED_APP,
1104         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
1105         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
1106         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1107         .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
1108         .clksel         = iva1_ifck_clksel,
1109         .recalc         = &omap2_clksel_recalc,
1110         .round_rate     = &omap2_clksel_round_rate,
1111         .set_rate       = &omap2_clksel_set_rate
1112 };
1113
1114 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1115 static struct clk iva1_mpu_int_ifck = {
1116         .name           = "iva1_mpu_int_ifck",
1117         .parent         = &iva1_ifck,
1118         .flags          = CLOCK_IN_OMAP242X,
1119         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
1120         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
1121         .fixed_div      = 2,
1122         .recalc         = &omap2_fixed_divisor_recalc,
1123 };
1124
1125 /*
1126  * L3 clock domain
1127  * L3 clocks are used for both interface and functional clocks to
1128  * multiple entities. Some of these clocks are completely managed
1129  * by hardware, and some others allow software control. Hardware
1130  * managed ones general are based on directly CLK_REQ signals and
1131  * various auto idle settings. The functional spec sets many of these
1132  * as 'tie-high' for their enables.
1133  *
1134  * I-CLOCKS:
1135  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1136  *      CAM, HS-USB.
1137  * F-CLOCK
1138  *      SSI.
1139  *
1140  * GPMC memories and SDRC have timing and clock sensitive registers which
1141  * may very well need notification when the clock changes. Currently for low
1142  * operating points, these are taken care of in sleep.S.
1143  */
1144 static const struct clksel_rate core_l3_core_rates[] = {
1145         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1146         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1147         { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1148         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1149         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1150         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1151         { .div = 16, .val = 16, .flags = RATE_IN_242X },
1152         { .div = 0 }
1153 };
1154
1155 static const struct clksel core_l3_clksel[] = {
1156         { .parent = &core_ck, .rates = core_l3_core_rates },
1157         { .parent = NULL }
1158 };
1159
1160 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
1161         .name           = "core_l3_ck",
1162         .parent         = &core_ck,
1163         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1164                                 ALWAYS_ENABLED | DELAYED_APP |
1165                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1166         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1167         .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
1168         .clksel         = core_l3_clksel,
1169         .recalc         = &omap2_clksel_recalc,
1170         .round_rate     = &omap2_clksel_round_rate,
1171         .set_rate       = &omap2_clksel_set_rate
1172 };
1173
1174 /* usb_l4_ick */
1175 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1176         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1177         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1178         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1179         { .div = 0 }
1180 };
1181
1182 static const struct clksel usb_l4_ick_clksel[] = {
1183         { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1184         { .parent = NULL },
1185 };
1186
1187 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
1188         .name           = "usb_l4_ick",
1189         .parent         = &core_l3_ck,
1190         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1191                                 DELAYED_APP | CONFIG_PARTICIPANT,
1192         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1193         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1194         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1195         .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
1196         .clksel         = usb_l4_ick_clksel,
1197         .recalc         = &omap2_clksel_recalc,
1198         .round_rate     = &omap2_clksel_round_rate,
1199         .set_rate       = &omap2_clksel_set_rate
1200 };
1201
1202 /*
1203  * SSI is in L3 management domain, its direct parent is core not l3,
1204  * many core power domain entities are grouped into the L3 clock
1205  * domain.
1206  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
1207  *
1208  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1209  */
1210 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1211         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1212         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1213         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1214         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1215         { .div = 5, .val = 5, .flags = RATE_IN_243X },
1216         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1217         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1218         { .div = 0 }
1219 };
1220
1221 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1222         { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1223         { .parent = NULL }
1224 };
1225
1226 static struct clk ssi_ssr_sst_fck = {
1227         .name           = "ssi_fck",
1228         .parent         = &core_ck,
1229         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1230                                 DELAYED_APP,
1231         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),       /* bit 1 */
1232         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1233         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1234         .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
1235         .clksel         = ssi_ssr_sst_fck_clksel,
1236         .recalc         = &omap2_clksel_recalc,
1237         .round_rate     = &omap2_clksel_round_rate,
1238         .set_rate       = &omap2_clksel_set_rate
1239 };
1240
1241 /*
1242  * GFX clock domain
1243  *      Clocks:
1244  * GFX_FCLK, GFX_ICLK
1245  * GFX_CG1(2d), GFX_CG2(3d)
1246  *
1247  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1248  * The 2d and 3d clocks run at a hardware determined
1249  * divided value of fclk.
1250  *
1251  */
1252 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1253
1254 /*
1255  * These clksel_rate/clksel structs are shared between gfx_3d_fck and
1256  * gfx_2d_fck
1257  */
1258 static const struct clksel_rate gfx_fck_core_l3_rates[] = {
1259         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1260         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1261         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1262         { .div = 4, .val = 4, .flags = RATE_IN_243X },
1263         { .div = 0 }
1264 };
1265
1266 static const struct clksel gfx_fck_clksel[] = {
1267         { .parent = &core_l3_ck, .rates = gfx_fck_core_l3_rates },
1268         { .parent = NULL },
1269 };
1270
1271 static struct clk gfx_3d_fck = {
1272         .name           = "gfx_3d_fck",
1273         .parent         = &core_l3_ck,
1274         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1275         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
1276         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
1277         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1278         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1279         .clksel         = gfx_fck_clksel,
1280         .recalc         = &omap2_clksel_recalc,
1281         .round_rate     = &omap2_clksel_round_rate,
1282         .set_rate       = &omap2_clksel_set_rate
1283 };
1284
1285 static struct clk gfx_2d_fck = {
1286         .name           = "gfx_2d_fck",
1287         .parent         = &core_l3_ck,
1288         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1289         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
1290         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
1291         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1292         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1293         .clksel         = gfx_fck_clksel,
1294         .recalc         = &omap2_clksel_recalc,
1295         .round_rate     = &omap2_clksel_round_rate,
1296         .set_rate       = &omap2_clksel_set_rate
1297 };
1298
1299 static struct clk gfx_ick = {
1300         .name           = "gfx_ick",            /* From l3 */
1301         .parent         = &core_l3_ck,
1302         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1303         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),  /* bit 0 */
1304         .enable_bit     = OMAP_EN_GFX_SHIFT,
1305         .recalc         = &followparent_recalc,
1306 };
1307
1308 /*
1309  * Modem clock domain (2430)
1310  *      CLOCKS:
1311  *              MDM_OSC_CLK
1312  *              MDM_ICLK
1313  * These clocks are usable in chassis mode only.
1314  */
1315 static const struct clksel_rate mdm_ick_core_rates[] = {
1316         { .div = 1, .val = 1, .flags = RATE_IN_243X },
1317         { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1318         { .div = 6, .val = 6, .flags = RATE_IN_243X },
1319         { .div = 9, .val = 9, .flags = RATE_IN_243X },
1320         { .div = 0 }
1321 };
1322
1323 static const struct clksel mdm_ick_clksel[] = {
1324         { .parent = &core_ck, .rates = mdm_ick_core_rates },
1325         { .parent = NULL }
1326 };
1327
1328 static struct clk mdm_ick = {           /* used both as a ick and fck */
1329         .name           = "mdm_ick",
1330         .parent         = &core_ck,
1331         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1332         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1333         .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1334         .clksel_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
1335         .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
1336         .clksel         = mdm_ick_clksel,
1337         .recalc         = &omap2_clksel_recalc,
1338         .round_rate     = &omap2_clksel_round_rate,
1339         .set_rate       = &omap2_clksel_set_rate
1340 };
1341
1342 static struct clk mdm_osc_ck = {
1343         .name           = "mdm_osc_ck",
1344         .parent         = &osc_ck,
1345         .flags          = CLOCK_IN_OMAP243X,
1346         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, OMAP24XX_CM_FCLKEN),
1347         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
1348         .recalc         = &followparent_recalc,
1349 };
1350
1351 /*
1352  * L4 clock management domain
1353  *
1354  * This domain contains lots of interface clocks from the L4 interface, some
1355  * functional clocks.   Fixed APLL functional source clocks are managed in
1356  * this domain.
1357  */
1358 static const struct clksel_rate l4_core_l3_rates[] = {
1359         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1360         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1361         { .div = 0 }
1362 };
1363
1364 static const struct clksel l4_clksel[] = {
1365         { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1366         { .parent = NULL }
1367 };
1368
1369 static struct clk l4_ck = {             /* used both as an ick and fck */
1370         .name           = "l4_ck",
1371         .parent         = &core_l3_ck,
1372         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1373                                 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1374         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1375         .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
1376         .clksel         = l4_clksel,
1377         .recalc         = &omap2_clksel_recalc,
1378         .round_rate     = &omap2_clksel_round_rate,
1379         .set_rate       = &omap2_clksel_set_rate
1380 };
1381
1382 static struct clk ssi_l4_ick = {
1383         .name           = "ssi_l4_ick",
1384         .parent         = &l4_ck,
1385         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1386         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),        /* bit 1 */
1387         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1388         .recalc         = &followparent_recalc,
1389 };
1390
1391 /*
1392  * DSS clock domain
1393  * CLOCKs:
1394  * DSS_L4_ICLK, DSS_L3_ICLK,
1395  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1396  *
1397  * DSS is both initiator and target.
1398  */
1399 /* XXX Add RATE_NOT_VALIDATED */
1400
1401 static const struct clksel_rate dss1_fck_sys_rates[] = {
1402         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1403         { .div = 0 }
1404 };
1405
1406 static const struct clksel_rate dss1_fck_core_rates[] = {
1407         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1408         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1409         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1410         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1411         { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1412         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1413         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1414         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1415         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1416         { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1417         { .div = 0 }
1418 };
1419
1420 static const struct clksel dss1_fck_clksel[] = {
1421         { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
1422         { .parent = &core_ck, .rates = dss1_fck_core_rates },
1423         { .parent = NULL },
1424 };
1425
1426 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1427         .name           = "dss_ick",
1428         .parent         = &l4_ck,       /* really both l3 and l4 */
1429         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1430         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1431         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1432         .recalc         = &followparent_recalc,
1433 };
1434
1435 static struct clk dss1_fck = {
1436         .name           = "dss1_fck",
1437         .parent         = &core_ck,             /* Core or sys */
1438         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1439                                 DELAYED_APP,
1440         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1441         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1442         .init           = &omap2_init_clksel_parent,
1443         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1444         .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
1445         .clksel         = dss1_fck_clksel,
1446         .recalc         = &omap2_clksel_recalc,
1447         .round_rate     = &omap2_clksel_round_rate,
1448         .set_rate       = &omap2_clksel_set_rate
1449 };
1450
1451 static const struct clksel_rate dss2_fck_sys_rates[] = {
1452         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1453         { .div = 0 }
1454 };
1455
1456 static const struct clksel_rate dss2_fck_48m_rates[] = {
1457         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1458         { .div = 0 }
1459 };
1460
1461 static const struct clksel dss2_fck_clksel[] = {
1462         { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
1463         { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1464         { .parent = NULL }
1465 };
1466
1467 static struct clk dss2_fck = {          /* Alt clk used in power management */
1468         .name           = "dss2_fck",
1469         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1470         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1471                                 DELAYED_APP,
1472         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1473         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
1474         .init           = &omap2_init_clksel_parent,
1475         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1476         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
1477         .clksel         = dss2_fck_clksel,
1478         .recalc         = &followparent_recalc,
1479 };
1480
1481 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1482         .name           = "dss_54m_fck",        /* 54m tv clk */
1483         .parent         = &func_54m_ck,
1484         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1485         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1486         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
1487         .recalc         = &followparent_recalc,
1488 };
1489
1490 /*
1491  * CORE power domain ICLK & FCLK defines.
1492  * Many of the these can have more than one possible parent. Entries
1493  * here will likely have an L4 interface parent, and may have multiple
1494  * functional clock parents.
1495  */
1496 static const struct clksel_rate gpt_32k_rates[] = {
1497         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1498         { .div = 0 }
1499 };
1500
1501 static const struct clksel_rate gpt_sys_rates[] = {
1502         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1503         { .div = 0 }
1504 };
1505
1506 static const struct clksel_rate gpt_alt_rates[] = {
1507         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1508         { .div = 0 }
1509 };
1510
1511 static const struct clksel gpt_clksel[] = {
1512         { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1513         { .parent = &sys_ck,      .rates = gpt_sys_rates },
1514         { .parent = &alt_ck,      .rates = gpt_alt_rates },
1515         { .parent = NULL },
1516 };
1517
1518 static struct clk gpt1_ick = {
1519         .name           = "gpt1_ick",
1520         .parent         = &l4_ck,
1521         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1522         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), /* Bit0 */
1523         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1524         .recalc         = &followparent_recalc,
1525 };
1526
1527 static struct clk gpt1_fck = {
1528         .name           = "gpt1_fck",
1529         .parent         = &func_32k_ck,
1530         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1531         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),        /* Bit0 */
1532         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1533         .init           = &omap2_init_clksel_parent,
1534         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1535         .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
1536         .clksel         = gpt_clksel,
1537         .recalc         = &omap2_clksel_recalc,
1538         .round_rate     = &omap2_clksel_round_rate,
1539         .set_rate       = &omap2_clksel_set_rate
1540 };
1541
1542 static struct clk gpt2_ick = {
1543         .name           = "gpt2_ick",
1544         .parent         = &l4_ck,
1545         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1546         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit4 */
1547         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1548         .recalc         = &followparent_recalc,
1549 };
1550
1551 static struct clk gpt2_fck = {
1552         .name           = "gpt2_fck",
1553         .parent         = &func_32k_ck,
1554         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1555         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1556         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1557         .init           = &omap2_init_clksel_parent,
1558         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1559         .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
1560         .clksel         = gpt_clksel,
1561         .recalc         = &omap2_clksel_recalc,
1562 };
1563
1564 static struct clk gpt3_ick = {
1565         .name           = "gpt3_ick",
1566         .parent         = &l4_ck,
1567         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1568         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit5 */
1569         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1570         .recalc         = &followparent_recalc,
1571 };
1572
1573 static struct clk gpt3_fck = {
1574         .name           = "gpt3_fck",
1575         .parent         = &func_32k_ck,
1576         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1577         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1578         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1579         .init           = &omap2_init_clksel_parent,
1580         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1581         .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
1582         .clksel         = gpt_clksel,
1583         .recalc         = &omap2_clksel_recalc,
1584 };
1585
1586 static struct clk gpt4_ick = {
1587         .name           = "gpt4_ick",
1588         .parent         = &l4_ck,
1589         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1590         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit6 */
1591         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1592         .recalc         = &followparent_recalc,
1593 };
1594
1595 static struct clk gpt4_fck = {
1596         .name           = "gpt4_fck",
1597         .parent         = &func_32k_ck,
1598         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1599         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1600         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1601         .init           = &omap2_init_clksel_parent,
1602         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1603         .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
1604         .clksel         = gpt_clksel,
1605         .recalc         = &omap2_clksel_recalc,
1606 };
1607
1608 static struct clk gpt5_ick = {
1609         .name           = "gpt5_ick",
1610         .parent         = &l4_ck,
1611         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1612         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* Bit7 */
1613         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1614         .recalc         = &followparent_recalc,
1615 };
1616
1617 static struct clk gpt5_fck = {
1618         .name           = "gpt5_fck",
1619         .parent         = &func_32k_ck,
1620         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1621         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1622         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1623         .init           = &omap2_init_clksel_parent,
1624         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1625         .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
1626         .clksel         = gpt_clksel,
1627         .recalc         = &omap2_clksel_recalc,
1628 };
1629
1630 static struct clk gpt6_ick = {
1631         .name           = "gpt6_ick",
1632         .parent         = &l4_ck,
1633         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1634         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit8 */
1635         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1636         .recalc         = &followparent_recalc,
1637 };
1638
1639 static struct clk gpt6_fck = {
1640         .name           = "gpt6_fck",
1641         .parent         = &func_32k_ck,
1642         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1643         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1644         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1645         .init           = &omap2_init_clksel_parent,
1646         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1647         .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
1648         .clksel         = gpt_clksel,
1649         .recalc         = &omap2_clksel_recalc,
1650 };
1651
1652 static struct clk gpt7_ick = {
1653         .name           = "gpt7_ick",
1654         .parent         = &l4_ck,
1655         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1656         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit9 */
1657         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1658         .recalc         = &followparent_recalc,
1659 };
1660
1661 static struct clk gpt7_fck = {
1662         .name           = "gpt7_fck",
1663         .parent         = &func_32k_ck,
1664         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1665         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1666         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1667         .init           = &omap2_init_clksel_parent,
1668         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1669         .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
1670         .clksel         = gpt_clksel,
1671         .recalc         = &omap2_clksel_recalc,
1672 };
1673
1674 static struct clk gpt8_ick = {
1675         .name           = "gpt8_ick",
1676         .parent         = &l4_ck,
1677         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1678         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit10 */
1679         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1680         .recalc         = &followparent_recalc,
1681 };
1682
1683 static struct clk gpt8_fck = {
1684         .name           = "gpt8_fck",
1685         .parent         = &func_32k_ck,
1686         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1687         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1688         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1689         .init           = &omap2_init_clksel_parent,
1690         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1691         .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
1692         .clksel         = gpt_clksel,
1693         .recalc         = &omap2_clksel_recalc,
1694 };
1695
1696 static struct clk gpt9_ick = {
1697         .name           = "gpt9_ick",
1698         .parent         = &l4_ck,
1699         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1700         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1701         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1702         .recalc         = &followparent_recalc,
1703 };
1704
1705 static struct clk gpt9_fck = {
1706         .name           = "gpt9_fck",
1707         .parent         = &func_32k_ck,
1708         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1709         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1710         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1711         .init           = &omap2_init_clksel_parent,
1712         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1713         .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
1714         .clksel         = gpt_clksel,
1715         .recalc         = &omap2_clksel_recalc,
1716 };
1717
1718 static struct clk gpt10_ick = {
1719         .name           = "gpt10_ick",
1720         .parent         = &l4_ck,
1721         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1722         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1723         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1724         .recalc         = &followparent_recalc,
1725 };
1726
1727 static struct clk gpt10_fck = {
1728         .name           = "gpt10_fck",
1729         .parent         = &func_32k_ck,
1730         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1731         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1732         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1733         .init           = &omap2_init_clksel_parent,
1734         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1735         .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
1736         .clksel         = gpt_clksel,
1737         .recalc         = &omap2_clksel_recalc,
1738 };
1739
1740 static struct clk gpt11_ick = {
1741         .name           = "gpt11_ick",
1742         .parent         = &l4_ck,
1743         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1744         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1745         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1746         .recalc         = &followparent_recalc,
1747 };
1748
1749 static struct clk gpt11_fck = {
1750         .name           = "gpt11_fck",
1751         .parent         = &func_32k_ck,
1752         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1753         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1754         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1755         .init           = &omap2_init_clksel_parent,
1756         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1757         .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
1758         .clksel         = gpt_clksel,
1759         .recalc         = &omap2_clksel_recalc,
1760 };
1761
1762 static struct clk gpt12_ick = {
1763         .name           = "gpt12_ick",
1764         .parent         = &l4_ck,
1765         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1766         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit14 */
1767         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1768         .recalc         = &followparent_recalc,
1769 };
1770
1771 static struct clk gpt12_fck = {
1772         .name           = "gpt12_fck",
1773         .parent         = &func_32k_ck,
1774         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1775         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1776         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1777         .init           = &omap2_init_clksel_parent,
1778         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1779         .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
1780         .clksel         = gpt_clksel,
1781         .recalc         = &omap2_clksel_recalc,
1782 };
1783
1784 static struct clk mcbsp1_ick = {
1785         .name           = "mcbsp1_ick",
1786         .parent         = &l4_ck,
1787         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1788         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1789         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1790         .recalc         = &followparent_recalc,
1791 };
1792
1793 static struct clk mcbsp1_fck = {
1794         .name           = "mcbsp1_fck",
1795         .parent         = &func_96m_ck,
1796         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1797         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1798         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1799         .recalc         = &followparent_recalc,
1800 };
1801
1802 static struct clk mcbsp2_ick = {
1803         .name           = "mcbsp2_ick",
1804         .parent         = &l4_ck,
1805         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1806         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1807         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1808         .recalc         = &followparent_recalc,
1809 };
1810
1811 static struct clk mcbsp2_fck = {
1812         .name           = "mcbsp2_fck",
1813         .parent         = &func_96m_ck,
1814         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1815         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1816         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1817         .recalc         = &followparent_recalc,
1818 };
1819
1820 static struct clk mcbsp3_ick = {
1821         .name           = "mcbsp3_ick",
1822         .parent         = &l4_ck,
1823         .flags          = CLOCK_IN_OMAP243X,
1824         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1825         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1826         .recalc         = &followparent_recalc,
1827 };
1828
1829 static struct clk mcbsp3_fck = {
1830         .name           = "mcbsp3_fck",
1831         .parent         = &func_96m_ck,
1832         .flags          = CLOCK_IN_OMAP243X,
1833         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1834         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1835         .recalc         = &followparent_recalc,
1836 };
1837
1838 static struct clk mcbsp4_ick = {
1839         .name           = "mcbsp4_ick",
1840         .parent         = &l4_ck,
1841         .flags          = CLOCK_IN_OMAP243X,
1842         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1843         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1844         .recalc         = &followparent_recalc,
1845 };
1846
1847 static struct clk mcbsp4_fck = {
1848         .name           = "mcbsp4_fck",
1849         .parent         = &func_96m_ck,
1850         .flags          = CLOCK_IN_OMAP243X,
1851         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1852         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1853         .recalc         = &followparent_recalc,
1854 };
1855
1856 static struct clk mcbsp5_ick = {
1857         .name           = "mcbsp5_ick",
1858         .parent         = &l4_ck,
1859         .flags          = CLOCK_IN_OMAP243X,
1860         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1861         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1862         .recalc         = &followparent_recalc,
1863 };
1864
1865 static struct clk mcbsp5_fck = {
1866         .name           = "mcbsp5_fck",
1867         .parent         = &func_96m_ck,
1868         .flags          = CLOCK_IN_OMAP243X,
1869         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1870         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1871         .recalc         = &followparent_recalc,
1872 };
1873
1874 static struct clk mcspi1_ick = {
1875         .name           = "mcspi_ick",
1876         .id             = 1,
1877         .parent         = &l4_ck,
1878         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1879         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1880         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1881         .recalc         = &followparent_recalc,
1882 };
1883
1884 static struct clk mcspi1_fck = {
1885         .name           = "mcspi_fck",
1886         .id             = 1,
1887         .parent         = &func_48m_ck,
1888         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1889         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1890         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1891         .recalc         = &followparent_recalc,
1892 };
1893
1894 static struct clk mcspi2_ick = {
1895         .name           = "mcspi_ick",
1896         .id             = 2,
1897         .parent         = &l4_ck,
1898         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1899         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1900         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1901         .recalc         = &followparent_recalc,
1902 };
1903
1904 static struct clk mcspi2_fck = {
1905         .name           = "mcspi_fck",
1906         .id             = 2,
1907         .parent         = &func_48m_ck,
1908         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1909         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1910         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1911         .recalc         = &followparent_recalc,
1912 };
1913
1914 static struct clk mcspi3_ick = {
1915         .name           = "mcspi_ick",
1916         .id             = 3,
1917         .parent         = &l4_ck,
1918         .flags          = CLOCK_IN_OMAP243X,
1919         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1920         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1921         .recalc         = &followparent_recalc,
1922 };
1923
1924 static struct clk mcspi3_fck = {
1925         .name           = "mcspi_fck",
1926         .id             = 3,
1927         .parent         = &func_48m_ck,
1928         .flags          = CLOCK_IN_OMAP243X,
1929         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1930         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1931         .recalc         = &followparent_recalc,
1932 };
1933
1934 static struct clk uart1_ick = {
1935         .name           = "uart1_ick",
1936         .parent         = &l4_ck,
1937         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1938         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1939         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1940         .recalc         = &followparent_recalc,
1941 };
1942
1943 static struct clk uart1_fck = {
1944         .name           = "uart1_fck",
1945         .parent         = &func_48m_ck,
1946         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1947         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1948         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1949         .recalc         = &followparent_recalc,
1950 };
1951
1952 static struct clk uart2_ick = {
1953         .name           = "uart2_ick",
1954         .parent         = &l4_ck,
1955         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1956         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1957         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1958         .recalc         = &followparent_recalc,
1959 };
1960
1961 static struct clk uart2_fck = {
1962         .name           = "uart2_fck",
1963         .parent         = &func_48m_ck,
1964         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1965         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1966         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1967         .recalc         = &followparent_recalc,
1968 };
1969
1970 static struct clk uart3_ick = {
1971         .name           = "uart3_ick",
1972         .parent         = &l4_ck,
1973         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1974         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1975         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1976         .recalc         = &followparent_recalc,
1977 };
1978
1979 static struct clk uart3_fck = {
1980         .name           = "uart3_fck",
1981         .parent         = &func_48m_ck,
1982         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1983         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1984         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1985         .recalc         = &followparent_recalc,
1986 };
1987
1988 static struct clk gpios_ick = {
1989         .name           = "gpios_ick",
1990         .parent         = &l4_ck,
1991         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1992         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1993         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1994         .recalc         = &followparent_recalc,
1995 };
1996
1997 static struct clk gpios_fck = {
1998         .name           = "gpios_fck",
1999         .parent         = &func_32k_ck,
2000         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2001         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
2002         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2003         .recalc         = &followparent_recalc,
2004 };
2005
2006 static struct clk mpu_wdt_ick = {
2007         .name           = "mpu_wdt_ick",
2008         .parent         = &l4_ck,
2009         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2010         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2011         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2012         .recalc         = &followparent_recalc,
2013 };
2014
2015 static struct clk mpu_wdt_fck = {
2016         .name           = "mpu_wdt_fck",
2017         .parent         = &func_32k_ck,
2018         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2019         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
2020         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2021         .recalc         = &followparent_recalc,
2022 };
2023
2024 static struct clk sync_32k_ick = {
2025         .name           = "sync_32k_ick",
2026         .parent         = &l4_ck,
2027         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2028         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2029         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
2030         .recalc         = &followparent_recalc,
2031 };
2032 static struct clk wdt1_ick = {
2033         .name           = "wdt1_ick",
2034         .parent         = &l4_ck,
2035         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2036         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2037         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
2038         .recalc         = &followparent_recalc,
2039 };
2040 static struct clk omapctrl_ick = {
2041         .name           = "omapctrl_ick",
2042         .parent         = &l4_ck,
2043         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2044         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2045         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
2046         .recalc         = &followparent_recalc,
2047 };
2048 static struct clk icr_ick = {
2049         .name           = "icr_ick",
2050         .parent         = &l4_ck,
2051         .flags          = CLOCK_IN_OMAP243X,
2052         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2053         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
2054         .recalc         = &followparent_recalc,
2055 };
2056
2057 static struct clk cam_ick = {
2058         .name           = "cam_ick",
2059         .parent         = &l4_ck,
2060         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2061         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2062         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2063         .recalc         = &followparent_recalc,
2064 };
2065
2066 static struct clk cam_fck = {
2067         .name           = "cam_fck",
2068         .parent         = &func_96m_ck,
2069         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2070         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2071         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2072         .recalc         = &followparent_recalc,
2073 };
2074
2075 static struct clk mailboxes_ick = {
2076         .name           = "mailboxes_ick",
2077         .parent         = &l4_ck,
2078         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2079         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2080         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
2081         .recalc         = &followparent_recalc,
2082 };
2083
2084 static struct clk wdt4_ick = {
2085         .name           = "wdt4_ick",
2086         .parent         = &l4_ck,
2087         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2088         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2089         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2090         .recalc         = &followparent_recalc,
2091 };
2092
2093 static struct clk wdt4_fck = {
2094         .name           = "wdt4_fck",
2095         .parent         = &func_32k_ck,
2096         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2097         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2098         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2099         .recalc         = &followparent_recalc,
2100 };
2101
2102 static struct clk wdt3_ick = {
2103         .name           = "wdt3_ick",
2104         .parent         = &l4_ck,
2105         .flags          = CLOCK_IN_OMAP242X,
2106         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2107         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2108         .recalc         = &followparent_recalc,
2109 };
2110
2111 static struct clk wdt3_fck = {
2112         .name           = "wdt3_fck",
2113         .parent         = &func_32k_ck,
2114         .flags          = CLOCK_IN_OMAP242X,
2115         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2116         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2117         .recalc         = &followparent_recalc,
2118 };
2119
2120 static struct clk mspro_ick = {
2121         .name           = "mspro_ick",
2122         .parent         = &l4_ck,
2123         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2124         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2125         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2126         .recalc         = &followparent_recalc,
2127 };
2128
2129 static struct clk mspro_fck = {
2130         .name           = "mspro_fck",
2131         .parent         = &func_96m_ck,
2132         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2133         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2134         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2135         .recalc         = &followparent_recalc,
2136 };
2137
2138 static struct clk mmc_ick = {
2139         .name           = "mmc_ick",
2140         .parent         = &l4_ck,
2141         .flags          = CLOCK_IN_OMAP242X,
2142         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2143         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2144         .recalc         = &followparent_recalc,
2145 };
2146
2147 static struct clk mmc_fck = {
2148         .name           = "mmc_fck",
2149         .parent         = &func_96m_ck,
2150         .flags          = CLOCK_IN_OMAP242X,
2151         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2152         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2153         .recalc         = &followparent_recalc,
2154 };
2155
2156 static struct clk fac_ick = {
2157         .name           = "fac_ick",
2158         .parent         = &l4_ck,
2159         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2160         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2161         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2162         .recalc         = &followparent_recalc,
2163 };
2164
2165 static struct clk fac_fck = {
2166         .name           = "fac_fck",
2167         .parent         = &func_12m_ck,
2168         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2169         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2170         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2171         .recalc         = &followparent_recalc,
2172 };
2173
2174 static struct clk eac_ick = {
2175         .name           = "eac_ick",
2176         .parent         = &l4_ck,
2177         .flags          = CLOCK_IN_OMAP242X,
2178         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2179         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2180         .recalc         = &followparent_recalc,
2181 };
2182
2183 static struct clk eac_fck = {
2184         .name           = "eac_fck",
2185         .parent         = &func_96m_ck,
2186         .flags          = CLOCK_IN_OMAP242X,
2187         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2188         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2189         .recalc         = &followparent_recalc,
2190 };
2191
2192 static struct clk hdq_ick = {
2193         .name           = "hdq_ick",
2194         .parent         = &l4_ck,
2195         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2196         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2197         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2198         .recalc         = &followparent_recalc,
2199 };
2200
2201 static struct clk hdq_fck = {
2202         .name           = "hdq_fck",
2203         .parent         = &func_12m_ck,
2204         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2205         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2206         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2207         .recalc         = &followparent_recalc,
2208 };
2209
2210 static struct clk i2c2_ick = {
2211         .name           = "i2c_ick",
2212         .id             = 2,
2213         .parent         = &l4_ck,
2214         .flags          = CLOCK_IN_OMAP242X,
2215         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2216         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2217         .recalc         = &followparent_recalc,
2218 };
2219
2220 static struct clk i2c2_fck = {
2221         .name           = "i2c_fck",
2222         .id             = 2,
2223         .parent         = &func_12m_ck,
2224         .flags          = CLOCK_IN_OMAP242X,
2225         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2226         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2227         .recalc         = &followparent_recalc,
2228 };
2229
2230 static struct clk i2chs2_fck = {
2231         .name           = "i2chs_fck",
2232         .id             = 2,
2233         .parent         = &func_96m_ck,
2234         .flags          = CLOCK_IN_OMAP243X,
2235         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2236         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
2237         .recalc         = &followparent_recalc,
2238 };
2239
2240 static struct clk i2c1_ick = {
2241         .name           = "i2c_ick",
2242         .id             = 1,
2243         .parent         = &l4_ck,
2244         .flags          = CLOCK_IN_OMAP242X,
2245         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2246         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2247         .recalc         = &followparent_recalc,
2248 };
2249
2250 static struct clk i2c1_fck = {
2251         .name           = "i2c_fck",
2252         .id             = 1,
2253         .parent         = &func_12m_ck,
2254         .flags          = CLOCK_IN_OMAP242X,
2255         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2256         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2257         .recalc         = &followparent_recalc,
2258 };
2259
2260 static struct clk i2chs1_fck = {
2261         .name           = "i2chs_fck",
2262         .id             = 1,
2263         .parent         = &func_96m_ck,
2264         .flags          = CLOCK_IN_OMAP243X,
2265         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2266         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
2267         .recalc         = &followparent_recalc,
2268 };
2269
2270 static struct clk vlynq_ick = {
2271         .name           = "vlynq_ick",
2272         .parent         = &core_l3_ck,
2273         .flags          = CLOCK_IN_OMAP242X,
2274         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2275         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2276         .recalc         = &followparent_recalc,
2277 };
2278
2279 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2280         { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2281         { .div = 0 }
2282 };
2283
2284 static const struct clksel_rate vlynq_fck_core_rates[] = {
2285         { .div = 1, .val = 1, .flags = RATE_IN_242X },
2286         { .div = 2, .val = 2, .flags = RATE_IN_242X },
2287         { .div = 3, .val = 3, .flags = RATE_IN_242X },
2288         { .div = 4, .val = 4, .flags = RATE_IN_242X },
2289         { .div = 6, .val = 6, .flags = RATE_IN_242X },
2290         { .div = 8, .val = 8, .flags = RATE_IN_242X },
2291         { .div = 9, .val = 9, .flags = RATE_IN_242X },
2292         { .div = 12, .val = 12, .flags = RATE_IN_242X },
2293         { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2294         { .div = 18, .val = 18, .flags = RATE_IN_242X },
2295         { .div = 0 }
2296 };
2297
2298 static const struct clksel vlynq_fck_clksel[] = {
2299         { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2300         { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
2301         { .parent = NULL }
2302 };
2303
2304 static struct clk vlynq_fck = {
2305         .name           = "vlynq_fck",
2306         .parent         = &func_96m_ck,
2307         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP,
2308         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2309         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2310         .init           = &omap2_init_clksel_parent,
2311         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
2312         .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
2313         .clksel         = vlynq_fck_clksel,
2314         .recalc         = &omap2_clksel_recalc,
2315         .round_rate     = &omap2_clksel_round_rate,
2316         .set_rate       = &omap2_clksel_set_rate
2317 };
2318
2319 static struct clk sdrc_ick = {
2320         .name           = "sdrc_ick",
2321         .parent         = &l4_ck,
2322         .flags          = CLOCK_IN_OMAP243X,
2323         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP2430_CM_ICLKEN3),
2324         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
2325         .recalc         = &followparent_recalc,
2326 };
2327
2328 static struct clk des_ick = {
2329         .name           = "des_ick",
2330         .parent         = &l4_ck,
2331         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2332         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2333         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
2334         .recalc         = &followparent_recalc,
2335 };
2336
2337 static struct clk sha_ick = {
2338         .name           = "sha_ick",
2339         .parent         = &l4_ck,
2340         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2341         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2342         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
2343         .recalc         = &followparent_recalc,
2344 };
2345
2346 static struct clk rng_ick = {
2347         .name           = "rng_ick",
2348         .parent         = &l4_ck,
2349         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2350         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2351         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
2352         .recalc         = &followparent_recalc,
2353 };
2354
2355 static struct clk aes_ick = {
2356         .name           = "aes_ick",
2357         .parent         = &l4_ck,
2358         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2359         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2360         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
2361         .recalc         = &followparent_recalc,
2362 };
2363
2364 static struct clk pka_ick = {
2365         .name           = "pka_ick",
2366         .parent         = &l4_ck,
2367         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2368         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2369         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
2370         .recalc         = &followparent_recalc,
2371 };
2372
2373 static struct clk usb_fck = {
2374         .name           = "usb_fck",
2375         .parent         = &func_48m_ck,
2376         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2377         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2378         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
2379         .recalc         = &followparent_recalc,
2380 };
2381
2382 static struct clk usbhs_ick = {
2383         .name           = "usbhs_ick",
2384         .parent         = &core_l3_ck,
2385         .flags          = CLOCK_IN_OMAP243X,
2386         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2387         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
2388         .recalc         = &followparent_recalc,
2389 };
2390
2391 static struct clk mmchs1_ick = {
2392         .name           = "mmchs1_ick",
2393         .parent         = &l4_ck,
2394         .flags          = CLOCK_IN_OMAP243X,
2395         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2396         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2397         .recalc         = &followparent_recalc,
2398 };
2399
2400 static struct clk mmchs1_fck = {
2401         .name           = "mmchs1_fck",
2402         .parent         = &func_96m_ck,
2403         .flags          = CLOCK_IN_OMAP243X,
2404         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2405         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2406         .recalc         = &followparent_recalc,
2407 };
2408
2409 static struct clk mmchs2_ick = {
2410         .name           = "mmchs2_ick",
2411         .parent         = &l4_ck,
2412         .flags          = CLOCK_IN_OMAP243X,
2413         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2414         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2415         .recalc         = &followparent_recalc,
2416 };
2417
2418 static struct clk mmchs2_fck = {
2419         .name           = "mmchs2_fck",
2420         .parent         = &func_96m_ck,
2421         .flags          = CLOCK_IN_OMAP243X,
2422         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2423         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2424         .recalc         = &followparent_recalc,
2425 };
2426
2427 static struct clk gpio5_ick = {
2428         .name           = "gpio5_ick",
2429         .parent         = &l4_ck,
2430         .flags          = CLOCK_IN_OMAP243X,
2431         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2432         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2433         .recalc         = &followparent_recalc,
2434 };
2435
2436 static struct clk gpio5_fck = {
2437         .name           = "gpio5_fck",
2438         .parent         = &func_32k_ck,
2439         .flags          = CLOCK_IN_OMAP243X,
2440         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2441         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2442         .recalc         = &followparent_recalc,
2443 };
2444
2445 static struct clk mdm_intc_ick = {
2446         .name           = "mdm_intc_ick",
2447         .parent         = &l4_ck,
2448         .flags          = CLOCK_IN_OMAP243X,
2449         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2450         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
2451         .recalc         = &followparent_recalc,
2452 };
2453
2454 static struct clk mmchsdb1_fck = {
2455         .name           = "mmchsdb1_fck",
2456         .parent         = &func_32k_ck,
2457         .flags          = CLOCK_IN_OMAP243X,
2458         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2459         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
2460         .recalc         = &followparent_recalc,
2461 };
2462
2463 static struct clk mmchsdb2_fck = {
2464         .name           = "mmchsdb2_fck",
2465         .parent         = &func_32k_ck,
2466         .flags          = CLOCK_IN_OMAP243X,
2467         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2468         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
2469         .recalc         = &followparent_recalc,
2470 };
2471
2472 /*
2473  * This clock is a composite clock which does entire set changes then
2474  * forces a rebalance. It keys on the MPU speed, but it really could
2475  * be any key speed part of a set in the rate table.
2476  *
2477  * to really change a set, you need memory table sets which get changed
2478  * in sram, pre-notifiers & post notifiers, changing the top set, without
2479  * having low level display recalc's won't work... this is why dpm notifiers
2480  * work, isr's off, walk a list of clocks already _off_ and not messing with
2481  * the bus.
2482  *
2483  * This clock should have no parent. It embodies the entire upper level
2484  * active set. A parent will mess up some of the init also.
2485  */
2486 static struct clk virt_prcm_set = {
2487         .name           = "virt_prcm_set",
2488         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2489                                 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
2490         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
2491         .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
2492         .set_rate       = &omap2_select_table_rate,
2493         .round_rate     = &omap2_round_to_table_rate,
2494 };
2495
2496 static struct clk *onchip_clks[] __initdata = {
2497         /* external root sources */
2498         &func_32k_ck,
2499         &osc_ck,
2500         &sys_ck,
2501         &alt_ck,
2502         /* internal analog sources */
2503         &dpll_ck,
2504         &apll96_ck,
2505         &apll54_ck,
2506         /* internal prcm root sources */
2507         &func_54m_ck,
2508         &core_ck,
2509         &func_96m_ck,
2510         &func_48m_ck,
2511         &func_12m_ck,
2512         &wdt1_osc_ck,
2513         &sys_clkout_src,
2514         &sys_clkout,
2515         &sys_clkout2_src,
2516         &sys_clkout2,
2517         &emul_ck,
2518         /* mpu domain clocks */
2519         &mpu_ck,
2520         /* dsp domain clocks */
2521         &iva2_1_fck,            /* 2430 */
2522         &iva2_1_ick,
2523         &dsp_ick,               /* 2420 */
2524         &dsp_fck,
2525         &iva1_ifck,
2526         &iva1_mpu_int_ifck,
2527         /* GFX domain clocks */
2528         &gfx_3d_fck,
2529         &gfx_2d_fck,
2530         &gfx_ick,
2531         /* Modem domain clocks */
2532         &mdm_ick,
2533         &mdm_osc_ck,
2534         /* DSS domain clocks */
2535         &dss_ick,
2536         &dss1_fck,
2537         &dss2_fck,
2538         &dss_54m_fck,
2539         /* L3 domain clocks */
2540         &core_l3_ck,
2541         &ssi_ssr_sst_fck,
2542         &usb_l4_ick,
2543         /* L4 domain clocks */
2544         &l4_ck,                 /* used as both core_l4 and wu_l4 */
2545         &ssi_l4_ick,
2546         /* virtual meta-group clock */
2547         &virt_prcm_set,
2548         /* general l4 interface ck, multi-parent functional clk */
2549         &gpt1_ick,
2550         &gpt1_fck,
2551         &gpt2_ick,
2552         &gpt2_fck,
2553         &gpt3_ick,
2554         &gpt3_fck,
2555         &gpt4_ick,
2556         &gpt4_fck,
2557         &gpt5_ick,
2558         &gpt5_fck,
2559         &gpt6_ick,
2560         &gpt6_fck,
2561         &gpt7_ick,
2562         &gpt7_fck,
2563         &gpt8_ick,
2564         &gpt8_fck,
2565         &gpt9_ick,
2566         &gpt9_fck,
2567         &gpt10_ick,
2568         &gpt10_fck,
2569         &gpt11_ick,
2570         &gpt11_fck,
2571         &gpt12_ick,
2572         &gpt12_fck,
2573         &mcbsp1_ick,
2574         &mcbsp1_fck,
2575         &mcbsp2_ick,
2576         &mcbsp2_fck,
2577         &mcbsp3_ick,
2578         &mcbsp3_fck,
2579         &mcbsp4_ick,
2580         &mcbsp4_fck,
2581         &mcbsp5_ick,
2582         &mcbsp5_fck,
2583         &mcspi1_ick,
2584         &mcspi1_fck,
2585         &mcspi2_ick,
2586         &mcspi2_fck,
2587         &mcspi3_ick,
2588         &mcspi3_fck,
2589         &uart1_ick,
2590         &uart1_fck,
2591         &uart2_ick,
2592         &uart2_fck,
2593         &uart3_ick,
2594         &uart3_fck,
2595         &gpios_ick,
2596         &gpios_fck,
2597         &mpu_wdt_ick,
2598         &mpu_wdt_fck,
2599         &sync_32k_ick,
2600         &wdt1_ick,
2601         &omapctrl_ick,
2602         &icr_ick,
2603         &cam_fck,
2604         &cam_ick,
2605         &mailboxes_ick,
2606         &wdt4_ick,
2607         &wdt4_fck,
2608         &wdt3_ick,
2609         &wdt3_fck,
2610         &mspro_ick,
2611         &mspro_fck,
2612         &mmc_ick,
2613         &mmc_fck,
2614         &fac_ick,
2615         &fac_fck,
2616         &eac_ick,
2617         &eac_fck,
2618         &hdq_ick,
2619         &hdq_fck,
2620         &i2c1_ick,
2621         &i2c1_fck,
2622         &i2chs1_fck,
2623         &i2c2_ick,
2624         &i2c2_fck,
2625         &i2chs2_fck,
2626         &vlynq_ick,
2627         &vlynq_fck,
2628         &sdrc_ick,
2629         &des_ick,
2630         &sha_ick,
2631         &rng_ick,
2632         &aes_ick,
2633         &pka_ick,
2634         &usb_fck,
2635         &usbhs_ick,
2636         &mmchs1_ick,
2637         &mmchs1_fck,
2638         &mmchs2_ick,
2639         &mmchs2_fck,
2640         &gpio5_ick,
2641         &gpio5_fck,
2642         &mdm_intc_ick,
2643         &mmchsdb1_fck,
2644         &mmchsdb2_fck,
2645 };
2646
2647 #endif