arch/arm/mach-omap2/clock.h

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock.h
   3  *
   4  *  Copyright (C) 2005 Texas Instruments Inc.
   5  *  Richard Woodruff <r-woodruff2@ti.com>
   6  *  Created for OMAP2.
   7  *
   8  *  Copyright (C) 2004 Nokia corporation
   9  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  10  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
  11  *
  12  *  Copyright (C) 2007 Texas Instruments, Inc.
  13  *  Copyright (C) 2007 Nokia Corporation
  14  *  Paul Walmsley
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
  22 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
  23
  24 #include "prm.h"
  25 #include "cm.h"
  26 #include "prm_regbits_24xx.h"
  27 #include "cm_regbits_24xx.h"
  28
  29 static void omap2_sys_clk_recalc(struct clk * clk);
  30 static void omap2_clksel_recalc(struct clk * clk);
  31 static void omap2_table_mpu_recalc(struct clk *clk);
  32 static int omap2_select_table_rate(struct clk * clk, unsigned long rate);
  33 static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate);
  34 static void omap2_clk_disable(struct clk *clk);
  35 static void omap2_sys_clk_recalc(struct clk * clk);
  36 static void omap2_init_clksel_parent(struct clk *clk);
  37 static u32 omap2_clksel_get_divisor(struct clk *clk);
  38 static u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val);
  39 static u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
  40 static void omap2_dpll_recalc(struct clk *clk);
  41 static void omap2_fixed_divisor_recalc(struct clk *clk);
  42 static long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
  43 static int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
  44 static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate);
  45
  46 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  47  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  48  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  49  */
  50 struct prcm_config {
  51         unsigned long xtal_speed;       /* crystal rate */
  52         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  53         unsigned long mpu_speed;        /* speed of MPU */
  54         unsigned long cm_clksel_mpu;    /* mpu divider */
  55         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  56         unsigned long cm_clksel_gfx;    /* gfx dividers */
  57         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  58         unsigned long cm_clksel1_pll;   /* m,n */
  59         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  60         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  61         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  62         unsigned char flags;
  63 };
  64
  65 /* REVISIT: CM_PLL_SEL2 unused */
  66
  67 /* Mask for clksel which support parent settign in set_rate */
  68 #define SRC_SEL_MASK (CM_CORE_SEL1 | CM_CORE_SEL2 | CM_WKUP_SEL1 | \
  69                         CM_PLL_SEL1 | CM_PLL_SEL2 | CM_SYSCLKOUT_SEL1)
  70
  71 /* Mask for clksel regs which support rate operations */
  72 #define SRC_RATE_SEL_MASK (SRC_SEL_MASK | CM_MPU_SEL1 | CM_DSP_SEL1 | \
  73                         CM_GFX_SEL1 | CM_MODEM_SEL1)
  74
  75 /*
  76  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  77  * These configurations are characterized by voltage and speed for clocks.
  78  * The device is only validated for certain combinations. One way to express
  79  * these combinations is via the 'ratio's' which the clocks operate with
  80  * respect to each other. These ratio sets are for a given voltage/DPLL
  81  * setting. All configurations can be described by a DPLL setting and a ratio
  82  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  83  *
  84  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  85  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  86  * 2430 (iva2.1, NOdsp, mdm)
  87  */
  88
  89 /* Core fields for cm_clksel, not ratio governed */
  90 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  91 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  92 #define RX_CLKSEL_SSI                   (0x5 << 20)
  93
  94 /*-------------------------------------------------------------------------
  95  * Voltage/DPLL ratios
  96  *-------------------------------------------------------------------------*/
  97
  98 /* 2430 Ratio's, 2430-Ratio Config 1 */
  99 #define R1_CLKSEL_L3                    (4 << 0)
 100 #define R1_CLKSEL_L4                    (2 << 5)
 101 #define R1_CLKSEL_USB                   (4 << 25)
 102 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
 103                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 104                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
 105 #define R1_CLKSEL_MPU                   (2 << 0)
 106 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
 107 #define R1_CLKSEL_DSP                   (2 << 0)
 108 #define R1_CLKSEL_DSP_IF                (2 << 5)
 109 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
 110 #define R1_CLKSEL_GFX                   (2 << 0)
 111 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
 112 #define R1_CLKSEL_MDM                   (4 << 0)
 113 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
 114
 115 /* 2430-Ratio Config 2 */
 116 #define R2_CLKSEL_L3                    (6 << 0)
 117 #define R2_CLKSEL_L4                    (2 << 5)
 118 #define R2_CLKSEL_USB                   (2 << 25)
 119 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
 120                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 121                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
 122 #define R2_CLKSEL_MPU                   (2 << 0)
 123 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 124 #define R2_CLKSEL_DSP                   (2 << 0)
 125 #define R2_CLKSEL_DSP_IF                (3 << 5)
 126 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 127 #define R2_CLKSEL_GFX                   (2 << 0)
 128 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 129 #define R2_CLKSEL_MDM                   (6 << 0)
 130 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 131
 132 /* 2430-Ratio Bootm (BYPASS) */
 133 #define RB_CLKSEL_L3                    (1 << 0)
 134 #define RB_CLKSEL_L4                    (1 << 5)
 135 #define RB_CLKSEL_USB                   (1 << 25)
 136 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 137                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 138                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 139 #define RB_CLKSEL_MPU                   (1 << 0)
 140 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 141 #define RB_CLKSEL_DSP                   (1 << 0)
 142 #define RB_CLKSEL_DSP_IF                (1 << 5)
 143 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 144 #define RB_CLKSEL_GFX                   (1 << 0)
 145 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 146 #define RB_CLKSEL_MDM                   (1 << 0)
 147 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 148
 149 /* 2420 Ratio Equivalents */
 150 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 151 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 152
 153 /* 2420-PRCM III 532MHz core */
 154 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 155 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 156 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 157 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 158                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 159                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 160                                         RIII_CLKSEL_L3
 161 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 162 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 163 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 164 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 165 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 166 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 167 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 168 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 169                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 170                                         RIII_CLKSEL_DSP
 171 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 172 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 173
 174 /* 2420-PRCM II 600MHz core */
 175 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 176 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 177 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 178 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 179                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 180                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 181                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 182 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 183 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 184 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 185 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 186 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 187 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 188 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 189 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 190                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 191                                         RII_CLKSEL_DSP
 192 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 193 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 194
 195 /* 2420-PRCM I 660MHz core */
 196 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 197 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 198 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 199 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 200                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 201                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 202                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 203 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 204 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 205 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 206 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 207 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 208 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 209 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 210 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 211                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 212                                         RI_CLKSEL_DSP
 213 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 214 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 215
 216 /* 2420-PRCM VII (boot) */
 217 #define RVII_CLKSEL_L3                  (1 << 0)
 218 #define RVII_CLKSEL_L4                  (1 << 5)
 219 #define RVII_CLKSEL_DSS1                (1 << 8)
 220 #define RVII_CLKSEL_DSS2                (0 << 13)
 221 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 222 #define RVII_CLKSEL_SSI                 (1 << 20)
 223 #define RVII_CLKSEL_USB                 (1 << 25)
 224
 225 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 226                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 227                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 228
 229 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 230 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 231
 232 #define RVII_CLKSEL_DSP                 (1 << 0)
 233 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 234 #define RVII_SYNC_DSP                   (0 << 7)
 235 #define RVII_CLKSEL_IVA                 (1 << 8)
 236 #define RVII_SYNC_IVA                   (0 << 13)
 237 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 238                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 239
 240 #define RVII_CLKSEL_GFX                 (1 << 0)
 241 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 242
 243 /*-------------------------------------------------------------------------
 244  * 2430 Target modes: Along with each configuration the CPU has several
 245  * modes which goes along with them. Modes mainly are the addition of
 246  * describe DPLL combinations to go along with a ratio.
 247  *-------------------------------------------------------------------------*/
 248
 249 /* Hardware governed */
 250 #define MX_48M_SRC                      (0 << 3)
 251 #define MX_54M_SRC                      (0 << 5)
 252 #define MX_APLLS_CLIKIN_12              (3 << 23)
 253 #define MX_APLLS_CLIKIN_13              (2 << 23)
 254 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 255
 256 /*
 257  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 258  * #2   (ratio1) baseport-target
 259  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 260  */
 261 #define M5A_DPLL_MULT_12                (133 << 12)
 262 #define M5A_DPLL_DIV_12                 (5 << 8)
 263 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 264                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 265                                         MX_APLLS_CLIKIN_12
 266 #define M5A_DPLL_MULT_13                (266 << 12)
 267 #define M5A_DPLL_DIV_13                 (12 << 8)
 268 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 269                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 270                                         MX_APLLS_CLIKIN_13
 271 #define M5A_DPLL_MULT_19                (180 << 12)
 272 #define M5A_DPLL_DIV_19                 (12 << 8)
 273 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 274                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 275                                         MX_APLLS_CLIKIN_19_2
 276 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 277 #define M5B_DPLL_MULT_12                (50 << 12)
 278 #define M5B_DPLL_DIV_12                 (2 << 8)
 279 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 280                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 281                                         MX_APLLS_CLIKIN_12
 282 #define M5B_DPLL_MULT_13                (200 << 12)
 283 #define M5B_DPLL_DIV_13                 (12 << 8)
 284
 285 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 286                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 287                                         MX_APLLS_CLIKIN_13
 288 #define M5B_DPLL_MULT_19                (125 << 12)
 289 #define M5B_DPLL_DIV_19                 (31 << 8)
 290 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 291                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 292                                         MX_APLLS_CLIKIN_19_2
 293 /*
 294  * #4   (ratio2)
 295  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 296  */
 297 #define M3_DPLL_MULT_12                 (55 << 12)
 298 #define M3_DPLL_DIV_12                  (1 << 8)
 299 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 300                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 301                                         MX_APLLS_CLIKIN_12
 302 #define M3_DPLL_MULT_13                 (330 << 12)
 303 #define M3_DPLL_DIV_13                  (12 << 8)
 304 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 305                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 306                                         MX_APLLS_CLIKIN_13
 307 #define M3_DPLL_MULT_19                 (275 << 12)
 308 #define M3_DPLL_DIV_19                  (15 << 8)
 309 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 310                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 311                                         MX_APLLS_CLIKIN_19_2
 312 /* boot (boot) */
 313 #define MB_DPLL_MULT                    (1 << 12)
 314 #define MB_DPLL_DIV                     (0 << 8)
 315 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 316                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 317
 318 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 319                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 320
 321 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 322                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 323
 324 /*
 325  * 2430 - chassis (sedna)
 326  * 165 (ratio1) same as above #2
 327  * 150 (ratio1)
 328  * 133 (ratio2) same as above #4
 329  * 110 (ratio2) same as above #3
 330  * 104 (ratio2)
 331  * boot (boot)
 332  */
 333
 334 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 335 #define MI_DPLL_MULT_12                 (55 << 12)
 336 #define MI_DPLL_DIV_12                  (1 << 8)
 337 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 338                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 339                                         MX_APLLS_CLIKIN_12
 340
 341 /*
 342  * 2420 Equivalent - mode registers
 343  * PRCM II , target DPLL = 2*300MHz = 600MHz
 344  */
 345 #define MII_DPLL_MULT_12                (50 << 12)
 346 #define MII_DPLL_DIV_12                 (1 << 8)
 347 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 348                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 349                                         MX_APLLS_CLIKIN_12
 350 #define MII_DPLL_MULT_13                (300 << 12)
 351 #define MII_DPLL_DIV_13                 (12 << 8)
 352 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 353                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 354                                         MX_APLLS_CLIKIN_13
 355
 356 /* PRCM III target DPLL = 2*266 = 532MHz*/
 357 #define MIII_DPLL_MULT_12               (133 << 12)
 358 #define MIII_DPLL_DIV_12                (5 << 8)
 359 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 360                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 361                                         MX_APLLS_CLIKIN_12
 362 #define MIII_DPLL_MULT_13               (266 << 12)
 363 #define MIII_DPLL_DIV_13                (12 << 8)
 364 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 365                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 366                                         MX_APLLS_CLIKIN_13
 367
 368 /* PRCM VII (boot bypass) */
 369 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 370 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 371
 372 /* High and low operation value */
 373 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 374 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 375
 376 /*
 377  * These represent optimal values for common parts, it won't work for all.
 378  * As long as you scale down, most parameters are still work, they just
 379  * become sub-optimal. The RFR value goes in the opposite direction. If you
 380  * don't adjust it down as your clock period increases the refresh interval
 381  * will not be met. Setting all parameters for complete worst case may work,
 382  * but may cut memory performance by 2x. Due to errata the DLLs need to be
 383  * unlocked and their value needs run time calibration. A dynamic call is
 384  * need for that as no single right value exists acorss production samples.
 385  *
 386  * Only the FULL speed values are given. Current code is such that rate
 387  * changes must be made at DPLLoutx2. The actual value adjustment for low
 388  * frequency operation will be handled by omap_set_performance()
 389  *
 390  * By having the boot loader boot up in the fastest L4 speed available likely
 391  * will result in something which you can switch between.
 392  */
 393 #define V24XX_SDRC_RFR_CTRL_165MHz      (0x00044c00 | 1)
 394 #define V24XX_SDRC_RFR_CTRL_133MHz      (0x0003de00 | 1)
 395 #define V24XX_SDRC_RFR_CTRL_100MHz      (0x0002da01 | 1)
 396 #define V24XX_SDRC_RFR_CTRL_110MHz      (0x0002da01 | 1) /* Need to calc */
 397 #define V24XX_SDRC_RFR_CTRL_BYPASS      (0x00005000 | 1) /* Need to calc */
 398
 399 /* MPU speed defines */
 400 #define S12M    12000000
 401 #define S13M    13000000
 402 #define S19M    19200000
 403 #define S26M    26000000
 404 #define S100M   100000000
 405 #define S133M   133000000
 406 #define S150M   150000000
 407 #define S165M   165000000
 408 #define S200M   200000000
 409 #define S266M   266000000
 410 #define S300M   300000000
 411 #define S330M   330000000
 412 #define S400M   400000000
 413 #define S532M   532000000
 414 #define S600M   600000000
 415 #define S660M   660000000
 416
 417 /*-------------------------------------------------------------------------
 418  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 419  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 420  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 421  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 422  *
 423  * Filling in table based on H4 boards and 2430-SDPs variants available.
 424  * There are quite a few more rates combinations which could be defined.
 425  *
 426  * When multiple values are defined the start up will try and choose the
 427  * fastest one. If a 'fast' value is defined, then automatically, the /2
 428  * one should be included as it can be used.    Generally having more that
 429  * one fast set does not make sense, as static timings need to be changed
 430  * to change the set.    The exception is the bypass setting which is
 431  * availble for low power bypass.
 432  *
 433  * Note: This table needs to be sorted, fastest to slowest.
 434  *-------------------------------------------------------------------------*/
 435 static struct prcm_config rate_table[] = {
 436         /* PRCM I - FAST */
 437         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 438                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 439                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 440                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_165MHz,
 441                 RATE_IN_242X},
 442
 443         /* PRCM II - FAST */
 444         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 445                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 446                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 447                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 448                 RATE_IN_242X},
 449
 450         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 451                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 452                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 453                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 454                 RATE_IN_242X},
 455
 456         /* PRCM III - FAST */
 457         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 458                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 459                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 460                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 461                 RATE_IN_242X},
 462
 463         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 464                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 465                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 466                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 467                 RATE_IN_242X},
 468
 469         /* PRCM II - SLOW */
 470         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 471                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 472                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 473                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 474                 RATE_IN_242X},
 475
 476         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 477                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 478                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 479                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 480                 RATE_IN_242X},
 481
 482         /* PRCM III - SLOW */
 483         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 484                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 485                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 486                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 487                 RATE_IN_242X},
 488
 489         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 490                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 491                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 492                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 493                 RATE_IN_242X},
 494
 495         /* PRCM-VII (boot-bypass) */
 496         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 497                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 498                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 499                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
 500                 RATE_IN_242X},
 501
 502         /* PRCM-VII (boot-bypass) */
 503         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 504                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 505                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 506                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
 507                 RATE_IN_242X},
 508
 509         /* PRCM #3 - ratio2 (ES2) - FAST */
 510         {S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 511                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 512                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 513                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 514                 V24XX_SDRC_RFR_CTRL_110MHz,
 515                 RATE_IN_243X},
 516
 517         /* PRCM #5a - ratio1 - FAST */
 518         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 519                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 520                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 521                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 522                 V24XX_SDRC_RFR_CTRL_133MHz,
 523                 RATE_IN_243X},
 524
 525         /* PRCM #5b - ratio1 - FAST */
 526         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 527                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 528                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 529                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 530                 V24XX_SDRC_RFR_CTRL_100MHz,
 531                 RATE_IN_243X},
 532
 533         /* PRCM #3 - ratio2 (ES2) - SLOW */
 534         {S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 535                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 536                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 537                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 538                 V24XX_SDRC_RFR_CTRL_110MHz,
 539                 RATE_IN_243X},
 540
 541         /* PRCM #5a - ratio1 - SLOW */
 542         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 543                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 544                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 545                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 546                 V24XX_SDRC_RFR_CTRL_133MHz,
 547                 RATE_IN_243X},
 548
 549         /* PRCM #5b - ratio1 - SLOW*/
 550         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 551                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 552                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 553                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 554                 V24XX_SDRC_RFR_CTRL_100MHz,
 555                 RATE_IN_243X},
 556
 557         /* PRCM-boot/bypass */
 558         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 559                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 560                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 561                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 562                 V24XX_SDRC_RFR_CTRL_BYPASS,
 563                 RATE_IN_243X},
 564
 565         /* PRCM-boot/bypass */
 566         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 567                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 568                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 569                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 570                 V24XX_SDRC_RFR_CTRL_BYPASS,
 571                 RATE_IN_243X},
 572
 573         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 574 };
 575
 576 /*-------------------------------------------------------------------------
 577  * 24xx clock tree.
 578  *
 579  * NOTE:In many cases here we are assigning a 'default' parent. In many
 580  *      cases the parent is selectable. The get/set parent calls will also
 581  *      switch sources.
 582  *
 583  *      Many some clocks say always_enabled, but they can be auto idled for
 584  *      power savings. They will always be available upon clock request.
 585  *
 586  *      Several sources are given initial rates which may be wrong, this will
 587  *      be fixed up in the init func.
 588  *
 589  *      Things are broadly separated below by clock domains. It is
 590  *      noteworthy that most periferals have dependencies on multiple clock
 591  *      domains. Many get their interface clocks from the L4 domain, but get
 592  *      functional clocks from fixed sources or other core domain derived
 593  *      clocks.
 594  *-------------------------------------------------------------------------*/
 595
 596 /* Base external input clocks */
 597 static struct clk func_32k_ck = {
 598         .name           = "func_32k_ck",
 599         .rate           = 32000,
 600         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 601                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 602         .recalc         = &propagate_rate,
 603 };
 604
 605 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 606 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 607         .name           = "osc_ck",
 608         .rate           = 26000000,             /* fixed up in clock init */
 609         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 610                                 RATE_FIXED | RATE_PROPAGATES,
 611         .recalc         = &propagate_rate,
 612 };
 613
 614 /* With out modem likely 12MHz, with modem likely 13MHz */
 615 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 616         .name           = "sys_ck",             /* ~ ref_clk also */
 617         .parent         = &osc_ck,
 618         .rate           = 13000000,
 619         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 620                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 621         .recalc         = &omap2_sys_clk_recalc,
 622 };
 623
 624 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 625         .name           = "alt_ck",
 626         .rate           = 54000000,
 627         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 628                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 629         .recalc         = &propagate_rate,
 630 };
 631
 632 /*
 633  * Analog domain root source clocks
 634  */
 635
 636 /* dpll_ck, is broken out in to special cases through clksel */
 637 /* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
 638  * deal with this
 639  */
 640 static struct clk dpll_ck = {
 641         .name           = "dpll_ck",
 642         .parent         = &sys_ck,              /* Can be func_32k also */
 643         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 644                                 RATE_PROPAGATES | CM_PLL_SEL1 | ALWAYS_ENABLED,
 645         .recalc         = &omap2_dpll_recalc,
 646         .set_rate       = &omap2_reprogram_dpll,
 647 };
 648
 649 static struct clk apll96_ck = {
 650         .name           = "apll96_ck",
 651         .parent         = &sys_ck,
 652         .rate           = 96000000,
 653         .flags          = CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X |
 654                                 RATE_FIXED | RATE_PROPAGATES,
 655         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 656         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 657         .recalc         = &propagate_rate,
 658 };
 659
 660 static struct clk apll54_ck = {
 661         .name           = "apll54_ck",
 662         .parent         = &sys_ck,
 663         .rate           = 54000000,
 664         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 665                                 RATE_FIXED | RATE_PROPAGATES,
 666         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 667         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 668         .recalc         = &propagate_rate,
 669 };
 670
 671 /*
 672  * PRCM digital base sources
 673  */
 674
 675 /* func_54m_ck */
 676
 677 static const struct clksel_rate func_54m_apll54_rates[] = {
 678         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 679         { .div = 0 },
 680 };
 681
 682 static const struct clksel_rate func_54m_alt_rates[] = {
 683         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 684         { .div = 0 },
 685 };
 686
 687 static const struct clksel func_54m_clksel[] = {
 688         { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
 689         { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
 690         { .parent = NULL },
 691 };
 692
 693 static struct clk func_54m_ck = {
 694         .name           = "func_54m_ck",
 695         .parent         = &apll54_ck,   /* can also be alt_clk */
 696         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 697                                 CM_PLL_SEL1 | RATE_PROPAGATES |
 698                                 PARENT_CONTROLS_CLOCK,
 699         .init           = &omap2_init_clksel_parent,
 700         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 701         .clksel_mask    = OMAP24XX_54M_SOURCE,
 702         .clksel         = func_54m_clksel,
 703         .recalc         = &omap2_clksel_recalc,
 704 };
 705
 706 static struct clk core_ck = {
 707         .name           = "core_ck",
 708         .parent         = &dpll_ck,             /* can also be 32k */
 709         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 710                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 711         .recalc         = &followparent_recalc,
 712 };
 713
 714 /* func_96m_ck */
 715 static const struct clksel_rate func_96m_apll96_rates[] = {
 716         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 717         { .div = 0 },
 718 };
 719
 720 static const struct clksel_rate func_96m_alt_rates[] = {
 721         { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
 722         { .div = 0 },
 723 };
 724
 725 static const struct clksel func_96m_clksel[] = {
 726         { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
 727         { .parent = &alt_ck,    .rates = func_96m_alt_rates },
 728         { .parent = NULL }
 729 };
 730
 731 /* The parent of this clock is not selectable on 2420. */
 732 static struct clk func_96m_ck = {
 733         .name           = "func_96m_ck",
 734         .parent         = &apll96_ck,
 735         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 736                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 737         .init           = &omap2_init_clksel_parent,
 738         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 739         .clksel_mask    = OMAP2430_96M_SOURCE,
 740         .clksel         = func_96m_clksel,
 741         .recalc         = &omap2_clksel_recalc,
 742         .round_rate     = &omap2_clksel_round_rate,
 743         .set_rate       = &omap2_clksel_set_rate
 744 };
 745
 746 /* func_48m_ck */
 747
 748 static const struct clksel_rate func_48m_apll96_rates[] = {
 749         { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 750         { .div = 0 },
 751 };
 752
 753 static const struct clksel_rate func_48m_alt_rates[] = {
 754         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 755         { .div = 0 },
 756 };
 757
 758 static const struct clksel func_48m_clksel[] = {
 759         { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
 760         { .parent = &alt_ck, .rates = func_48m_alt_rates },
 761         { .parent = NULL }
 762 };
 763
 764 static struct clk func_48m_ck = {
 765         .name           = "func_48m_ck",
 766         .parent         = &apll96_ck,    /* 96M or Alt */
 767         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 768                                 CM_PLL_SEL1 | RATE_PROPAGATES |
 769                                 PARENT_CONTROLS_CLOCK,
 770         .init           = &omap2_init_clksel_parent,
 771         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 772         .clksel_mask    = OMAP24XX_48M_SOURCE,
 773         .clksel         = func_48m_clksel,
 774         .recalc         = &omap2_clksel_recalc,
 775         .round_rate     = &omap2_clksel_round_rate,
 776         .set_rate       = &omap2_clksel_set_rate
 777 };
 778
 779 static struct clk func_12m_ck = {
 780         .name           = "func_12m_ck",
 781         .parent         = &func_48m_ck,
 782         .fixed_div      = 4,
 783         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 784                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 785         .recalc         = &omap2_fixed_divisor_recalc,
 786 };
 787
 788 /* Secure timer, only available in secure mode */
 789 static struct clk wdt1_osc_ck = {
 790         .name           = "ck_wdt1_osc",
 791         .parent         = &osc_ck,
 792         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 793         .recalc         = &followparent_recalc,
 794 };
 795
 796 /*
 797  * The common_clkout* clksel_rate structs are common to
 798  * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
 799  * sys_clkout2_* are 2420-only, so the
 800  * clksel_rate flags fields are inaccurate for those clocks. This is
 801  * harmless since access to those clocks are gated by the struct clk
 802  * flags fields, which mark them as 2420-only.
 803  */
 804 static const struct clksel_rate common_clkout_src_core_rates[] = {
 805         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 806         { .div = 0 }
 807 };
 808
 809 static const struct clksel_rate common_clkout_src_sys_rates[] = {
 810         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 811         { .div = 0 }
 812 };
 813
 814 static const struct clksel_rate common_clkout_src_96m_rates[] = {
 815         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 816         { .div = 0 }
 817 };
 818
 819 static const struct clksel_rate common_clkout_src_54m_rates[] = {
 820         { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
 821         { .div = 0 }
 822 };
 823
 824 static const struct clksel common_clkout_src_clksel[] = {
 825         { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
 826         { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
 827         { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
 828         { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
 829         { .parent = NULL }
 830 };
 831
 832 static struct clk sys_clkout_src = {
 833         .name           = "sys_clkout_src",
 834         .parent         = &func_54m_ck,
 835         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 836                                 CM_SYSCLKOUT_SEL1 | RATE_PROPAGATES,
 837         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 838         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 839         .init           = &omap2_init_clksel_parent,
 840         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 841         .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
 842         .clksel         = common_clkout_src_clksel,
 843         .recalc         = &omap2_clksel_recalc,
 844         .round_rate     = &omap2_clksel_round_rate,
 845         .set_rate       = &omap2_clksel_set_rate
 846 };
 847
 848 static const struct clksel_rate common_clkout_rates[] = {
 849         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 850         { .div = 2, .val = 1, .flags = RATE_IN_24XX },
 851         { .div = 4, .val = 2, .flags = RATE_IN_24XX },
 852         { .div = 8, .val = 3, .flags = RATE_IN_24XX },
 853         { .div = 16, .val = 4, .flags = RATE_IN_24XX },
 854         { .div = 0 },
 855 };
 856
 857 static const struct clksel sys_clkout_clksel[] = {
 858         { .parent = &sys_clkout_src, .rates = common_clkout_rates },
 859         { .parent = NULL }
 860 };
 861
 862 static struct clk sys_clkout = {
 863         .name           = "sys_clkout",
 864         .parent         = &sys_clkout_src,
 865         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 866                                 CM_SYSCLKOUT_SEL1 | PARENT_CONTROLS_CLOCK,
 867         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 868         .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
 869         .clksel         = sys_clkout_clksel,
 870         .recalc         = &omap2_clksel_recalc,
 871         .round_rate     = &omap2_clksel_round_rate,
 872         .set_rate       = &omap2_clksel_set_rate
 873 };
 874
 875 /* In 2430, new in 2420 ES2 */
 876 static struct clk sys_clkout2_src = {
 877         .name           = "sys_clkout2_src",
 878         .parent         = &func_54m_ck,
 879         .flags          = CLOCK_IN_OMAP242X | CM_SYSCLKOUT_SEL1 |
 880                                 RATE_PROPAGATES,
 881         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 882         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 883         .init           = &omap2_init_clksel_parent,
 884         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 885         .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
 886         .clksel         = common_clkout_src_clksel,
 887         .recalc         = &omap2_clksel_recalc,
 888         .round_rate     = &omap2_clksel_round_rate,
 889         .set_rate       = &omap2_clksel_set_rate
 890 };
 891
 892 static const struct clksel sys_clkout2_clksel[] = {
 893         { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
 894         { .parent = NULL }
 895 };
 896
 897 /* In 2430, new in 2420 ES2 */
 898 static struct clk sys_clkout2 = {
 899         .name           = "sys_clkout2",
 900         .parent         = &sys_clkout2_src,
 901         .flags          = CLOCK_IN_OMAP242X | CM_SYSCLKOUT_SEL1 |
 902                                 PARENT_CONTROLS_CLOCK,
 903         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 904         .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
 905         .clksel         = sys_clkout2_clksel,
 906         .recalc         = &omap2_clksel_recalc,
 907         .round_rate     = &omap2_clksel_round_rate,
 908         .set_rate       = &omap2_clksel_set_rate
 909 };
 910
 911 static struct clk emul_ck = {
 912         .name           = "emul_ck",
 913         .parent         = &func_54m_ck,
 914         .flags          = CLOCK_IN_OMAP242X,
 915         .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL,
 916         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 917         .recalc         = &followparent_recalc,
 918
 919 };
 920
 921 /*
 922  * MPU clock domain
 923  *      Clocks:
 924  *              MPU_FCLK, MPU_ICLK
 925  *              INT_M_FCLK, INT_M_I_CLK
 926  *
 927  * - Individual clocks are hardware managed.
 928  * - Base divider comes from: CM_CLKSEL_MPU
 929  *
 930  */
 931 static const struct clksel_rate mpu_core_rates[] = {
 932         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 933         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 934         { .div = 4, .val = 4, .flags = RATE_IN_242X },
 935         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 936         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 937         { .div = 0 },
 938 };
 939
 940 static const struct clksel mpu_clksel[] = {
 941         { .parent = &core_ck, .rates = mpu_core_rates },
 942         { .parent = NULL }
 943 };
 944
 945 static struct clk mpu_ck = {    /* Control cpu */
 946         .name           = "mpu_ck",
 947         .parent         = &core_ck,
 948         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 949                                 ALWAYS_ENABLED | CM_MPU_SEL1 | DELAYED_APP |
 950                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
 951         .init           = &omap2_init_clksel_parent,
 952         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
 953         .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
 954         .clksel         = mpu_clksel,
 955         .recalc         = &omap2_clksel_recalc,
 956         .round_rate     = &omap2_clksel_round_rate,
 957         .set_rate       = &omap2_clksel_set_rate
 958 };
 959
 960 /*
 961  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
 962  * Clocks:
 963  *      2430: IVA2.1_FCLK, IVA2.1_ICLK
 964  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
 965  */
 966 /* XXX Okay, this is dumb.  iva2_1fck and dsp_fck are the same clock.
 967  * they should just be treated as such.
 968  */
 969
 970 /* iva2_1_fck */
 971 static const struct clksel_rate iva2_1_fck_core_rates[] = {
 972         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 973         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 974         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
 975         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
 976         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 977         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 978         { .div = 12, .val = 12, .flags = RATE_IN_242X },
 979         { .div = 0 },
 980 };
 981
 982 static const struct clksel iva2_1_fck_clksel[] = {
 983         { .parent = &core_ck, .rates = iva2_1_fck_core_rates },
 984         { .parent = NULL }
 985 };
 986
 987 static struct clk iva2_1_fck = {
 988         .name           = "iva2_1_fck",
 989         .parent         = &core_ck,
 990         .flags          = CLOCK_IN_OMAP243X | CM_DSP_SEL1 |
 991                                 DELAYED_APP | RATE_PROPAGATES |
 992                                 CONFIG_PARTICIPANT,
 993         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 994         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
 995         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
 996         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
 997         .clksel         = iva2_1_fck_clksel,
 998         .recalc         = &omap2_clksel_recalc,
 999         .round_rate     = &omap2_clksel_round_rate,
1000         .set_rate       = &omap2_clksel_set_rate
1001 };
1002
1003 /* iva2_1_ick */
1004 static const struct clksel_rate iva2_1_ick_core_rates[] = {
1005         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1006         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1007         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1008         { .div = 0 },
1009 };
1010
1011 static const struct clksel iva2_1_ick_clksel[] = {
1012         { .parent = &core_ck, .rates = iva2_1_ick_core_rates },
1013         { .parent = NULL }
1014 };
1015
1016 static struct clk iva2_1_ick = {
1017         .name           = "iva2_1_ick",
1018         .parent         = &iva2_1_fck,
1019         .flags          = CLOCK_IN_OMAP243X | CM_DSP_SEL1 |
1020                                 DELAYED_APP | CONFIG_PARTICIPANT,
1021         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1022         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1023         .clksel         = iva2_1_ick_clksel,
1024         .recalc         = &omap2_clksel_recalc,
1025         .round_rate     = &omap2_clksel_round_rate,
1026         .set_rate       = &omap2_clksel_set_rate
1027 };
1028
1029 /*
1030  * Won't be too specific here. The core clock comes into this block
1031  * it is divided then tee'ed. One branch goes directly to xyz enable
1032  * controls. The other branch gets further divided by 2 then possibly
1033  * routed into a synchronizer and out of clocks abc.
1034  */
1035 static const struct clksel_rate dsp_fck_core_rates[] = {
1036         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1037         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1038         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1039         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1040         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1041         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1042         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1043         { .div = 0 },
1044 };
1045
1046 static const struct clksel dsp_fck_clksel[] = {
1047         { .parent = &core_ck, .rates = dsp_fck_core_rates },
1048         { .parent = NULL }
1049 };
1050
1051 static struct clk dsp_fck = {
1052         .name           = "dsp_fck",
1053         .parent         = &core_ck,
1054         .flags          = CLOCK_IN_OMAP242X | CM_DSP_SEL1 |
1055                         DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
1056         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
1057         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1058         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1059         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
1060         .clksel         = dsp_fck_clksel,
1061         .recalc         = &omap2_clksel_recalc,
1062         .round_rate     = &omap2_clksel_round_rate,
1063         .set_rate       = &omap2_clksel_set_rate
1064 };
1065
1066 static const struct clksel_rate dsp_ick_core_rates[] = {
1067         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1068         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1069         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1070         { .div = 0 },
1071 };
1072
1073 static const struct clksel dsp_ick_clksel[] = {
1074         { .parent = &core_ck, .rates = dsp_ick_core_rates },
1075         { .parent = NULL }
1076 };
1077
1078 static struct clk dsp_ick = {
1079         .name           = "dsp_ick",     /* apparently ipi and isp */
1080         .parent         = &core_ck,
1081         .flags          = CLOCK_IN_OMAP242X | CM_DSP_SEL1 |
1082                                 DELAYED_APP | CONFIG_PARTICIPANT,
1083         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
1084         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,            /* for ipi */
1085         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1086         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1087         .clksel         = dsp_ick_clksel,
1088         .recalc         = &omap2_clksel_recalc,
1089 };
1090
1091 static const struct clksel_rate iva1_ifck_core_rates[] = {
1092         { .div = 1, .val = 1, .flags = RATE_IN_242X | DEFAULT_RATE },
1093         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1094         { .div = 3, .val = 3, .flags = RATE_IN_242X },
1095         { .div = 4, .val = 4, .flags = RATE_IN_242X },
1096         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1097         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1098         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1099         { .div = 0 },
1100 };
1101
1102 static const struct clksel iva1_ifck_clksel[] = {
1103         { .parent = &core_ck, .rates = iva1_ifck_core_rates },
1104         { .parent = NULL }
1105 };
1106
1107 static struct clk iva1_ifck = {
1108         .name           = "iva1_ifck",
1109         .parent         = &core_ck,
1110         .flags          = CLOCK_IN_OMAP242X | CM_DSP_SEL1 |
1111                         CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
1112         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
1113         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
1114         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1115         .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
1116         .clksel         = iva1_ifck_clksel,
1117         .recalc         = &omap2_clksel_recalc,
1118         .round_rate     = &omap2_clksel_round_rate,
1119         .set_rate       = &omap2_clksel_set_rate
1120 };
1121
1122 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1123 static struct clk iva1_mpu_int_ifck = {
1124         .name           = "iva1_mpu_int_ifck",
1125         .parent         = &iva1_ifck,
1126         .flags          = CLOCK_IN_OMAP242X,
1127         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
1128         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
1129         .fixed_div      = 2,
1130         .recalc         = &omap2_fixed_divisor_recalc,
1131 };
1132
1133 /*
1134  * L3 clock domain
1135  * L3 clocks are used for both interface and functional clocks to
1136  * multiple entities. Some of these clocks are completely managed
1137  * by hardware, and some others allow software control. Hardware
1138  * managed ones general are based on directly CLK_REQ signals and
1139  * various auto idle settings. The functional spec sets many of these
1140  * as 'tie-high' for their enables.
1141  *
1142  * I-CLOCKS:
1143  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1144  *      CAM, HS-USB.
1145  * F-CLOCK
1146  *      SSI.
1147  *
1148  * GPMC memories and SDRC have timing and clock sensitive registers which
1149  * may very well need notification when the clock changes. Currently for low
1150  * operating points, these are taken care of in sleep.S.
1151  */
1152 static const struct clksel_rate core_l3_core_rates[] = {
1153         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1154         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1155         { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1156         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1157         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1158         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1159         { .div = 16, .val = 16, .flags = RATE_IN_242X },
1160         { .div = 0 }
1161 };
1162
1163 static const struct clksel core_l3_clksel[] = {
1164         { .parent = &core_ck, .rates = core_l3_core_rates },
1165         { .parent = NULL }
1166 };
1167
1168 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
1169         .name           = "core_l3_ck",
1170         .parent         = &core_ck,
1171         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1172                                 ALWAYS_ENABLED | CM_CORE_SEL1 |
1173                                 DELAYED_APP | CONFIG_PARTICIPANT |
1174                                 RATE_PROPAGATES,
1175         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1176         .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
1177         .clksel         = core_l3_clksel,
1178         .recalc         = &omap2_clksel_recalc,
1179         .round_rate     = &omap2_clksel_round_rate,
1180         .set_rate       = &omap2_clksel_set_rate
1181 };
1182
1183 /* usb_l4_ick */
1184 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1185         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1186         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1187         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1188         { .div = 0 }
1189 };
1190
1191 static const struct clksel usb_l4_ick_clksel[] = {
1192         { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1193         { .parent = NULL },
1194 };
1195
1196 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
1197         .name           = "usb_l4_ick",
1198         .parent         = &core_l3_ck,
1199         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1200                                 CM_CORE_SEL1 | DELAYED_APP |
1201                                 CONFIG_PARTICIPANT,
1202         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1203         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1204         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1205         .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
1206         .clksel         = usb_l4_ick_clksel,
1207         .recalc         = &omap2_clksel_recalc,
1208         .round_rate     = &omap2_clksel_round_rate,
1209         .set_rate       = &omap2_clksel_set_rate
1210 };
1211
1212 /*
1213  * SSI is in L3 management domain, its direct parent is core not l3,
1214  * many core power domain entities are grouped into the L3 clock
1215  * domain.
1216  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
1217  *
1218  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1219  */
1220 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1221         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1222         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1223         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1224         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1225         { .div = 5, .val = 5, .flags = RATE_IN_243X },
1226         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1227         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1228         { .div = 0 }
1229 };
1230
1231 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1232         { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1233         { .parent = NULL }
1234 };
1235
1236 static struct clk ssi_ssr_sst_fck = {
1237         .name           = "ssi_fck",
1238         .parent         = &core_ck,
1239         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1240                                 CM_CORE_SEL1 | DELAYED_APP,
1241         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),       /* bit 1 */
1242         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1243         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1244         .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
1245         .clksel         = ssi_ssr_sst_fck_clksel,
1246         .recalc         = &omap2_clksel_recalc,
1247         .round_rate     = &omap2_clksel_round_rate,
1248         .set_rate       = &omap2_clksel_set_rate
1249 };
1250
1251 /*
1252  * GFX clock domain
1253  *      Clocks:
1254  * GFX_FCLK, GFX_ICLK
1255  * GFX_CG1(2d), GFX_CG2(3d)
1256  *
1257  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1258  * The 2d and 3d clocks run at a hardware determined
1259  * divided value of fclk.
1260  *
1261  */
1262 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1263
1264 /*
1265  * These clksel_rate/clksel structs are shared between gfx_3d_fck and
1266  * gfx_2d_fck
1267  */
1268 static const struct clksel_rate gfx_fck_core_l3_rates[] = {
1269         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1270         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1271         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1272         { .div = 4, .val = 4, .flags = RATE_IN_243X },
1273         { .div = 0 }
1274 };
1275
1276 static const struct clksel gfx_fck_clksel[] = {
1277         { .parent = &core_l3_ck, .rates = gfx_fck_core_l3_rates },
1278         { .parent = NULL },
1279 };
1280
1281 static struct clk gfx_3d_fck = {
1282         .name           = "gfx_3d_fck",
1283         .parent         = &core_l3_ck,
1284         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1285                                 CM_GFX_SEL1,
1286         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
1287         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
1288         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1289         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1290         .clksel         = gfx_fck_clksel,
1291         .recalc         = &omap2_clksel_recalc,
1292         .round_rate     = &omap2_clksel_round_rate,
1293         .set_rate       = &omap2_clksel_set_rate
1294 };
1295
1296 static struct clk gfx_2d_fck = {
1297         .name           = "gfx_2d_fck",
1298         .parent         = &core_l3_ck,
1299         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1300                                 CM_GFX_SEL1,
1301         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
1302         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
1303         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1304         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1305         .clksel         = gfx_fck_clksel,
1306         .recalc         = &omap2_clksel_recalc,
1307         .round_rate     = &omap2_clksel_round_rate,
1308         .set_rate       = &omap2_clksel_set_rate
1309 };
1310
1311 static struct clk gfx_ick = {
1312         .name           = "gfx_ick",            /* From l3 */
1313         .parent         = &core_l3_ck,
1314         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1315         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),  /* bit 0 */
1316         .enable_bit     = OMAP_EN_GFX_SHIFT,
1317         .recalc         = &followparent_recalc,
1318 };
1319
1320 /*
1321  * Modem clock domain (2430)
1322  *      CLOCKS:
1323  *              MDM_OSC_CLK
1324  *              MDM_ICLK
1325  * These clocks are usable in chassis mode only.
1326  */
1327 static const struct clksel_rate mdm_ick_core_rates[] = {
1328         { .div = 1, .val = 1, .flags = RATE_IN_243X },
1329         { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1330         { .div = 6, .val = 6, .flags = RATE_IN_243X },
1331         { .div = 9, .val = 9, .flags = RATE_IN_243X },
1332         { .div = 0 }
1333 };
1334
1335 static const struct clksel mdm_ick_clksel[] = {
1336         { .parent = &core_ck, .rates = mdm_ick_core_rates },
1337         { .parent = NULL }
1338 };
1339
1340 static struct clk mdm_ick = {           /* used both as a ick and fck */
1341         .name           = "mdm_ick",
1342         .parent         = &core_ck,
1343         .flags          = CLOCK_IN_OMAP243X | CM_MODEM_SEL1 |
1344                                 DELAYED_APP | CONFIG_PARTICIPANT,
1345         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1346         .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1347         .clksel_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
1348         .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
1349         .clksel         = mdm_ick_clksel,
1350         .recalc         = &omap2_clksel_recalc,
1351         .round_rate     = &omap2_clksel_round_rate,
1352         .set_rate       = &omap2_clksel_set_rate
1353 };
1354
1355 static struct clk mdm_osc_ck = {
1356         .name           = "mdm_osc_ck",
1357         .parent         = &osc_ck,
1358         .flags          = CLOCK_IN_OMAP243X,
1359         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, OMAP24XX_CM_FCLKEN),
1360         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
1361         .recalc         = &followparent_recalc,
1362 };
1363
1364 /*
1365  * L4 clock management domain
1366  *
1367  * This domain contains lots of interface clocks from the L4 interface, some
1368  * functional clocks.   Fixed APLL functional source clocks are managed in
1369  * this domain.
1370  */
1371 static const struct clksel_rate l4_core_l3_rates[] = {
1372         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1373         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1374         { .div = 0 }
1375 };
1376
1377 static const struct clksel l4_clksel[] = {
1378         { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1379         { .parent = NULL }
1380 };
1381
1382 static struct clk l4_ck = {             /* used both as an ick and fck */
1383         .name           = "l4_ck",
1384         .parent         = &core_l3_ck,
1385         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1386                                 ALWAYS_ENABLED | CM_CORE_SEL1 |
1387                                 DELAYED_APP | RATE_PROPAGATES,
1388         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1389         .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
1390         .clksel         = l4_clksel,
1391         .recalc         = &omap2_clksel_recalc,
1392         .round_rate     = &omap2_clksel_round_rate,
1393         .set_rate       = &omap2_clksel_set_rate
1394 };
1395
1396 static struct clk ssi_l4_ick = {
1397         .name           = "ssi_l4_ick",
1398         .parent         = &l4_ck,
1399         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1400         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),        /* bit 1 */
1401         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1402         .recalc         = &followparent_recalc,
1403 };
1404
1405 /*
1406  * DSS clock domain
1407  * CLOCKs:
1408  * DSS_L4_ICLK, DSS_L3_ICLK,
1409  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1410  *
1411  * DSS is both initiator and target.
1412  */
1413 /* XXX Add RATE_NOT_VALIDATED */
1414
1415 static const struct clksel_rate dss1_fck_sys_rates[] = {
1416         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1417         { .div = 0 }
1418 };
1419
1420 static const struct clksel_rate dss1_fck_core_rates[] = {
1421         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1422         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1423         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1424         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1425         { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1426         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1427         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1428         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1429         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1430         { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1431         { .div = 0 }
1432 };
1433
1434 static const struct clksel dss1_fck_clksel[] = {
1435         { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
1436         { .parent = &core_ck, .rates = dss1_fck_core_rates },
1437         { .parent = NULL },
1438 };
1439
1440 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1441         .name           = "dss_ick",
1442         .parent         = &l4_ck,       /* really both l3 and l4 */
1443         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1444         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1445         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1446         .recalc         = &followparent_recalc,
1447 };
1448
1449 static struct clk dss1_fck = {
1450         .name           = "dss1_fck",
1451         .parent         = &core_ck,             /* Core or sys */
1452         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1453                                 CM_CORE_SEL1 | DELAYED_APP,
1454         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1455         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1456         .init           = &omap2_init_clksel_parent,
1457         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1458         .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
1459         .clksel         = dss1_fck_clksel,
1460         .recalc         = &omap2_clksel_recalc,
1461         .round_rate     = &omap2_clksel_round_rate,
1462         .set_rate       = &omap2_clksel_set_rate
1463 };
1464
1465 static const struct clksel_rate dss2_fck_sys_rates[] = {
1466         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1467         { .div = 0 }
1468 };
1469
1470 static const struct clksel_rate dss2_fck_48m_rates[] = {
1471         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1472         { .div = 0 }
1473 };
1474
1475 static const struct clksel dss2_fck_clksel[] = {
1476         { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
1477         { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1478         { .parent = NULL }
1479 };
1480
1481 static struct clk dss2_fck = {          /* Alt clk used in power management */
1482         .name           = "dss2_fck",
1483         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1484         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1485                                 CM_CORE_SEL1 | DELAYED_APP,
1486         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1487         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
1488         .init           = &omap2_init_clksel_parent,
1489         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1490         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
1491         .clksel         = dss2_fck_clksel,
1492         .recalc         = &followparent_recalc,
1493 };
1494
1495 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1496         .name           = "dss_54m_fck",        /* 54m tv clk */
1497         .parent         = &func_54m_ck,
1498         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1499         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1500         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
1501         .recalc         = &followparent_recalc,
1502 };
1503
1504 /*
1505  * CORE power domain ICLK & FCLK defines.
1506  * Many of the these can have more than one possible parent. Entries
1507  * here will likely have an L4 interface parent, and may have multiple
1508  * functional clock parents.
1509  */
1510 static const struct clksel_rate gpt_32k_rates[] = {
1511         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1512         { .div = 0 }
1513 };
1514
1515 static const struct clksel_rate gpt_sys_rates[] = {
1516         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1517         { .div = 0 }
1518 };
1519
1520 static const struct clksel_rate gpt_alt_rates[] = {
1521         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1522         { .div = 0 }
1523 };
1524
1525 static const struct clksel gpt_clksel[] = {
1526         { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1527         { .parent = &sys_ck,      .rates = gpt_sys_rates },
1528         { .parent = &alt_ck,      .rates = gpt_alt_rates },
1529         { .parent = NULL },
1530 };
1531
1532 static struct clk gpt1_ick = {
1533         .name           = "gpt1_ick",
1534         .parent         = &l4_ck,
1535         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1536         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), /* Bit0 */
1537         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1538         .recalc         = &followparent_recalc,
1539 };
1540
1541 static struct clk gpt1_fck = {
1542         .name           = "gpt1_fck",
1543         .parent         = &func_32k_ck,
1544         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1545                                 CM_WKUP_SEL1,
1546         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),        /* Bit0 */
1547         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1548         .init           = &omap2_init_clksel_parent,
1549         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1550         .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
1551         .clksel         = gpt_clksel,
1552         .recalc         = &omap2_clksel_recalc,
1553         .round_rate     = &omap2_clksel_round_rate,
1554         .set_rate       = &omap2_clksel_set_rate
1555 };
1556
1557 static struct clk gpt2_ick = {
1558         .name           = "gpt2_ick",
1559         .parent         = &l4_ck,
1560         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1561         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit4 */
1562         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1563         .recalc         = &followparent_recalc,
1564 };
1565
1566 static struct clk gpt2_fck = {
1567         .name           = "gpt2_fck",
1568         .parent         = &func_32k_ck,
1569         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1570                                 CM_CORE_SEL2,
1571         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1572         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1573         .init           = &omap2_init_clksel_parent,
1574         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1575         .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
1576         .clksel         = gpt_clksel,
1577         .recalc         = &omap2_clksel_recalc,
1578 };
1579
1580 static struct clk gpt3_ick = {
1581         .name           = "gpt3_ick",
1582         .parent         = &l4_ck,
1583         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1584         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit5 */
1585         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1586         .recalc         = &followparent_recalc,
1587 };
1588
1589 static struct clk gpt3_fck = {
1590         .name           = "gpt3_fck",
1591         .parent         = &func_32k_ck,
1592         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1593                                 CM_CORE_SEL2,
1594         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1595         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1596         .init           = &omap2_init_clksel_parent,
1597         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1598         .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
1599         .clksel         = gpt_clksel,
1600         .recalc         = &omap2_clksel_recalc,
1601 };
1602
1603 static struct clk gpt4_ick = {
1604         .name           = "gpt4_ick",
1605         .parent         = &l4_ck,
1606         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1607         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit6 */
1608         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1609         .recalc         = &followparent_recalc,
1610 };
1611
1612 static struct clk gpt4_fck = {
1613         .name           = "gpt4_fck",
1614         .parent         = &func_32k_ck,
1615         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1616                                 CM_CORE_SEL2,
1617         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1618         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1619         .init           = &omap2_init_clksel_parent,
1620         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1621         .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
1622         .clksel         = gpt_clksel,
1623         .recalc         = &omap2_clksel_recalc,
1624 };
1625
1626 static struct clk gpt5_ick = {
1627         .name           = "gpt5_ick",
1628         .parent         = &l4_ck,
1629         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1630         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* Bit7 */
1631         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1632         .recalc         = &followparent_recalc,
1633 };
1634
1635 static struct clk gpt5_fck = {
1636         .name           = "gpt5_fck",
1637         .parent         = &func_32k_ck,
1638         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1639                                 CM_CORE_SEL2,
1640         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1641         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1642         .init           = &omap2_init_clksel_parent,
1643         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1644         .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
1645         .clksel         = gpt_clksel,
1646         .recalc         = &omap2_clksel_recalc,
1647 };
1648
1649 static struct clk gpt6_ick = {
1650         .name           = "gpt6_ick",
1651         .parent         = &l4_ck,
1652         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1653         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit8 */
1654         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1655         .recalc         = &followparent_recalc,
1656 };
1657
1658 static struct clk gpt6_fck = {
1659         .name           = "gpt6_fck",
1660         .parent         = &func_32k_ck,
1661         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1662                                 CM_CORE_SEL2,
1663         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1664         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1665         .init           = &omap2_init_clksel_parent,
1666         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1667         .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
1668         .clksel         = gpt_clksel,
1669         .recalc         = &omap2_clksel_recalc,
1670 };
1671
1672 static struct clk gpt7_ick = {
1673         .name           = "gpt7_ick",
1674         .parent         = &l4_ck,
1675         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1676         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit9 */
1677         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1678         .recalc         = &followparent_recalc,
1679 };
1680
1681 static struct clk gpt7_fck = {
1682         .name           = "gpt7_fck",
1683         .parent         = &func_32k_ck,
1684         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1685                                 CM_CORE_SEL2,
1686         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1687         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1688         .init           = &omap2_init_clksel_parent,
1689         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1690         .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
1691         .clksel         = gpt_clksel,
1692         .recalc         = &omap2_clksel_recalc,
1693 };
1694
1695 static struct clk gpt8_ick = {
1696         .name           = "gpt8_ick",
1697         .parent         = &l4_ck,
1698         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1699         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit10 */
1700         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1701         .recalc         = &followparent_recalc,
1702 };
1703
1704 static struct clk gpt8_fck = {
1705         .name           = "gpt8_fck",
1706         .parent         = &func_32k_ck,
1707         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1708                                 CM_CORE_SEL2,
1709         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1710         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1711         .init           = &omap2_init_clksel_parent,
1712         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1713         .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
1714         .clksel         = gpt_clksel,
1715         .recalc         = &omap2_clksel_recalc,
1716 };
1717
1718 static struct clk gpt9_ick = {
1719         .name           = "gpt9_ick",
1720         .parent         = &l4_ck,
1721         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1722         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1723         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1724         .recalc         = &followparent_recalc,
1725 };
1726
1727 static struct clk gpt9_fck = {
1728         .name           = "gpt9_fck",
1729         .parent         = &func_32k_ck,
1730         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1731                                         CM_CORE_SEL2,
1732         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1733         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1734         .init           = &omap2_init_clksel_parent,
1735         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1736         .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
1737         .clksel         = gpt_clksel,
1738         .recalc         = &omap2_clksel_recalc,
1739 };
1740
1741 static struct clk gpt10_ick = {
1742         .name           = "gpt10_ick",
1743         .parent         = &l4_ck,
1744         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1745         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1746         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1747         .recalc         = &followparent_recalc,
1748 };
1749
1750 static struct clk gpt10_fck = {
1751         .name           = "gpt10_fck",
1752         .parent         = &func_32k_ck,
1753         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1754                                         CM_CORE_SEL2,
1755         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1756         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1757         .init           = &omap2_init_clksel_parent,
1758         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1759         .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
1760         .clksel         = gpt_clksel,
1761         .recalc         = &omap2_clksel_recalc,
1762 };
1763
1764 static struct clk gpt11_ick = {
1765         .name           = "gpt11_ick",
1766         .parent         = &l4_ck,
1767         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1768         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1769         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1770         .recalc         = &followparent_recalc,
1771 };
1772
1773 static struct clk gpt11_fck = {
1774         .name           = "gpt11_fck",
1775         .parent         = &func_32k_ck,
1776         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1777                                         CM_CORE_SEL2,
1778         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1779         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1780         .init           = &omap2_init_clksel_parent,
1781         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1782         .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
1783         .clksel         = gpt_clksel,
1784         .recalc         = &omap2_clksel_recalc,
1785 };
1786
1787 static struct clk gpt12_ick = {
1788         .name           = "gpt12_ick",
1789         .parent         = &l4_ck,
1790         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1791         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit14 */
1792         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1793         .recalc         = &followparent_recalc,
1794 };
1795
1796 static struct clk gpt12_fck = {
1797         .name           = "gpt12_fck",
1798         .parent         = &func_32k_ck,
1799         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1800                                         CM_CORE_SEL2,
1801         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1802         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1803         .init           = &omap2_init_clksel_parent,
1804         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1805         .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
1806         .clksel         = gpt_clksel,
1807         .recalc         = &omap2_clksel_recalc,
1808 };
1809
1810 static struct clk mcbsp1_ick = {
1811         .name           = "mcbsp1_ick",
1812         .parent         = &l4_ck,
1813         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1814         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1815         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1816         .recalc         = &followparent_recalc,
1817 };
1818
1819 static struct clk mcbsp1_fck = {
1820         .name           = "mcbsp1_fck",
1821         .parent         = &func_96m_ck,
1822         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1823         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1824         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1825         .recalc         = &followparent_recalc,
1826 };
1827
1828 static struct clk mcbsp2_ick = {
1829         .name           = "mcbsp2_ick",
1830         .parent         = &l4_ck,
1831         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1832         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1833         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1834         .recalc         = &followparent_recalc,
1835 };
1836
1837 static struct clk mcbsp2_fck = {
1838         .name           = "mcbsp2_fck",
1839         .parent         = &func_96m_ck,
1840         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1841         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1842         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1843         .recalc         = &followparent_recalc,
1844 };
1845
1846 static struct clk mcbsp3_ick = {
1847         .name           = "mcbsp3_ick",
1848         .parent         = &l4_ck,
1849         .flags          = CLOCK_IN_OMAP243X,
1850         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1851         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1852         .recalc         = &followparent_recalc,
1853 };
1854
1855 static struct clk mcbsp3_fck = {
1856         .name           = "mcbsp3_fck",
1857         .parent         = &func_96m_ck,
1858         .flags          = CLOCK_IN_OMAP243X,
1859         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1860         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1861         .recalc         = &followparent_recalc,
1862 };
1863
1864 static struct clk mcbsp4_ick = {
1865         .name           = "mcbsp4_ick",
1866         .parent         = &l4_ck,
1867         .flags          = CLOCK_IN_OMAP243X,
1868         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1869         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1870         .recalc         = &followparent_recalc,
1871 };
1872
1873 static struct clk mcbsp4_fck = {
1874         .name           = "mcbsp4_fck",
1875         .parent         = &func_96m_ck,
1876         .flags          = CLOCK_IN_OMAP243X,
1877         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1878         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1879         .recalc         = &followparent_recalc,
1880 };
1881
1882 static struct clk mcbsp5_ick = {
1883         .name           = "mcbsp5_ick",
1884         .parent         = &l4_ck,
1885         .flags          = CLOCK_IN_OMAP243X,
1886         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1887         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1888         .recalc         = &followparent_recalc,
1889 };
1890
1891 static struct clk mcbsp5_fck = {
1892         .name           = "mcbsp5_fck",
1893         .parent         = &func_96m_ck,
1894         .flags          = CLOCK_IN_OMAP243X,
1895         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1896         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1897         .recalc         = &followparent_recalc,
1898 };
1899
1900 static struct clk mcspi1_ick = {
1901         .name           = "mcspi_ick",
1902         .id             = 1,
1903         .parent         = &l4_ck,
1904         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1905         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1906         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1907         .recalc         = &followparent_recalc,
1908 };
1909
1910 static struct clk mcspi1_fck = {
1911         .name           = "mcspi_fck",
1912         .id             = 1,
1913         .parent         = &func_48m_ck,
1914         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1915         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1916         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1917         .recalc         = &followparent_recalc,
1918 };
1919
1920 static struct clk mcspi2_ick = {
1921         .name           = "mcspi_ick",
1922         .id             = 2,
1923         .parent         = &l4_ck,
1924         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1925         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1926         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1927         .recalc         = &followparent_recalc,
1928 };
1929
1930 static struct clk mcspi2_fck = {
1931         .name           = "mcspi_fck",
1932         .id             = 2,
1933         .parent         = &func_48m_ck,
1934         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1935         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1936         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1937         .recalc         = &followparent_recalc,
1938 };
1939
1940 static struct clk mcspi3_ick = {
1941         .name           = "mcspi_ick",
1942         .id             = 3,
1943         .parent         = &l4_ck,
1944         .flags          = CLOCK_IN_OMAP243X,
1945         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1946         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1947         .recalc         = &followparent_recalc,
1948 };
1949
1950 static struct clk mcspi3_fck = {
1951         .name           = "mcspi_fck",
1952         .id             = 3,
1953         .parent         = &func_48m_ck,
1954         .flags          = CLOCK_IN_OMAP243X,
1955         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1956         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1957         .recalc         = &followparent_recalc,
1958 };
1959
1960 static struct clk uart1_ick = {
1961         .name           = "uart1_ick",
1962         .parent         = &l4_ck,
1963         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1964         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1965         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1966         .recalc         = &followparent_recalc,
1967 };
1968
1969 static struct clk uart1_fck = {
1970         .name           = "uart1_fck",
1971         .parent         = &func_48m_ck,
1972         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1973         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1974         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1975         .recalc         = &followparent_recalc,
1976 };
1977
1978 static struct clk uart2_ick = {
1979         .name           = "uart2_ick",
1980         .parent         = &l4_ck,
1981         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1982         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1983         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1984         .recalc         = &followparent_recalc,
1985 };
1986
1987 static struct clk uart2_fck = {
1988         .name           = "uart2_fck",
1989         .parent         = &func_48m_ck,
1990         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1991         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1992         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1993         .recalc         = &followparent_recalc,
1994 };
1995
1996 static struct clk uart3_ick = {
1997         .name           = "uart3_ick",
1998         .parent         = &l4_ck,
1999         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2000         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2001         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
2002         .recalc         = &followparent_recalc,
2003 };
2004
2005 static struct clk uart3_fck = {
2006         .name           = "uart3_fck",
2007         .parent         = &func_48m_ck,
2008         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2009         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2010         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
2011         .recalc         = &followparent_recalc,
2012 };
2013
2014 static struct clk gpios_ick = {
2015         .name           = "gpios_ick",
2016         .parent         = &l4_ck,
2017         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2018         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2019         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2020         .recalc         = &followparent_recalc,
2021 };
2022
2023 static struct clk gpios_fck = {
2024         .name           = "gpios_fck",
2025         .parent         = &func_32k_ck,
2026         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2027         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
2028         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2029         .recalc         = &followparent_recalc,
2030 };
2031
2032 static struct clk mpu_wdt_ick = {
2033         .name           = "mpu_wdt_ick",
2034         .parent         = &l4_ck,
2035         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2036         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2037         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2038         .recalc         = &followparent_recalc,
2039 };
2040
2041 static struct clk mpu_wdt_fck = {
2042         .name           = "mpu_wdt_fck",
2043         .parent         = &func_32k_ck,
2044         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2045         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
2046         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2047         .recalc         = &followparent_recalc,
2048 };
2049
2050 static struct clk sync_32k_ick = {
2051         .name           = "sync_32k_ick",
2052         .parent         = &l4_ck,
2053         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2054         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2055         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
2056         .recalc         = &followparent_recalc,
2057 };
2058 static struct clk wdt1_ick = {
2059         .name           = "wdt1_ick",
2060         .parent         = &l4_ck,
2061         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2062         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2063         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
2064         .recalc         = &followparent_recalc,
2065 };
2066 static struct clk omapctrl_ick = {
2067         .name           = "omapctrl_ick",
2068         .parent         = &l4_ck,
2069         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2070         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2071         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
2072         .recalc         = &followparent_recalc,
2073 };
2074 static struct clk icr_ick = {
2075         .name           = "icr_ick",
2076         .parent         = &l4_ck,
2077         .flags          = CLOCK_IN_OMAP243X,
2078         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2079         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
2080         .recalc         = &followparent_recalc,
2081 };
2082
2083 static struct clk cam_ick = {
2084         .name           = "cam_ick",
2085         .parent         = &l4_ck,
2086         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2087         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2088         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2089         .recalc         = &followparent_recalc,
2090 };
2091
2092 static struct clk cam_fck = {
2093         .name           = "cam_fck",
2094         .parent         = &func_96m_ck,
2095         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2096         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2097         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2098         .recalc         = &followparent_recalc,
2099 };
2100
2101 static struct clk mailboxes_ick = {
2102         .name           = "mailboxes_ick",
2103         .parent         = &l4_ck,
2104         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2105         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2106         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
2107         .recalc         = &followparent_recalc,
2108 };
2109
2110 static struct clk wdt4_ick = {
2111         .name           = "wdt4_ick",
2112         .parent         = &l4_ck,
2113         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2114         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2115         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2116         .recalc         = &followparent_recalc,
2117 };
2118
2119 static struct clk wdt4_fck = {
2120         .name           = "wdt4_fck",
2121         .parent         = &func_32k_ck,
2122         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2123         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2124         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2125         .recalc         = &followparent_recalc,
2126 };
2127
2128 static struct clk wdt3_ick = {
2129         .name           = "wdt3_ick",
2130         .parent         = &l4_ck,
2131         .flags          = CLOCK_IN_OMAP242X,
2132         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2133         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2134         .recalc         = &followparent_recalc,
2135 };
2136
2137 static struct clk wdt3_fck = {
2138         .name           = "wdt3_fck",
2139         .parent         = &func_32k_ck,
2140         .flags          = CLOCK_IN_OMAP242X,
2141         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2142         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2143         .recalc         = &followparent_recalc,
2144 };
2145
2146 static struct clk mspro_ick = {
2147         .name           = "mspro_ick",
2148         .parent         = &l4_ck,
2149         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2150         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2151         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2152         .recalc         = &followparent_recalc,
2153 };
2154
2155 static struct clk mspro_fck = {
2156         .name           = "mspro_fck",
2157         .parent         = &func_96m_ck,
2158         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2159         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2160         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2161         .recalc         = &followparent_recalc,
2162 };
2163
2164 static struct clk mmc_ick = {
2165         .name           = "mmc_ick",
2166         .parent         = &l4_ck,
2167         .flags          = CLOCK_IN_OMAP242X,
2168         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2169         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2170         .recalc         = &followparent_recalc,
2171 };
2172
2173 static struct clk mmc_fck = {
2174         .name           = "mmc_fck",
2175         .parent         = &func_96m_ck,
2176         .flags          = CLOCK_IN_OMAP242X,
2177         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2178         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2179         .recalc         = &followparent_recalc,
2180 };
2181
2182 static struct clk fac_ick = {
2183         .name           = "fac_ick",
2184         .parent         = &l4_ck,
2185         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2186         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2187         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2188         .recalc         = &followparent_recalc,
2189 };
2190
2191 static struct clk fac_fck = {
2192         .name           = "fac_fck",
2193         .parent         = &func_12m_ck,
2194         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2195         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2196         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2197         .recalc         = &followparent_recalc,
2198 };
2199
2200 static struct clk eac_ick = {
2201         .name           = "eac_ick",
2202         .parent         = &l4_ck,
2203         .flags          = CLOCK_IN_OMAP242X,
2204         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2205         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2206         .recalc         = &followparent_recalc,
2207 };
2208
2209 static struct clk eac_fck = {
2210         .name           = "eac_fck",
2211         .parent         = &func_96m_ck,
2212         .flags          = CLOCK_IN_OMAP242X,
2213         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2214         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2215         .recalc         = &followparent_recalc,
2216 };
2217
2218 static struct clk hdq_ick = {
2219         .name           = "hdq_ick",
2220         .parent         = &l4_ck,
2221         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2222         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2223         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2224         .recalc         = &followparent_recalc,
2225 };
2226
2227 static struct clk hdq_fck = {
2228         .name           = "hdq_fck",
2229         .parent         = &func_12m_ck,
2230         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2231         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2232         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2233         .recalc         = &followparent_recalc,
2234 };
2235
2236 static struct clk i2c2_ick = {
2237         .name           = "i2c_ick",
2238         .id             = 2,
2239         .parent         = &l4_ck,
2240         .flags          = CLOCK_IN_OMAP242X,
2241         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2242         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2243         .recalc         = &followparent_recalc,
2244 };
2245
2246 static struct clk i2c2_fck = {
2247         .name           = "i2c_fck",
2248         .id             = 2,
2249         .parent         = &func_12m_ck,
2250         .flags          = CLOCK_IN_OMAP242X,
2251         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2252         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2253         .recalc         = &followparent_recalc,
2254 };
2255
2256 static struct clk i2chs2_fck = {
2257         .name           = "i2chs_fck",
2258         .id             = 2,
2259         .parent         = &func_96m_ck,
2260         .flags          = CLOCK_IN_OMAP243X,
2261         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2262         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
2263         .recalc         = &followparent_recalc,
2264 };
2265
2266 static struct clk i2c1_ick = {
2267         .name           = "i2c_ick",
2268         .id             = 1,
2269         .parent         = &l4_ck,
2270         .flags          = CLOCK_IN_OMAP242X,
2271         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2272         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2273         .recalc         = &followparent_recalc,
2274 };
2275
2276 static struct clk i2c1_fck = {
2277         .name           = "i2c_fck",
2278         .id             = 1,
2279         .parent         = &func_12m_ck,
2280         .flags          = CLOCK_IN_OMAP242X,
2281         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2282         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2283         .recalc         = &followparent_recalc,
2284 };
2285
2286 static struct clk i2chs1_fck = {
2287         .name           = "i2chs_fck",
2288         .id             = 1,
2289         .parent         = &func_96m_ck,
2290         .flags          = CLOCK_IN_OMAP243X,
2291         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2292         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
2293         .recalc         = &followparent_recalc,
2294 };
2295
2296 static struct clk vlynq_ick = {
2297         .name           = "vlynq_ick",
2298         .parent         = &core_l3_ck,
2299         .flags          = CLOCK_IN_OMAP242X,
2300         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2301         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2302         .recalc         = &followparent_recalc,
2303 };
2304
2305 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2306         { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2307         { .div = 0 }
2308 };
2309
2310 static const struct clksel_rate vlynq_fck_core_rates[] = {
2311         { .div = 1, .val = 1, .flags = RATE_IN_242X },
2312         { .div = 2, .val = 2, .flags = RATE_IN_242X },
2313         { .div = 3, .val = 3, .flags = RATE_IN_242X },
2314         { .div = 4, .val = 4, .flags = RATE_IN_242X },
2315         { .div = 6, .val = 6, .flags = RATE_IN_242X },
2316         { .div = 8, .val = 8, .flags = RATE_IN_242X },
2317         { .div = 9, .val = 9, .flags = RATE_IN_242X },
2318         { .div = 12, .val = 12, .flags = RATE_IN_242X },
2319         { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2320         { .div = 18, .val = 18, .flags = RATE_IN_242X },
2321         { .div = 0 }
2322 };
2323
2324 static const struct clksel vlynq_fck_clksel[] = {
2325         { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2326         { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
2327         { .parent = NULL }
2328 };
2329
2330 static struct clk vlynq_fck = {
2331         .name           = "vlynq_fck",
2332         .parent         = &func_96m_ck,
2333         .flags          = CLOCK_IN_OMAP242X | CM_CORE_SEL1 | DELAYED_APP,
2334         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2335         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2336         .init           = &omap2_init_clksel_parent,
2337         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
2338         .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
2339         .clksel         = vlynq_fck_clksel,
2340         .recalc         = &omap2_clksel_recalc,
2341         .round_rate     = &omap2_clksel_round_rate,
2342         .set_rate       = &omap2_clksel_set_rate
2343 };
2344
2345 static struct clk sdrc_ick = {
2346         .name           = "sdrc_ick",
2347         .parent         = &l4_ck,
2348         .flags          = CLOCK_IN_OMAP243X,
2349         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP2430_CM_ICLKEN3),
2350         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
2351         .recalc         = &followparent_recalc,
2352 };
2353
2354 static struct clk des_ick = {
2355         .name           = "des_ick",
2356         .parent         = &l4_ck,
2357         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2358         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2359         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
2360         .recalc         = &followparent_recalc,
2361 };
2362
2363 static struct clk sha_ick = {
2364         .name           = "sha_ick",
2365         .parent         = &l4_ck,
2366         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2367         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2368         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
2369         .recalc         = &followparent_recalc,
2370 };
2371
2372 static struct clk rng_ick = {
2373         .name           = "rng_ick",
2374         .parent         = &l4_ck,
2375         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2376         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2377         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
2378         .recalc         = &followparent_recalc,
2379 };
2380
2381 static struct clk aes_ick = {
2382         .name           = "aes_ick",
2383         .parent         = &l4_ck,
2384         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2385         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2386         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
2387         .recalc         = &followparent_recalc,
2388 };
2389
2390 static struct clk pka_ick = {
2391         .name           = "pka_ick",
2392         .parent         = &l4_ck,
2393         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2394         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2395         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
2396         .recalc         = &followparent_recalc,
2397 };
2398
2399 static struct clk usb_fck = {
2400         .name           = "usb_fck",
2401         .parent         = &func_48m_ck,
2402         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2403         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2404         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
2405         .recalc         = &followparent_recalc,
2406 };
2407
2408 static struct clk usbhs_ick = {
2409         .name           = "usbhs_ick",
2410         .parent         = &core_l3_ck,
2411         .flags          = CLOCK_IN_OMAP243X,
2412         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2413         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
2414         .recalc         = &followparent_recalc,
2415 };
2416
2417 static struct clk mmchs1_ick = {
2418         .name           = "mmchs1_ick",
2419         .parent         = &l4_ck,
2420         .flags          = CLOCK_IN_OMAP243X,
2421         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2422         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2423         .recalc         = &followparent_recalc,
2424 };
2425
2426 static struct clk mmchs1_fck = {
2427         .name           = "mmchs1_fck",
2428         .parent         = &func_96m_ck,
2429         .flags          = CLOCK_IN_OMAP243X,
2430         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2431         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2432         .recalc         = &followparent_recalc,
2433 };
2434
2435 static struct clk mmchs2_ick = {
2436         .name           = "mmchs2_ick",
2437         .parent         = &l4_ck,
2438         .flags          = CLOCK_IN_OMAP243X,
2439         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2440         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2441         .recalc         = &followparent_recalc,
2442 };
2443
2444 static struct clk mmchs2_fck = {
2445         .name           = "mmchs2_fck",
2446         .parent         = &func_96m_ck,
2447         .flags          = CLOCK_IN_OMAP243X,
2448         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2449         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2450         .recalc         = &followparent_recalc,
2451 };
2452
2453 static struct clk gpio5_ick = {
2454         .name           = "gpio5_ick",
2455         .parent         = &l4_ck,
2456         .flags          = CLOCK_IN_OMAP243X,
2457         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2458         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2459         .recalc         = &followparent_recalc,
2460 };
2461
2462 static struct clk gpio5_fck = {
2463         .name           = "gpio5_fck",
2464         .parent         = &func_32k_ck,
2465         .flags          = CLOCK_IN_OMAP243X,
2466         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2467         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2468         .recalc         = &followparent_recalc,
2469 };
2470
2471 static struct clk mdm_intc_ick = {
2472         .name           = "mdm_intc_ick",
2473         .parent         = &l4_ck,
2474         .flags          = CLOCK_IN_OMAP243X,
2475         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2476         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
2477         .recalc         = &followparent_recalc,
2478 };
2479
2480 static struct clk mmchsdb1_fck = {
2481         .name           = "mmchsdb1_fck",
2482         .parent         = &func_32k_ck,
2483         .flags          = CLOCK_IN_OMAP243X,
2484         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2485         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
2486         .recalc         = &followparent_recalc,
2487 };
2488
2489 static struct clk mmchsdb2_fck = {
2490         .name           = "mmchsdb2_fck",
2491         .parent         = &func_32k_ck,
2492         .flags          = CLOCK_IN_OMAP243X,
2493         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2494         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
2495         .recalc         = &followparent_recalc,
2496 };
2497
2498 /*
2499  * This clock is a composite clock which does entire set changes then
2500  * forces a rebalance. It keys on the MPU speed, but it really could
2501  * be any key speed part of a set in the rate table.
2502  *
2503  * to really change a set, you need memory table sets which get changed
2504  * in sram, pre-notifiers & post notifiers, changing the top set, without
2505  * having low level display recalc's won't work... this is why dpm notifiers
2506  * work, isr's off, walk a list of clocks already _off_ and not messing with
2507  * the bus.
2508  *
2509  * This clock should have no parent. It embodies the entire upper level
2510  * active set. A parent will mess up some of the init also.
2511  */
2512 static struct clk virt_prcm_set = {
2513         .name           = "virt_prcm_set",
2514         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2515                                 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
2516         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
2517         .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
2518         .set_rate       = &omap2_select_table_rate,
2519         .round_rate     = &omap2_round_to_table_rate,
2520 };
2521
2522 static struct clk *onchip_clks[] __initdata = {
2523         /* external root sources */
2524         &func_32k_ck,
2525         &osc_ck,
2526         &sys_ck,
2527         &alt_ck,
2528         /* internal analog sources */
2529         &dpll_ck,
2530         &apll96_ck,
2531         &apll54_ck,
2532         /* internal prcm root sources */
2533         &func_54m_ck,
2534         &core_ck,
2535         &func_96m_ck,
2536         &func_48m_ck,
2537         &func_12m_ck,
2538         &wdt1_osc_ck,
2539         &sys_clkout_src,
2540         &sys_clkout,
2541         &sys_clkout2_src,
2542         &sys_clkout2,
2543         &emul_ck,
2544         /* mpu domain clocks */
2545         &mpu_ck,
2546         /* dsp domain clocks */
2547         &iva2_1_fck,            /* 2430 */
2548         &iva2_1_ick,
2549         &dsp_ick,               /* 2420 */
2550         &dsp_fck,
2551         &iva1_ifck,
2552         &iva1_mpu_int_ifck,
2553         /* GFX domain clocks */
2554         &gfx_3d_fck,
2555         &gfx_2d_fck,
2556         &gfx_ick,
2557         /* Modem domain clocks */
2558         &mdm_ick,
2559         &mdm_osc_ck,
2560         /* DSS domain clocks */
2561         &dss_ick,
2562         &dss1_fck,
2563         &dss2_fck,
2564         &dss_54m_fck,
2565         /* L3 domain clocks */
2566         &core_l3_ck,
2567         &ssi_ssr_sst_fck,
2568         &usb_l4_ick,
2569         /* L4 domain clocks */
2570         &l4_ck,                 /* used as both core_l4 and wu_l4 */
2571         &ssi_l4_ick,
2572         /* virtual meta-group clock */
2573         &virt_prcm_set,
2574         /* general l4 interface ck, multi-parent functional clk */
2575         &gpt1_ick,
2576         &gpt1_fck,
2577         &gpt2_ick,
2578         &gpt2_fck,
2579         &gpt3_ick,
2580         &gpt3_fck,
2581         &gpt4_ick,
2582         &gpt4_fck,
2583         &gpt5_ick,
2584         &gpt5_fck,
2585         &gpt6_ick,
2586         &gpt6_fck,
2587         &gpt7_ick,
2588         &gpt7_fck,
2589         &gpt8_ick,
2590         &gpt8_fck,
2591         &gpt9_ick,
2592         &gpt9_fck,
2593         &gpt10_ick,
2594         &gpt10_fck,
2595         &gpt11_ick,
2596         &gpt11_fck,
2597         &gpt12_ick,
2598         &gpt12_fck,
2599         &mcbsp1_ick,
2600         &mcbsp1_fck,
2601         &mcbsp2_ick,
2602         &mcbsp2_fck,
2603         &mcbsp3_ick,
2604         &mcbsp3_fck,
2605         &mcbsp4_ick,
2606         &mcbsp4_fck,
2607         &mcbsp5_ick,
2608         &mcbsp5_fck,
2609         &mcspi1_ick,
2610         &mcspi1_fck,
2611         &mcspi2_ick,
2612         &mcspi2_fck,
2613         &mcspi3_ick,
2614         &mcspi3_fck,
2615         &uart1_ick,
2616         &uart1_fck,
2617         &uart2_ick,
2618         &uart2_fck,
2619         &uart3_ick,
2620         &uart3_fck,
2621         &gpios_ick,
2622         &gpios_fck,
2623         &mpu_wdt_ick,
2624         &mpu_wdt_fck,
2625         &sync_32k_ick,
2626         &wdt1_ick,
2627         &omapctrl_ick,
2628         &icr_ick,
2629         &cam_fck,
2630         &cam_ick,
2631         &mailboxes_ick,
2632         &wdt4_ick,
2633         &wdt4_fck,
2634         &wdt3_ick,
2635         &wdt3_fck,
2636         &mspro_ick,
2637         &mspro_fck,
2638         &mmc_ick,
2639         &mmc_fck,
2640         &fac_ick,
2641         &fac_fck,
2642         &eac_ick,
2643         &eac_fck,
2644         &hdq_ick,
2645         &hdq_fck,
2646         &i2c1_ick,
2647         &i2c1_fck,
2648         &i2chs1_fck,
2649         &i2c2_ick,
2650         &i2c2_fck,
2651         &i2chs2_fck,
2652         &vlynq_ick,
2653         &vlynq_fck,
2654         &sdrc_ick,
2655         &des_ick,
2656         &sha_ick,
2657         &rng_ick,
2658         &aes_ick,
2659         &pka_ick,
2660         &usb_fck,
2661         &usbhs_ick,
2662         &mmchs1_ick,
2663         &mmchs1_fck,
2664         &mmchs2_ick,
2665         &mmchs2_fck,
2666         &gpio5_ick,
2667         &gpio5_fck,
2668         &mdm_intc_ick,
2669         &mmchsdb1_fck,
2670         &mmchsdb2_fck,
2671 };
2672
2673 #endif