2 * linux/arch/arm/mach-omap24xx/clock.h
4 * Copyright (C) 2005 Texas Instruments Inc.
5 * Richard Woodruff <r-woodruff2@ti.com>
8 * Copyright (C) 2004 Nokia corporation
9 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
10 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
18 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
22 #include "prm_regbits_24xx.h"
23 #include "cm_regbits_24xx.h"
25 static void omap2_sys_clk_recalc(struct clk * clk);
26 static void omap2_clksel_recalc(struct clk * clk);
27 static void omap2_followparent_recalc(struct clk * clk);
28 static void omap2_propagate_rate(struct clk * clk);
29 static void omap2_mpu_recalc(struct clk * clk);
30 static int omap2_select_table_rate(struct clk * clk, unsigned long rate);
31 static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate);
32 static void omap2_clk_disable(struct clk *clk);
33 static void omap2_sys_clk_recalc(struct clk * clk);
34 static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val);
35 static u32 omap2_clksel_get_divisor(struct clk *clk);
37 /* REVISIT: should use a clock flag for this, not a magic number */
38 #define PARENT_CONTROLS_CLOCK 0xff
40 #define RATE_IN_242X (1 << 0)
41 #define RATE_IN_243X (1 << 1)
42 #define RATE_IN_343X (1 << 2)
44 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
45 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
46 * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
49 unsigned long xtal_speed; /* crystal rate */
50 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
51 unsigned long mpu_speed; /* speed of MPU */
52 unsigned long cm_clksel_mpu; /* mpu divider */
53 unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
54 unsigned long cm_clksel_gfx; /* gfx dividers */
55 unsigned long cm_clksel1_core; /* major subsystem dividers */
56 unsigned long cm_clksel1_pll; /* m,n */
57 unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
58 unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
59 unsigned long base_sdrc_rfr; /* base refresh timing for a set */
63 /* Mask for clksel which support parent settign in set_rate */
64 #define SRC_SEL_MASK (CM_CORE_SEL1 | CM_CORE_SEL2 | CM_WKUP_SEL1 | \
65 CM_PLL_SEL1 | CM_PLL_SEL2 | CM_SYSCLKOUT_SEL1)
67 /* Mask for clksel regs which support rate operations */
68 #define SRC_RATE_SEL_MASK (SRC_SEL_MASK | CM_MPU_SEL1 | CM_DSP_SEL1 | \
69 CM_GFX_SEL1 | CM_MODEM_SEL1)
72 * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
73 * These configurations are characterized by voltage and speed for clocks.
74 * The device is only validated for certain combinations. One way to express
75 * these combinations is via the 'ratio's' which the clocks operate with
76 * respect to each other. These ratio sets are for a given voltage/DPLL
77 * setting. All configurations can be described by a DPLL setting and a ratio
78 * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
80 * 2430 differs from 2420 in that there are no more phase synchronizers used.
81 * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
82 * 2430 (iva2.1, NOdsp, mdm)
85 /* Core fields for cm_clksel, not ratio governed */
86 #define RX_CLKSEL_DSS1 (0x10 << 8)
87 #define RX_CLKSEL_DSS2 (0x0 << 13)
88 #define RX_CLKSEL_SSI (0x5 << 20)
90 /*-------------------------------------------------------------------------
92 *-------------------------------------------------------------------------*/
94 /* 2430 Ratio's, 2430-Ratio Config 1 */
95 #define R1_CLKSEL_L3 (4 << 0)
96 #define R1_CLKSEL_L4 (2 << 5)
97 #define R1_CLKSEL_USB (4 << 25)
98 #define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | \
99 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
100 R1_CLKSEL_L4 | R1_CLKSEL_L3
101 #define R1_CLKSEL_MPU (2 << 0)
102 #define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU
103 #define R1_CLKSEL_DSP (2 << 0)
104 #define R1_CLKSEL_DSP_IF (2 << 5)
105 #define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
106 #define R1_CLKSEL_GFX (2 << 0)
107 #define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX
108 #define R1_CLKSEL_MDM (4 << 0)
109 #define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM
111 /* 2430-Ratio Config 2 */
112 #define R2_CLKSEL_L3 (6 << 0)
113 #define R2_CLKSEL_L4 (2 << 5)
114 #define R2_CLKSEL_USB (2 << 25)
115 #define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | \
116 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
117 R2_CLKSEL_L4 | R2_CLKSEL_L3
118 #define R2_CLKSEL_MPU (2 << 0)
119 #define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU
120 #define R2_CLKSEL_DSP (2 << 0)
121 #define R2_CLKSEL_DSP_IF (3 << 5)
122 #define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
123 #define R2_CLKSEL_GFX (2 << 0)
124 #define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX
125 #define R2_CLKSEL_MDM (6 << 0)
126 #define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM
128 /* 2430-Ratio Bootm (BYPASS) */
129 #define RB_CLKSEL_L3 (1 << 0)
130 #define RB_CLKSEL_L4 (1 << 5)
131 #define RB_CLKSEL_USB (1 << 25)
132 #define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | \
133 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
134 RB_CLKSEL_L4 | RB_CLKSEL_L3
135 #define RB_CLKSEL_MPU (1 << 0)
136 #define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU
137 #define RB_CLKSEL_DSP (1 << 0)
138 #define RB_CLKSEL_DSP_IF (1 << 5)
139 #define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
140 #define RB_CLKSEL_GFX (1 << 0)
141 #define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX
142 #define RB_CLKSEL_MDM (1 << 0)
143 #define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM
145 /* 2420 Ratio Equivalents */
146 #define RXX_CLKSEL_VLYNQ (0x12 << 15)
147 #define RXX_CLKSEL_SSI (0x8 << 20)
149 /* 2420-PRCM III 532MHz core */
150 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
151 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
152 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
153 #define RIII_CM_CLKSEL1_CORE_VAL RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
154 RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
155 RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
157 #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
158 #define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU
159 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
160 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
161 #define RIII_SYNC_DSP (1 << 7) /* Enable sync */
162 #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
163 #define RIII_SYNC_IVA (1 << 13) /* Enable sync */
164 #define RIII_CM_CLKSEL_DSP_VAL RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
165 RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
167 #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
168 #define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX
170 /* 2420-PRCM II 600MHz core */
171 #define RII_CLKSEL_L3 (6 << 0) /* 100MHz */
172 #define RII_CLKSEL_L4 (2 << 5) /* 50MHz */
173 #define RII_CLKSEL_USB (2 << 25) /* 50MHz */
174 #define RII_CM_CLKSEL1_CORE_VAL RII_CLKSEL_USB | \
175 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
176 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
177 RII_CLKSEL_L4 | RII_CLKSEL_L3
178 #define RII_CLKSEL_MPU (2 << 0) /* 300MHz */
179 #define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU
180 #define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
181 #define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
182 #define RII_SYNC_DSP (0 << 7) /* Bypass sync */
183 #define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */
184 #define RII_SYNC_IVA (0 << 13) /* Bypass sync */
185 #define RII_CM_CLKSEL_DSP_VAL RII_SYNC_IVA | RII_CLKSEL_IVA | \
186 RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
188 #define RII_CLKSEL_GFX (2 << 0) /* 50MHz */
189 #define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX
191 /* 2420-PRCM I 660MHz core */
192 #define RI_CLKSEL_L3 (4 << 0) /* 165MHz */
193 #define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */
194 #define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */
195 #define RI_CM_CLKSEL1_CORE_VAL RI_CLKSEL_USB | \
196 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
197 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
198 RI_CLKSEL_L4 | RI_CLKSEL_L3
199 #define RI_CLKSEL_MPU (2 << 0) /* 330MHz */
200 #define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU
201 #define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */
202 #define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */
203 #define RI_SYNC_DSP (1 << 7) /* Activate sync */
204 #define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */
205 #define RI_SYNC_IVA (0 << 13) /* Bypass sync */
206 #define RI_CM_CLKSEL_DSP_VAL RI_SYNC_IVA | RI_CLKSEL_IVA | \
207 RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
209 #define RI_CLKSEL_GFX (1 << 0) /* 165MHz */
210 #define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX
212 /* 2420-PRCM VII (boot) */
213 #define RVII_CLKSEL_L3 (1 << 0)
214 #define RVII_CLKSEL_L4 (1 << 5)
215 #define RVII_CLKSEL_DSS1 (1 << 8)
216 #define RVII_CLKSEL_DSS2 (0 << 13)
217 #define RVII_CLKSEL_VLYNQ (1 << 15)
218 #define RVII_CLKSEL_SSI (1 << 20)
219 #define RVII_CLKSEL_USB (1 << 25)
221 #define RVII_CM_CLKSEL1_CORE_VAL RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
222 RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
223 RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
225 #define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */
226 #define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU
228 #define RVII_CLKSEL_DSP (1 << 0)
229 #define RVII_CLKSEL_DSP_IF (1 << 5)
230 #define RVII_SYNC_DSP (0 << 7)
231 #define RVII_CLKSEL_IVA (1 << 8)
232 #define RVII_SYNC_IVA (0 << 13)
233 #define RVII_CM_CLKSEL_DSP_VAL RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
234 RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
236 #define RVII_CLKSEL_GFX (1 << 0)
237 #define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX
239 /*-------------------------------------------------------------------------
240 * 2430 Target modes: Along with each configuration the CPU has several
241 * modes which goes along with them. Modes mainly are the addition of
242 * describe DPLL combinations to go along with a ratio.
243 *-------------------------------------------------------------------------*/
245 /* Hardware governed */
246 #define MX_48M_SRC (0 << 3)
247 #define MX_54M_SRC (0 << 5)
248 #define MX_APLLS_CLIKIN_12 (3 << 23)
249 #define MX_APLLS_CLIKIN_13 (2 << 23)
250 #define MX_APLLS_CLIKIN_19_2 (0 << 23)
253 * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
254 * #2 (ratio1) baseport-target
255 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
257 #define M5A_DPLL_MULT_12 (133 << 12)
258 #define M5A_DPLL_DIV_12 (5 << 8)
259 #define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
260 M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
262 #define M5A_DPLL_MULT_13 (266 << 12)
263 #define M5A_DPLL_DIV_13 (12 << 8)
264 #define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
265 M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
267 #define M5A_DPLL_MULT_19 (180 << 12)
268 #define M5A_DPLL_DIV_19 (12 << 8)
269 #define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
270 M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
272 /* #5b (ratio1) target DPLL = 200*2 = 400MHz */
273 #define M5B_DPLL_MULT_12 (50 << 12)
274 #define M5B_DPLL_DIV_12 (2 << 8)
275 #define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
276 M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
278 #define M5B_DPLL_MULT_13 (200 << 12)
279 #define M5B_DPLL_DIV_13 (12 << 8)
281 #define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
282 M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
284 #define M5B_DPLL_MULT_19 (125 << 12)
285 #define M5B_DPLL_DIV_19 (31 << 8)
286 #define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
287 M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
291 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
293 #define M3_DPLL_MULT_12 (55 << 12)
294 #define M3_DPLL_DIV_12 (1 << 8)
295 #define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
296 M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
298 #define M3_DPLL_MULT_13 (330 << 12)
299 #define M3_DPLL_DIV_13 (12 << 8)
300 #define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
301 M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
303 #define M3_DPLL_MULT_19 (275 << 12)
304 #define M3_DPLL_DIV_19 (15 << 8)
305 #define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
306 M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
309 #define MB_DPLL_MULT (1 << 12)
310 #define MB_DPLL_DIV (0 << 8)
311 #define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
312 MB_DPLL_MULT | MX_APLLS_CLIKIN_12
314 #define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
315 MB_DPLL_MULT | MX_APLLS_CLIKIN_13
317 #define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
318 MB_DPLL_MULT | MX_APLLS_CLIKIN_19
321 * 2430 - chassis (sedna)
322 * 165 (ratio1) same as above #2
324 * 133 (ratio2) same as above #4
325 * 110 (ratio2) same as above #3
330 /* PRCM I target DPLL = 2*330MHz = 660MHz */
331 #define MI_DPLL_MULT_12 (55 << 12)
332 #define MI_DPLL_DIV_12 (1 << 8)
333 #define MI_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
334 MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
338 * 2420 Equivalent - mode registers
339 * PRCM II , target DPLL = 2*300MHz = 600MHz
341 #define MII_DPLL_MULT_12 (50 << 12)
342 #define MII_DPLL_DIV_12 (1 << 8)
343 #define MII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
344 MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
346 #define MII_DPLL_MULT_13 (300 << 12)
347 #define MII_DPLL_DIV_13 (12 << 8)
348 #define MII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
349 MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
352 /* PRCM III target DPLL = 2*266 = 532MHz*/
353 #define MIII_DPLL_MULT_12 (133 << 12)
354 #define MIII_DPLL_DIV_12 (5 << 8)
355 #define MIII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
356 MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
358 #define MIII_DPLL_MULT_13 (266 << 12)
359 #define MIII_DPLL_DIV_13 (12 << 8)
360 #define MIII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
361 MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
364 /* PRCM VII (boot bypass) */
365 #define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL
366 #define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL
368 /* High and low operation value */
369 #define MX_CLKSEL2_PLL_2x_VAL (2 << 0)
370 #define MX_CLKSEL2_PLL_1x_VAL (1 << 0)
373 * These represent optimal values for common parts, it won't work for all.
374 * As long as you scale down, most parameters are still work, they just
375 * become sub-optimal. The RFR value goes in the opposite direction. If you
376 * don't adjust it down as your clock period increases the refresh interval
377 * will not be met. Setting all parameters for complete worst case may work,
378 * but may cut memory performance by 2x. Due to errata the DLLs need to be
379 * unlocked and their value needs run time calibration. A dynamic call is
380 * need for that as no single right value exists acorss production samples.
382 * Only the FULL speed values are given. Current code is such that rate
383 * changes must be made at DPLLoutx2. The actual value adjustment for low
384 * frequency operation will be handled by omap_set_performance()
386 * By having the boot loader boot up in the fastest L4 speed available likely
387 * will result in something which you can switch between.
389 #define V24XX_SDRC_RFR_CTRL_165MHz (0x00044c00 | 1)
390 #define V24XX_SDRC_RFR_CTRL_133MHz (0x0003de00 | 1)
391 #define V24XX_SDRC_RFR_CTRL_100MHz (0x0002da01 | 1)
392 #define V24XX_SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */
393 #define V24XX_SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */
395 /* MPU speed defines */
396 #define S12M 12000000
397 #define S13M 13000000
398 #define S19M 19200000
399 #define S26M 26000000
400 #define S100M 100000000
401 #define S133M 133000000
402 #define S150M 150000000
403 #define S165M 165000000
404 #define S200M 200000000
405 #define S266M 266000000
406 #define S300M 300000000
407 #define S330M 330000000
408 #define S400M 400000000
409 #define S532M 532000000
410 #define S600M 600000000
411 #define S660M 660000000
413 /*-------------------------------------------------------------------------
414 * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
415 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
416 * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
417 * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
419 * Filling in table based on H4 boards and 2430-SDPs variants available.
420 * There are quite a few more rates combinations which could be defined.
422 * When multiple values are defined the start up will try and choose the
423 * fastest one. If a 'fast' value is defined, then automatically, the /2
424 * one should be included as it can be used. Generally having more that
425 * one fast set does not make sense, as static timings need to be changed
426 * to change the set. The exception is the bypass setting which is
427 * availble for low power bypass.
429 * Note: This table needs to be sorted, fastest to slowest.
430 *-------------------------------------------------------------------------*/
431 static struct prcm_config rate_table[] = {
433 {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
434 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
435 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
436 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_165MHz,
440 {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
441 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
442 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
443 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
446 {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
447 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
448 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
449 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
452 /* PRCM III - FAST */
453 {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
454 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
455 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
456 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
459 {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
460 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
461 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
462 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
466 {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
467 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
468 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
469 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
472 {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
473 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
474 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
475 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
478 /* PRCM III - SLOW */
479 {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
480 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
481 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
482 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
485 {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
486 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
487 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
488 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
491 /* PRCM-VII (boot-bypass) */
492 {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
493 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
494 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
495 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
498 /* PRCM-VII (boot-bypass) */
499 {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
500 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
501 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
502 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
505 /* PRCM #3 - ratio2 (ES2) - FAST */
506 {S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
507 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
508 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
509 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
510 V24XX_SDRC_RFR_CTRL_110MHz,
513 /* PRCM #5a - ratio1 - FAST */
514 {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
515 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
516 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
517 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
518 V24XX_SDRC_RFR_CTRL_133MHz,
521 /* PRCM #5b - ratio1 - FAST */
522 {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
523 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
524 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
525 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
526 V24XX_SDRC_RFR_CTRL_100MHz,
529 /* PRCM #3 - ratio2 (ES2) - SLOW */
530 {S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
531 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
532 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
533 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
534 V24XX_SDRC_RFR_CTRL_110MHz,
537 /* PRCM #5a - ratio1 - SLOW */
538 {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
539 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
540 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
541 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
542 V24XX_SDRC_RFR_CTRL_133MHz,
545 /* PRCM #5b - ratio1 - SLOW*/
546 {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */
547 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
548 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
549 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
550 V24XX_SDRC_RFR_CTRL_100MHz,
553 /* PRCM-boot/bypass */
554 {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */
555 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
556 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
557 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
558 V24XX_SDRC_RFR_CTRL_BYPASS,
561 /* PRCM-boot/bypass */
562 {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */
563 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
564 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
565 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
566 V24XX_SDRC_RFR_CTRL_BYPASS,
569 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
572 /*-------------------------------------------------------------------------
575 * NOTE:In many cases here we are assigning a 'default' parent. In many
576 * cases the parent is selectable. The get/set parent calls will also
579 * Many some clocks say always_enabled, but they can be auto idled for
580 * power savings. They will always be available upon clock request.
582 * Several sources are given initial rates which may be wrong, this will
583 * be fixed up in the init func.
585 * Things are broadly separated below by clock domains. It is
586 * noteworthy that most periferals have dependencies on multiple clock
587 * domains. Many get their interface clocks from the L4 domain, but get
588 * functional clocks from fixed sources or other core domain derived
590 *-------------------------------------------------------------------------*/
592 /* Base external input clocks */
593 static struct clk func_32k_ck = {
594 .name = "func_32k_ck",
596 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
597 RATE_FIXED | ALWAYS_ENABLED,
600 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
601 static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
603 .rate = 26000000, /* fixed up in clock init */
604 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
605 RATE_FIXED | RATE_PROPAGATES,
608 /* With out modem likely 12MHz, with modem likely 13MHz */
609 static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
610 .name = "sys_ck", /* ~ ref_clk also */
613 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
614 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
615 .rate_offset = OMAP_SYSCLKDIV_SHIFT, /* sysclkdiv 1 or 2, already handled or no boot */
616 .recalc = &omap2_sys_clk_recalc,
619 static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
622 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
623 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
624 .recalc = &omap2_propagate_rate,
628 * Analog domain root source clocks
631 /* dpll_ck, is broken out in to special cases through clksel */
632 static struct clk dpll_ck = {
634 .parent = &sys_ck, /* Can be func_32k also */
635 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
636 RATE_PROPAGATES | RATE_CKCTL | CM_PLL_SEL1,
637 .recalc = &omap2_clksel_recalc,
640 static struct clk apll96_ck = {
644 .flags = CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X |
645 RATE_FIXED | RATE_PROPAGATES,
646 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
647 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
648 .recalc = &omap2_propagate_rate,
651 static struct clk apll54_ck = {
655 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
656 RATE_FIXED | RATE_PROPAGATES,
657 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
658 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
659 .recalc = &omap2_propagate_rate,
663 * PRCM digital base sources
665 static struct clk func_54m_ck = {
666 .name = "func_54m_ck",
667 .parent = &apll54_ck, /* can also be alt_clk */
669 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
670 RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
671 .src_offset = OMAP24XX_54M_SOURCE_SHIFT,
672 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
673 .enable_bit = PARENT_CONTROLS_CLOCK,
674 .recalc = &omap2_propagate_rate,
677 static struct clk core_ck = {
679 .parent = &dpll_ck, /* can also be 32k */
680 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
681 ALWAYS_ENABLED | RATE_PROPAGATES,
682 .recalc = &omap2_propagate_rate,
685 static struct clk func_96m_ck = {
686 .name = "func_96m_ck",
687 .parent = &apll96_ck,
689 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
690 RATE_FIXED | RATE_PROPAGATES,
691 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
692 .enable_bit = PARENT_CONTROLS_CLOCK,
693 .recalc = &omap2_propagate_rate,
696 static struct clk func_48m_ck = {
697 .name = "func_48m_ck",
698 .parent = &apll96_ck, /* 96M or Alt */
700 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
701 RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
702 .src_offset = OMAP24XX_48M_SOURCE_SHIFT,
703 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
704 .enable_bit = PARENT_CONTROLS_CLOCK,
705 .recalc = &omap2_propagate_rate,
708 static struct clk func_12m_ck = {
709 .name = "func_12m_ck",
710 .parent = &func_48m_ck,
712 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
713 RATE_FIXED | RATE_PROPAGATES,
714 .recalc = &omap2_propagate_rate,
715 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
716 .enable_bit = PARENT_CONTROLS_CLOCK,
719 /* Secure timer, only available in secure mode */
720 static struct clk wdt1_osc_ck = {
721 .name = "ck_wdt1_osc",
723 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
724 .recalc = &omap2_followparent_recalc,
727 static struct clk sys_clkout = {
728 .name = "sys_clkout",
729 .parent = &func_54m_ck,
731 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
732 CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
733 .src_offset = OMAP24XX_CLKOUT_SOURCE_SHIFT,
734 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
735 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
736 .rate_offset = OMAP24XX_CLKOUT_DIV_SHIFT,
737 .recalc = &omap2_clksel_recalc,
740 /* In 2430, new in 2420 ES2 */
741 static struct clk sys_clkout2 = {
742 .name = "sys_clkout2",
743 .parent = &func_54m_ck,
745 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
746 CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
747 .src_offset = OMAP2420_CLKOUT2_SOURCE_SHIFT,
748 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
749 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
750 .rate_offset = OMAP2420_CLKOUT2_DIV_SHIFT,
751 .recalc = &omap2_clksel_recalc,
754 static struct clk emul_ck = {
756 .parent = &func_54m_ck,
757 .flags = CLOCK_IN_OMAP242X,
758 .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL,
759 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
760 .recalc = &omap2_propagate_rate,
768 * INT_M_FCLK, INT_M_I_CLK
770 * - Individual clocks are hardware managed.
771 * - Base divider comes from: CM_CLKSEL_MPU
774 static struct clk mpu_ck = { /* Control cpu */
777 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL |
778 ALWAYS_ENABLED | CM_MPU_SEL1 | DELAYED_APP |
779 CONFIG_PARTICIPANT | RATE_PROPAGATES,
780 .rate_offset = OMAP24XX_CLKSEL_MPU_SHIFT, /* bits 0-4 */
781 .recalc = &omap2_clksel_recalc,
785 * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
787 * 2430: IVA2.1_FCLK, IVA2.1_ICLK
788 * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
790 static struct clk iva2_1_fck = {
791 .name = "iva2_1_fck",
793 .flags = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
794 DELAYED_APP | RATE_PROPAGATES |
796 .rate_offset = OMAP24XX_CLKSEL_DSP_SHIFT,
797 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
798 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
799 .recalc = &omap2_clksel_recalc,
802 static struct clk iva2_1_ick = {
803 .name = "iva2_1_ick",
804 .parent = &iva2_1_fck,
805 .flags = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
806 DELAYED_APP | CONFIG_PARTICIPANT,
807 .rate_offset = OMAP24XX_CLKSEL_DSP_IF_SHIFT,
808 .recalc = &omap2_clksel_recalc,
812 * Won't be too specific here. The core clock comes into this block
813 * it is divided then tee'ed. One branch goes directly to xyz enable
814 * controls. The other branch gets further divided by 2 then possibly
815 * routed into a synchronizer and out of clocks abc.
817 static struct clk dsp_fck = {
820 .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
821 DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
822 .rate_offset = OMAP24XX_CLKSEL_DSP_SHIFT,
823 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
824 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
825 .recalc = &omap2_clksel_recalc,
828 static struct clk dsp_ick = {
829 .name = "dsp_ick", /* apparently ipi and isp */
831 .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
832 DELAYED_APP | CONFIG_PARTICIPANT,
833 .rate_offset = OMAP24XX_CLKSEL_DSP_IF_SHIFT,
834 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
835 .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
836 .recalc = &omap2_clksel_recalc,
839 static struct clk iva1_ifck = {
842 .flags = CLOCK_IN_OMAP242X | CM_DSP_SEL1 | RATE_CKCTL |
843 CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
844 .rate_offset = OMAP2420_CLKSEL_IVA_SHIFT,
845 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
846 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
847 .recalc = &omap2_clksel_recalc,
850 /* IVA1 mpu/int/i/f clocks are /2 of parent */
851 static struct clk iva1_mpu_int_ifck = {
852 .name = "iva1_mpu_int_ifck",
853 .parent = &iva1_ifck,
854 .flags = CLOCK_IN_OMAP242X,
855 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
856 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
857 .recalc = &omap2_clksel_recalc,
862 * L3 clocks are used for both interface and functional clocks to
863 * multiple entities. Some of these clocks are completely managed
864 * by hardware, and some others allow software control. Hardware
865 * managed ones general are based on directly CLK_REQ signals and
866 * various auto idle settings. The functional spec sets many of these
867 * as 'tie-high' for their enables.
870 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
875 * GPMC memories and SDRC have timing and clock sensitive registers which
876 * may very well need notification when the clock changes. Currently for low
877 * operating points, these are taken care of in sleep.S.
879 static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
880 .name = "core_l3_ck",
882 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
883 RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
884 DELAYED_APP | CONFIG_PARTICIPANT |
886 .rate_offset = OMAP24XX_CLKSEL_L3_SHIFT,
887 .recalc = &omap2_clksel_recalc,
890 static struct clk usb_l4_ick = { /* FS-USB interface clock */
891 .name = "usb_l4_ick",
892 .parent = &core_l3_ck,
893 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
894 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP |
896 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
897 .enable_bit = OMAP24XX_EN_USB_SHIFT,
898 .rate_offset = OMAP24XX_CLKSEL_USB_SHIFT,
899 .recalc = &omap2_clksel_recalc,
903 * SSI is in L3 management domain, its direct parent is core not l3,
904 * many core power domain entities are grouped into the L3 clock
906 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
908 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
910 static struct clk ssi_ssr_sst_fck = {
913 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
914 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
915 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), /* bit 1 */
916 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
917 .rate_offset = OMAP24XX_CLKSEL_SSI_SHIFT,
918 .recalc = &omap2_clksel_recalc,
925 * GFX_CG1(2d), GFX_CG2(3d)
927 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
928 * The 2d and 3d clocks run at a hardware determined
929 * divided value of fclk.
932 static struct clk gfx_3d_fck = {
933 .name = "gfx_3d_fck",
934 .parent = &core_l3_ck,
935 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
936 RATE_CKCTL | CM_GFX_SEL1,
937 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
938 .enable_bit = OMAP24XX_EN_3D_SHIFT,
939 .rate_offset = OMAP_CLKSEL_GFX_SHIFT,
940 .recalc = &omap2_clksel_recalc,
943 static struct clk gfx_2d_fck = {
944 .name = "gfx_2d_fck",
945 .parent = &core_l3_ck,
946 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
947 RATE_CKCTL | CM_GFX_SEL1,
948 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
949 .enable_bit = OMAP24XX_EN_2D_SHIFT,
950 .rate_offset = OMAP_CLKSEL_GFX_SHIFT,
951 .recalc = &omap2_clksel_recalc,
954 static struct clk gfx_ick = {
955 .name = "gfx_ick", /* From l3 */
956 .parent = &core_l3_ck,
957 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
958 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), /* bit 0 */
959 .enable_bit = OMAP_EN_GFX_SHIFT,
960 .recalc = &omap2_followparent_recalc,
964 * Modem clock domain (2430)
969 static struct clk mdm_ick = { /* used both as a ick and fck */
972 .flags = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_MODEM_SEL1 |
973 DELAYED_APP | CONFIG_PARTICIPANT,
974 .rate_offset = OMAP2430_CLKSEL_MDM_SHIFT,
975 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
976 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
977 .recalc = &omap2_clksel_recalc,
980 static struct clk mdm_osc_ck = {
981 .name = "mdm_osc_ck",
984 .flags = CLOCK_IN_OMAP243X | RATE_FIXED,
985 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, OMAP24XX_CM_FCLKEN),
986 .enable_bit = OMAP2430_EN_OSC_SHIFT,
987 .recalc = &omap2_followparent_recalc,
991 * L4 clock management domain
993 * This domain contains lots of interface clocks from the L4 interface, some
994 * functional clocks. Fixed APLL functional source clocks are managed in
997 static struct clk l4_ck = { /* used both as an ick and fck */
999 .parent = &core_l3_ck,
1000 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1001 RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
1002 DELAYED_APP | RATE_PROPAGATES,
1003 .rate_offset = OMAP24XX_CLKSEL_L4_SHIFT,
1004 .recalc = &omap2_clksel_recalc,
1007 static struct clk ssi_l4_ick = {
1008 .name = "ssi_l4_ick",
1010 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1011 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), /* bit 1 */
1012 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1013 .recalc = &omap2_followparent_recalc,
1019 * DSS_L4_ICLK, DSS_L3_ICLK,
1020 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1022 * DSS is both initiator and target.
1024 static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
1026 .parent = &l4_ck, /* really both l3 and l4 */
1027 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1028 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1029 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
1030 .recalc = &omap2_followparent_recalc,
1033 static struct clk dss1_fck = {
1035 .parent = &core_ck, /* Core or sys */
1036 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1037 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
1038 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1039 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
1040 .rate_offset = OMAP24XX_CLKSEL_DSS1_SHIFT,
1041 .src_offset = OMAP24XX_CLKSEL_DSS1_SHIFT,
1042 .recalc = &omap2_clksel_recalc,
1045 static struct clk dss2_fck = { /* Alt clk used in power management */
1047 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
1048 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1049 RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED |
1051 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1052 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
1053 .src_offset = OMAP24XX_CLKSEL_DSS2_SHIFT,
1054 .recalc = &omap2_followparent_recalc,
1057 static struct clk dss_54m_fck = { /* Alt clk used in power management */
1058 .name = "dss_54m_fck", /* 54m tv clk */
1059 .parent = &func_54m_ck,
1060 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1061 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1062 .enable_bit = OMAP24XX_EN_TV_SHIFT,
1063 .recalc = &omap2_followparent_recalc,
1067 * CORE power domain ICLK & FCLK defines.
1068 * Many of the these can have more than one possible parent. Entries
1069 * here will likely have an L4 interface parent, and may have multiple
1070 * functional clock parents.
1072 static struct clk gpt1_ick = {
1075 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1076 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), /* Bit0 */
1077 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
1078 .recalc = &omap2_followparent_recalc,
1081 static struct clk gpt1_fck = {
1083 .parent = &func_32k_ck,
1084 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1086 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN), /* Bit0 */
1087 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
1088 .src_offset = OMAP24XX_CLKSEL_GPT1_SHIFT,
1089 .recalc = &omap2_followparent_recalc,
1092 static struct clk gpt2_ick = {
1095 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1096 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), /* Bit4 */
1097 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
1098 .recalc = &omap2_followparent_recalc,
1101 static struct clk gpt2_fck = {
1103 .parent = &func_32k_ck,
1104 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1106 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1107 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
1108 .src_offset = OMAP24XX_CLKSEL_GPT2_SHIFT,
1109 .recalc = &omap2_followparent_recalc,
1112 static struct clk gpt3_ick = {
1115 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1116 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), /* Bit5 */
1117 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
1118 .recalc = &omap2_followparent_recalc,
1121 static struct clk gpt3_fck = {
1123 .parent = &func_32k_ck,
1124 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1126 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1127 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
1128 .src_offset = OMAP24XX_CLKSEL_GPT3_SHIFT,
1129 .recalc = &omap2_followparent_recalc,
1132 static struct clk gpt4_ick = {
1135 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1136 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), /* Bit6 */
1137 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
1138 .recalc = &omap2_followparent_recalc,
1141 static struct clk gpt4_fck = {
1143 .parent = &func_32k_ck,
1144 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1146 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1147 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
1148 .src_offset = OMAP24XX_CLKSEL_GPT4_SHIFT,
1149 .recalc = &omap2_followparent_recalc,
1152 static struct clk gpt5_ick = {
1155 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1156 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), /* Bit7 */
1157 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
1158 .recalc = &omap2_followparent_recalc,
1161 static struct clk gpt5_fck = {
1163 .parent = &func_32k_ck,
1164 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1166 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1167 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
1168 .src_offset = OMAP24XX_CLKSEL_GPT5_SHIFT,
1169 .recalc = &omap2_followparent_recalc,
1172 static struct clk gpt6_ick = {
1175 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1176 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
1177 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), /* bit8 */
1178 .recalc = &omap2_followparent_recalc,
1181 static struct clk gpt6_fck = {
1183 .parent = &func_32k_ck,
1184 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1186 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1187 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
1188 .src_offset = OMAP24XX_CLKSEL_GPT6_SHIFT,
1189 .recalc = &omap2_followparent_recalc,
1192 static struct clk gpt7_ick = {
1195 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1196 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), /* bit9 */
1197 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1198 .recalc = &omap2_followparent_recalc,
1201 static struct clk gpt7_fck = {
1203 .parent = &func_32k_ck,
1204 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1206 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1207 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1208 .src_offset = OMAP24XX_CLKSEL_GPT7_SHIFT,
1209 .recalc = &omap2_followparent_recalc,
1212 static struct clk gpt8_ick = {
1215 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1216 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), /* bit10 */
1217 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1218 .recalc = &omap2_followparent_recalc,
1221 static struct clk gpt8_fck = {
1223 .parent = &func_32k_ck,
1224 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1226 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1227 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1228 .src_offset = OMAP24XX_CLKSEL_GPT8_SHIFT,
1229 .recalc = &omap2_followparent_recalc,
1232 static struct clk gpt9_ick = {
1235 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1236 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1237 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1238 .recalc = &omap2_followparent_recalc,
1241 static struct clk gpt9_fck = {
1243 .parent = &func_32k_ck,
1244 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1246 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1247 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1248 .src_offset = OMAP24XX_CLKSEL_GPT9_SHIFT,
1249 .recalc = &omap2_followparent_recalc,
1252 static struct clk gpt10_ick = {
1253 .name = "gpt10_ick",
1255 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1256 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1257 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1258 .recalc = &omap2_followparent_recalc,
1261 static struct clk gpt10_fck = {
1262 .name = "gpt10_fck",
1263 .parent = &func_32k_ck,
1264 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1266 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1267 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1268 .src_offset = OMAP24XX_CLKSEL_GPT10_SHIFT,
1269 .recalc = &omap2_followparent_recalc,
1272 static struct clk gpt11_ick = {
1273 .name = "gpt11_ick",
1275 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1276 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1277 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1278 .recalc = &omap2_followparent_recalc,
1281 static struct clk gpt11_fck = {
1282 .name = "gpt11_fck",
1283 .parent = &func_32k_ck,
1284 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1286 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1287 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1288 .src_offset = OMAP24XX_CLKSEL_GPT11_SHIFT,
1289 .recalc = &omap2_followparent_recalc,
1292 static struct clk gpt12_ick = {
1293 .name = "gpt12_ick",
1295 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1296 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), /* bit14 */
1297 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1298 .recalc = &omap2_followparent_recalc,
1301 static struct clk gpt12_fck = {
1302 .name = "gpt12_fck",
1303 .parent = &func_32k_ck,
1304 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1306 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1307 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1308 .src_offset = OMAP24XX_CLKSEL_GPT12_SHIFT,
1309 .recalc = &omap2_followparent_recalc,
1312 /* REVISIT: bit comment below wrong? */
1313 static struct clk mcbsp1_ick = {
1314 .name = "mcbsp1_ick",
1316 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1317 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), /* bit16 */
1318 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1319 .recalc = &omap2_followparent_recalc,
1322 static struct clk mcbsp1_fck = {
1323 .name = "mcbsp1_fck",
1324 .parent = &func_96m_ck,
1325 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1326 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1327 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1328 .recalc = &omap2_followparent_recalc,
1331 static struct clk mcbsp2_ick = {
1332 .name = "mcbsp2_ick",
1334 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1335 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1336 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1337 .recalc = &omap2_followparent_recalc,
1340 static struct clk mcbsp2_fck = {
1341 .name = "mcbsp2_fck",
1342 .parent = &func_96m_ck,
1343 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1344 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1345 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1346 .recalc = &omap2_followparent_recalc,
1349 static struct clk mcbsp3_ick = {
1350 .name = "mcbsp3_ick",
1352 .flags = CLOCK_IN_OMAP243X,
1353 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1354 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1355 .recalc = &omap2_followparent_recalc,
1358 static struct clk mcbsp3_fck = {
1359 .name = "mcbsp3_fck",
1360 .parent = &func_96m_ck,
1361 .flags = CLOCK_IN_OMAP243X,
1362 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1363 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1364 .recalc = &omap2_followparent_recalc,
1367 static struct clk mcbsp4_ick = {
1368 .name = "mcbsp4_ick",
1370 .flags = CLOCK_IN_OMAP243X,
1371 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1372 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1373 .recalc = &omap2_followparent_recalc,
1376 static struct clk mcbsp4_fck = {
1377 .name = "mcbsp4_fck",
1378 .parent = &func_96m_ck,
1379 .flags = CLOCK_IN_OMAP243X,
1380 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1381 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1382 .recalc = &omap2_followparent_recalc,
1385 static struct clk mcbsp5_ick = {
1386 .name = "mcbsp5_ick",
1388 .flags = CLOCK_IN_OMAP243X,
1389 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1390 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1391 .recalc = &omap2_followparent_recalc,
1394 static struct clk mcbsp5_fck = {
1395 .name = "mcbsp5_fck",
1396 .parent = &func_96m_ck,
1397 .flags = CLOCK_IN_OMAP243X,
1398 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1399 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1400 .recalc = &omap2_followparent_recalc,
1403 static struct clk mcspi1_ick = {
1404 .name = "mcspi_ick",
1407 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1408 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1409 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1410 .recalc = &omap2_followparent_recalc,
1413 static struct clk mcspi1_fck = {
1414 .name = "mcspi_fck",
1416 .parent = &func_48m_ck,
1417 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1418 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1419 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1420 .recalc = &omap2_followparent_recalc,
1423 static struct clk mcspi2_ick = {
1424 .name = "mcspi_ick",
1427 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1428 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1429 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1430 .recalc = &omap2_followparent_recalc,
1433 static struct clk mcspi2_fck = {
1434 .name = "mcspi_fck",
1436 .parent = &func_48m_ck,
1437 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1438 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1439 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1440 .recalc = &omap2_followparent_recalc,
1443 static struct clk mcspi3_ick = {
1444 .name = "mcspi_ick",
1447 .flags = CLOCK_IN_OMAP243X,
1448 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1449 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1450 .recalc = &omap2_followparent_recalc,
1453 static struct clk mcspi3_fck = {
1454 .name = "mcspi_fck",
1456 .parent = &func_48m_ck,
1457 .flags = CLOCK_IN_OMAP243X,
1458 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1459 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1460 .recalc = &omap2_followparent_recalc,
1463 static struct clk uart1_ick = {
1464 .name = "uart1_ick",
1466 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1467 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1468 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1469 .recalc = &omap2_followparent_recalc,
1472 static struct clk uart1_fck = {
1473 .name = "uart1_fck",
1474 .parent = &func_48m_ck,
1475 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1476 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1477 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1478 .recalc = &omap2_followparent_recalc,
1481 static struct clk uart2_ick = {
1482 .name = "uart2_ick",
1484 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1485 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1486 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1487 .recalc = &omap2_followparent_recalc,
1490 static struct clk uart2_fck = {
1491 .name = "uart2_fck",
1492 .parent = &func_48m_ck,
1493 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1494 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1495 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1496 .recalc = &omap2_followparent_recalc,
1499 static struct clk uart3_ick = {
1500 .name = "uart3_ick",
1502 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1503 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1504 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1505 .recalc = &omap2_followparent_recalc,
1508 static struct clk uart3_fck = {
1509 .name = "uart3_fck",
1510 .parent = &func_48m_ck,
1511 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1512 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1513 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1514 .recalc = &omap2_followparent_recalc,
1517 static struct clk gpios_ick = {
1518 .name = "gpios_ick",
1520 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1521 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1522 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1523 .recalc = &omap2_followparent_recalc,
1526 static struct clk gpios_fck = {
1527 .name = "gpios_fck",
1528 .parent = &func_32k_ck,
1529 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1530 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
1531 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1532 .recalc = &omap2_followparent_recalc,
1535 static struct clk mpu_wdt_ick = {
1536 .name = "mpu_wdt_ick",
1538 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1539 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1540 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1541 .recalc = &omap2_followparent_recalc,
1544 static struct clk mpu_wdt_fck = {
1545 .name = "mpu_wdt_fck",
1546 .parent = &func_32k_ck,
1547 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1548 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
1549 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1550 .recalc = &omap2_followparent_recalc,
1553 static struct clk sync_32k_ick = {
1554 .name = "sync_32k_ick",
1556 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1557 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1558 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
1559 .recalc = &omap2_followparent_recalc,
1561 static struct clk wdt1_ick = {
1564 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1565 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1566 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
1567 .recalc = &omap2_followparent_recalc,
1569 static struct clk omapctrl_ick = {
1570 .name = "omapctrl_ick",
1572 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1573 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1574 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
1575 .recalc = &omap2_followparent_recalc,
1577 static struct clk icr_ick = {
1580 .flags = CLOCK_IN_OMAP243X,
1581 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1582 .enable_bit = OMAP2430_EN_ICR_SHIFT,
1583 .recalc = &omap2_followparent_recalc,
1586 static struct clk cam_ick = {
1589 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1590 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1591 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1592 .recalc = &omap2_followparent_recalc,
1595 static struct clk cam_fck = {
1597 .parent = &func_96m_ck,
1598 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1599 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1600 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1601 .recalc = &omap2_followparent_recalc,
1604 static struct clk mailboxes_ick = {
1605 .name = "mailboxes_ick",
1607 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1608 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1609 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1610 .recalc = &omap2_followparent_recalc,
1613 static struct clk wdt4_ick = {
1616 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1617 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1618 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1619 .recalc = &omap2_followparent_recalc,
1622 static struct clk wdt4_fck = {
1624 .parent = &func_32k_ck,
1625 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1626 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1627 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1628 .recalc = &omap2_followparent_recalc,
1631 static struct clk wdt3_ick = {
1634 .flags = CLOCK_IN_OMAP242X,
1635 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1636 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
1637 .recalc = &omap2_followparent_recalc,
1640 static struct clk wdt3_fck = {
1642 .parent = &func_32k_ck,
1643 .flags = CLOCK_IN_OMAP242X,
1644 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1645 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
1646 .recalc = &omap2_followparent_recalc,
1649 static struct clk mspro_ick = {
1650 .name = "mspro_ick",
1652 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1653 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1654 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1655 .recalc = &omap2_followparent_recalc,
1658 static struct clk mspro_fck = {
1659 .name = "mspro_fck",
1660 .parent = &func_96m_ck,
1661 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1662 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1663 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1664 .recalc = &omap2_followparent_recalc,
1667 static struct clk mmc_ick = {
1670 .flags = CLOCK_IN_OMAP242X,
1671 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1672 .enable_bit = OMAP2420_EN_MMC_SHIFT,
1673 .recalc = &omap2_followparent_recalc,
1676 static struct clk mmc_fck = {
1678 .parent = &func_96m_ck,
1679 .flags = CLOCK_IN_OMAP242X,
1680 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1681 .enable_bit = OMAP2420_EN_MMC_SHIFT,
1682 .recalc = &omap2_followparent_recalc,
1685 static struct clk fac_ick = {
1688 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1689 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1690 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1691 .recalc = &omap2_followparent_recalc,
1694 static struct clk fac_fck = {
1696 .parent = &func_12m_ck,
1697 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1698 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1699 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1700 .recalc = &omap2_followparent_recalc,
1703 static struct clk eac_ick = {
1706 .flags = CLOCK_IN_OMAP242X,
1707 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1708 .enable_bit = OMAP2420_EN_EAC_SHIFT,
1709 .recalc = &omap2_followparent_recalc,
1712 static struct clk eac_fck = {
1714 .parent = &func_96m_ck,
1715 .flags = CLOCK_IN_OMAP242X,
1716 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1717 .enable_bit = OMAP2420_EN_EAC_SHIFT,
1718 .recalc = &omap2_followparent_recalc,
1721 static struct clk hdq_ick = {
1724 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1725 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1726 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1727 .recalc = &omap2_followparent_recalc,
1730 static struct clk hdq_fck = {
1732 .parent = &func_12m_ck,
1733 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1734 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1735 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1736 .recalc = &omap2_followparent_recalc,
1739 static struct clk i2c2_ick = {
1743 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1744 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1745 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1746 .recalc = &omap2_followparent_recalc,
1749 static struct clk i2c2_fck = {
1752 .parent = &func_12m_ck,
1753 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1754 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1755 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1756 .recalc = &omap2_followparent_recalc,
1759 static struct clk i2chs2_fck = {
1760 .name = "i2chs_fck",
1762 .parent = &func_96m_ck,
1763 .flags = CLOCK_IN_OMAP243X,
1764 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1765 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
1766 .recalc = &omap2_followparent_recalc,
1769 static struct clk i2c1_ick = {
1773 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1774 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1775 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
1776 .recalc = &omap2_followparent_recalc,
1779 static struct clk i2c1_fck = {
1782 .parent = &func_12m_ck,
1783 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1784 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1785 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
1786 .recalc = &omap2_followparent_recalc,
1789 static struct clk i2chs1_fck = {
1790 .name = "i2chs_fck",
1792 .parent = &func_96m_ck,
1793 .flags = CLOCK_IN_OMAP243X,
1794 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1795 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
1796 .recalc = &omap2_followparent_recalc,
1799 static struct clk vlynq_ick = {
1800 .name = "vlynq_ick",
1801 .parent = &core_l3_ck,
1802 .flags = CLOCK_IN_OMAP242X,
1803 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1804 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
1805 .recalc = &omap2_followparent_recalc,
1808 static struct clk vlynq_fck = {
1809 .name = "vlynq_fck",
1810 .parent = &func_96m_ck,
1811 .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
1812 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1813 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
1814 .src_offset = OMAP2420_CLKSEL_VLYNQ_SHIFT,
1815 .recalc = &omap2_clksel_recalc,
1818 static struct clk sdrc_ick = {
1821 .flags = CLOCK_IN_OMAP243X,
1822 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP2430_CM_ICLKEN3),
1823 .enable_bit = OMAP2430_EN_SDRC_SHIFT,
1824 .recalc = &omap2_followparent_recalc,
1827 static struct clk des_ick = {
1830 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1831 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1832 .enable_bit = OMAP24XX_EN_DES_SHIFT,
1833 .recalc = &omap2_followparent_recalc,
1836 static struct clk sha_ick = {
1839 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1840 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1841 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
1842 .recalc = &omap2_followparent_recalc,
1845 static struct clk rng_ick = {
1848 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1849 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1850 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
1851 .recalc = &omap2_followparent_recalc,
1854 static struct clk aes_ick = {
1857 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1858 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1859 .enable_bit = OMAP24XX_EN_AES_SHIFT,
1860 .recalc = &omap2_followparent_recalc,
1863 static struct clk pka_ick = {
1866 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1867 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1868 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
1869 .recalc = &omap2_followparent_recalc,
1872 static struct clk usb_fck = {
1874 .parent = &func_48m_ck,
1875 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1876 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1877 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1878 .recalc = &omap2_followparent_recalc,
1881 static struct clk usbhs_ick = {
1882 .name = "usbhs_ick",
1883 .parent = &core_l3_ck,
1884 .flags = CLOCK_IN_OMAP243X,
1885 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1886 .enable_bit = OMAP2430_EN_USBHS_SHIFT,
1887 .recalc = &omap2_followparent_recalc,
1890 static struct clk mmchs1_ick = {
1891 .name = "mmchs1_ick",
1893 .flags = CLOCK_IN_OMAP243X,
1894 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1895 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
1896 .recalc = &omap2_followparent_recalc,
1899 static struct clk mmchs1_fck = {
1900 .name = "mmchs1_fck",
1901 .parent = &func_96m_ck,
1902 .flags = CLOCK_IN_OMAP243X,
1903 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1904 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
1905 .recalc = &omap2_followparent_recalc,
1908 static struct clk mmchs2_ick = {
1909 .name = "mmchs2_ick",
1911 .flags = CLOCK_IN_OMAP243X,
1912 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1913 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
1914 .recalc = &omap2_followparent_recalc,
1917 static struct clk mmchs2_fck = {
1918 .name = "mmchs2_fck",
1919 .parent = &func_96m_ck,
1920 .flags = CLOCK_IN_OMAP243X,
1921 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1922 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
1923 .recalc = &omap2_followparent_recalc,
1926 static struct clk gpio5_ick = {
1927 .name = "gpio5_ick",
1929 .flags = CLOCK_IN_OMAP243X,
1930 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1931 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
1932 .recalc = &omap2_followparent_recalc,
1935 static struct clk gpio5_fck = {
1936 .name = "gpio5_fck",
1937 .parent = &func_32k_ck,
1938 .flags = CLOCK_IN_OMAP243X,
1939 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1940 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
1941 .recalc = &omap2_followparent_recalc,
1944 static struct clk mdm_intc_ick = {
1945 .name = "mdm_intc_ick",
1947 .flags = CLOCK_IN_OMAP243X,
1948 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1949 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
1950 .recalc = &omap2_followparent_recalc,
1953 static struct clk mmchsdb1_fck = {
1954 .name = "mmchsdb1_fck",
1955 .parent = &func_32k_ck,
1956 .flags = CLOCK_IN_OMAP243X,
1957 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1958 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
1959 .recalc = &omap2_followparent_recalc,
1962 static struct clk mmchsdb2_fck = {
1963 .name = "mmchsdb2_fck",
1964 .parent = &func_32k_ck,
1965 .flags = CLOCK_IN_OMAP243X,
1966 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1967 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
1968 .recalc = &omap2_followparent_recalc,
1972 * This clock is a composite clock which does entire set changes then
1973 * forces a rebalance. It keys on the MPU speed, but it really could
1974 * be any key speed part of a set in the rate table.
1976 * to really change a set, you need memory table sets which get changed
1977 * in sram, pre-notifiers & post notifiers, changing the top set, without
1978 * having low level display recalc's won't work... this is why dpm notifiers
1979 * work, isr's off, walk a list of clocks already _off_ and not messing with
1982 * This clock should have no parent. It embodies the entire upper level
1983 * active set. A parent will mess up some of the init also.
1985 static struct clk virt_prcm_set = {
1986 .name = "virt_prcm_set",
1987 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1988 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
1989 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
1990 .recalc = &omap2_mpu_recalc, /* sets are keyed on mpu rate */
1991 .set_rate = &omap2_select_table_rate,
1992 .round_rate = &omap2_round_to_table_rate,
1995 static struct clk *onchip_clks[] = {
1996 /* external root sources */
2001 /* internal analog sources */
2005 /* internal prcm root sources */
2015 /* mpu domain clocks */
2017 /* dsp domain clocks */
2018 &iva2_1_fck, /* 2430 */
2020 &dsp_ick, /* 2420 */
2024 /* GFX domain clocks */
2028 /* Modem domain clocks */
2031 /* DSS domain clocks */
2036 /* L3 domain clocks */
2040 /* L4 domain clocks */
2041 &l4_ck, /* used as both core_l4 and wu_l4 */
2043 /* virtual meta-group clock */
2045 /* general l4 interface ck, multi-parent functional clk */