arch/arm/mach-omap2/clock.h

   1 /*
   2  *  linux/arch/arm/mach-omap24xx/clock.h
   3  *
   4  *  Copyright (C) 2005 Texas Instruments Inc.
   5  *  Richard Woodruff <r-woodruff2@ti.com>
   6  *  Created for OMAP2.
   7  *
   8  *  Copyright (C) 2004 Nokia corporation
   9  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  10  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
  18 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
  19
  20 #include "prm.h"
  21 #include "cm.h"
  22 #include "prm_regbits_24xx.h"
  23 #include "cm_regbits_24xx.h"
  24
  25 static void omap2_sys_clk_recalc(struct clk * clk);
  26 static void omap2_clksel_recalc(struct clk * clk);
  27 static void omap2_table_mpu_recalc(struct clk *clk);
  28 static int omap2_select_table_rate(struct clk * clk, unsigned long rate);
  29 static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate);
  30 static void omap2_clk_disable(struct clk *clk);
  31 static void omap2_sys_clk_recalc(struct clk * clk);
  32 static void omap2_init_clksel_parent(struct clk *clk);
  33 static u32 omap2_clksel_get_divisor(struct clk *clk);
  34 static u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val);
  35 static u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
  36 static void omap2_dpll_recalc(struct clk *clk);
  37 static void omap2_fixed_divisor_recalc(struct clk *clk);
  38
  39 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  40  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  41  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  42  */
  43 struct prcm_config {
  44         unsigned long xtal_speed;       /* crystal rate */
  45         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  46         unsigned long mpu_speed;        /* speed of MPU */
  47         unsigned long cm_clksel_mpu;    /* mpu divider */
  48         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  49         unsigned long cm_clksel_gfx;    /* gfx dividers */
  50         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  51         unsigned long cm_clksel1_pll;   /* m,n */
  52         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  53         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  54         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  55         unsigned char flags;
  56 };
  57
  58 /* REVISIT: CM_PLL_SEL2 unused */
  59
  60 /* Mask for clksel which support parent settign in set_rate */
  61 #define SRC_SEL_MASK (CM_CORE_SEL1 | CM_CORE_SEL2 | CM_WKUP_SEL1 | \
  62                         CM_PLL_SEL1 | CM_PLL_SEL2 | CM_SYSCLKOUT_SEL1)
  63
  64 /* Mask for clksel regs which support rate operations */
  65 #define SRC_RATE_SEL_MASK (SRC_SEL_MASK | CM_MPU_SEL1 | CM_DSP_SEL1 | \
  66                         CM_GFX_SEL1 | CM_MODEM_SEL1)
  67
  68 /*
  69  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  70  * These configurations are characterized by voltage and speed for clocks.
  71  * The device is only validated for certain combinations. One way to express
  72  * these combinations is via the 'ratio's' which the clocks operate with
  73  * respect to each other. These ratio sets are for a given voltage/DPLL
  74  * setting. All configurations can be described by a DPLL setting and a ratio
  75  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  76  *
  77  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  78  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  79  * 2430 (iva2.1, NOdsp, mdm)
  80  */
  81
  82 /* Core fields for cm_clksel, not ratio governed */
  83 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  84 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  85 #define RX_CLKSEL_SSI                   (0x5 << 20)
  86
  87 /*-------------------------------------------------------------------------
  88  * Voltage/DPLL ratios
  89  *-------------------------------------------------------------------------*/
  90
  91 /* 2430 Ratio's, 2430-Ratio Config 1 */
  92 #define R1_CLKSEL_L3                    (4 << 0)
  93 #define R1_CLKSEL_L4                    (2 << 5)
  94 #define R1_CLKSEL_USB                   (4 << 25)
  95 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
  96                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  97                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
  98 #define R1_CLKSEL_MPU                   (2 << 0)
  99 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
 100 #define R1_CLKSEL_DSP                   (2 << 0)
 101 #define R1_CLKSEL_DSP_IF                (2 << 5)
 102 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
 103 #define R1_CLKSEL_GFX                   (2 << 0)
 104 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
 105 #define R1_CLKSEL_MDM                   (4 << 0)
 106 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
 107
 108 /* 2430-Ratio Config 2 */
 109 #define R2_CLKSEL_L3                    (6 << 0)
 110 #define R2_CLKSEL_L4                    (2 << 5)
 111 #define R2_CLKSEL_USB                   (2 << 25)
 112 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
 113                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 114                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
 115 #define R2_CLKSEL_MPU                   (2 << 0)
 116 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 117 #define R2_CLKSEL_DSP                   (2 << 0)
 118 #define R2_CLKSEL_DSP_IF                (3 << 5)
 119 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 120 #define R2_CLKSEL_GFX                   (2 << 0)
 121 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 122 #define R2_CLKSEL_MDM                   (6 << 0)
 123 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 124
 125 /* 2430-Ratio Bootm (BYPASS) */
 126 #define RB_CLKSEL_L3                    (1 << 0)
 127 #define RB_CLKSEL_L4                    (1 << 5)
 128 #define RB_CLKSEL_USB                   (1 << 25)
 129 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 130                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 131                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 132 #define RB_CLKSEL_MPU                   (1 << 0)
 133 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 134 #define RB_CLKSEL_DSP                   (1 << 0)
 135 #define RB_CLKSEL_DSP_IF                (1 << 5)
 136 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 137 #define RB_CLKSEL_GFX                   (1 << 0)
 138 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 139 #define RB_CLKSEL_MDM                   (1 << 0)
 140 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 141
 142 /* 2420 Ratio Equivalents */
 143 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 144 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 145
 146 /* 2420-PRCM III 532MHz core */
 147 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 148 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 149 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 150 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 151                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 152                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 153                                         RIII_CLKSEL_L3
 154 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 155 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 156 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 157 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 158 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 159 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 160 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 161 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 162                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 163                                         RIII_CLKSEL_DSP
 164 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 165 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 166
 167 /* 2420-PRCM II 600MHz core */
 168 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 169 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 170 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 171 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 172                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 173                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 174                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 175 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 176 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 177 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 178 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 179 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 180 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 181 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 182 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 183                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 184                                         RII_CLKSEL_DSP
 185 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 186 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 187
 188 /* 2420-PRCM I 660MHz core */
 189 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 190 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 191 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 192 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 193                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 194                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 195                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 196 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 197 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 198 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 199 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 200 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 201 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 202 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 203 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 204                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 205                                         RI_CLKSEL_DSP
 206 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 207 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 208
 209 /* 2420-PRCM VII (boot) */
 210 #define RVII_CLKSEL_L3                  (1 << 0)
 211 #define RVII_CLKSEL_L4                  (1 << 5)
 212 #define RVII_CLKSEL_DSS1                (1 << 8)
 213 #define RVII_CLKSEL_DSS2                (0 << 13)
 214 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 215 #define RVII_CLKSEL_SSI                 (1 << 20)
 216 #define RVII_CLKSEL_USB                 (1 << 25)
 217
 218 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 219                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 220                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 221
 222 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 223 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 224
 225 #define RVII_CLKSEL_DSP                 (1 << 0)
 226 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 227 #define RVII_SYNC_DSP                   (0 << 7)
 228 #define RVII_CLKSEL_IVA                 (1 << 8)
 229 #define RVII_SYNC_IVA                   (0 << 13)
 230 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 231                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 232
 233 #define RVII_CLKSEL_GFX                 (1 << 0)
 234 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 235
 236 /*-------------------------------------------------------------------------
 237  * 2430 Target modes: Along with each configuration the CPU has several
 238  * modes which goes along with them. Modes mainly are the addition of
 239  * describe DPLL combinations to go along with a ratio.
 240  *-------------------------------------------------------------------------*/
 241
 242 /* Hardware governed */
 243 #define MX_48M_SRC                      (0 << 3)
 244 #define MX_54M_SRC                      (0 << 5)
 245 #define MX_APLLS_CLIKIN_12              (3 << 23)
 246 #define MX_APLLS_CLIKIN_13              (2 << 23)
 247 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 248
 249 /*
 250  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 251  * #2   (ratio1) baseport-target
 252  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 253  */
 254 #define M5A_DPLL_MULT_12                (133 << 12)
 255 #define M5A_DPLL_DIV_12                 (5 << 8)
 256 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 257                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 258                                         MX_APLLS_CLIKIN_12
 259 #define M5A_DPLL_MULT_13                (266 << 12)
 260 #define M5A_DPLL_DIV_13                 (12 << 8)
 261 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 262                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 263                                         MX_APLLS_CLIKIN_13
 264 #define M5A_DPLL_MULT_19                (180 << 12)
 265 #define M5A_DPLL_DIV_19                 (12 << 8)
 266 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 267                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 268                                         MX_APLLS_CLIKIN_19_2
 269 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 270 #define M5B_DPLL_MULT_12                (50 << 12)
 271 #define M5B_DPLL_DIV_12                 (2 << 8)
 272 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 273                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 274                                         MX_APLLS_CLIKIN_12
 275 #define M5B_DPLL_MULT_13                (200 << 12)
 276 #define M5B_DPLL_DIV_13                 (12 << 8)
 277
 278 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 279                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 280                                         MX_APLLS_CLIKIN_13
 281 #define M5B_DPLL_MULT_19                (125 << 12)
 282 #define M5B_DPLL_DIV_19                 (31 << 8)
 283 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 284                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 285                                         MX_APLLS_CLIKIN_19_2
 286 /*
 287  * #4   (ratio2)
 288  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 289  */
 290 #define M3_DPLL_MULT_12                 (55 << 12)
 291 #define M3_DPLL_DIV_12                  (1 << 8)
 292 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 293                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 294                                         MX_APLLS_CLIKIN_12
 295 #define M3_DPLL_MULT_13                 (330 << 12)
 296 #define M3_DPLL_DIV_13                  (12 << 8)
 297 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 298                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 299                                         MX_APLLS_CLIKIN_13
 300 #define M3_DPLL_MULT_19                 (275 << 12)
 301 #define M3_DPLL_DIV_19                  (15 << 8)
 302 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 303                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 304                                         MX_APLLS_CLIKIN_19_2
 305 /* boot (boot) */
 306 #define MB_DPLL_MULT                    (1 << 12)
 307 #define MB_DPLL_DIV                     (0 << 8)
 308 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 309                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 310
 311 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 312                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 313
 314 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 315                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 316
 317 /*
 318  * 2430 - chassis (sedna)
 319  * 165 (ratio1) same as above #2
 320  * 150 (ratio1)
 321  * 133 (ratio2) same as above #4
 322  * 110 (ratio2) same as above #3
 323  * 104 (ratio2)
 324  * boot (boot)
 325  */
 326
 327 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 328 #define MI_DPLL_MULT_12                 (55 << 12)
 329 #define MI_DPLL_DIV_12                  (1 << 8)
 330 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 331                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 332                                         MX_APLLS_CLIKIN_12
 333
 334 /*
 335  * 2420 Equivalent - mode registers
 336  * PRCM II , target DPLL = 2*300MHz = 600MHz
 337  */
 338 #define MII_DPLL_MULT_12                (50 << 12)
 339 #define MII_DPLL_DIV_12                 (1 << 8)
 340 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 341                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 342                                         MX_APLLS_CLIKIN_12
 343 #define MII_DPLL_MULT_13                (300 << 12)
 344 #define MII_DPLL_DIV_13                 (12 << 8)
 345 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 346                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 347                                         MX_APLLS_CLIKIN_13
 348
 349 /* PRCM III target DPLL = 2*266 = 532MHz*/
 350 #define MIII_DPLL_MULT_12               (133 << 12)
 351 #define MIII_DPLL_DIV_12                (5 << 8)
 352 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 353                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 354                                         MX_APLLS_CLIKIN_12
 355 #define MIII_DPLL_MULT_13               (266 << 12)
 356 #define MIII_DPLL_DIV_13                (12 << 8)
 357 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 358                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 359                                         MX_APLLS_CLIKIN_13
 360
 361 /* PRCM VII (boot bypass) */
 362 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 363 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 364
 365 /* High and low operation value */
 366 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 367 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 368
 369 /*
 370  * These represent optimal values for common parts, it won't work for all.
 371  * As long as you scale down, most parameters are still work, they just
 372  * become sub-optimal. The RFR value goes in the opposite direction. If you
 373  * don't adjust it down as your clock period increases the refresh interval
 374  * will not be met. Setting all parameters for complete worst case may work,
 375  * but may cut memory performance by 2x. Due to errata the DLLs need to be
 376  * unlocked and their value needs run time calibration. A dynamic call is
 377  * need for that as no single right value exists acorss production samples.
 378  *
 379  * Only the FULL speed values are given. Current code is such that rate
 380  * changes must be made at DPLLoutx2. The actual value adjustment for low
 381  * frequency operation will be handled by omap_set_performance()
 382  *
 383  * By having the boot loader boot up in the fastest L4 speed available likely
 384  * will result in something which you can switch between.
 385  */
 386 #define V24XX_SDRC_RFR_CTRL_165MHz      (0x00044c00 | 1)
 387 #define V24XX_SDRC_RFR_CTRL_133MHz      (0x0003de00 | 1)
 388 #define V24XX_SDRC_RFR_CTRL_100MHz      (0x0002da01 | 1)
 389 #define V24XX_SDRC_RFR_CTRL_110MHz      (0x0002da01 | 1) /* Need to calc */
 390 #define V24XX_SDRC_RFR_CTRL_BYPASS      (0x00005000 | 1) /* Need to calc */
 391
 392 /* MPU speed defines */
 393 #define S12M    12000000
 394 #define S13M    13000000
 395 #define S19M    19200000
 396 #define S26M    26000000
 397 #define S100M   100000000
 398 #define S133M   133000000
 399 #define S150M   150000000
 400 #define S165M   165000000
 401 #define S200M   200000000
 402 #define S266M   266000000
 403 #define S300M   300000000
 404 #define S330M   330000000
 405 #define S400M   400000000
 406 #define S532M   532000000
 407 #define S600M   600000000
 408 #define S660M   660000000
 409
 410 /*-------------------------------------------------------------------------
 411  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 412  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 413  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 414  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 415  *
 416  * Filling in table based on H4 boards and 2430-SDPs variants available.
 417  * There are quite a few more rates combinations which could be defined.
 418  *
 419  * When multiple values are defined the start up will try and choose the
 420  * fastest one. If a 'fast' value is defined, then automatically, the /2
 421  * one should be included as it can be used.    Generally having more that
 422  * one fast set does not make sense, as static timings need to be changed
 423  * to change the set.    The exception is the bypass setting which is
 424  * availble for low power bypass.
 425  *
 426  * Note: This table needs to be sorted, fastest to slowest.
 427  *-------------------------------------------------------------------------*/
 428 static struct prcm_config rate_table[] = {
 429         /* PRCM I - FAST */
 430         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 431                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 432                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 433                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_165MHz,
 434                 RATE_IN_242X},
 435
 436         /* PRCM II - FAST */
 437         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 438                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 439                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 440                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 441                 RATE_IN_242X},
 442
 443         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 444                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 445                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 446                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 447                 RATE_IN_242X},
 448
 449         /* PRCM III - FAST */
 450         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 451                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 452                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 453                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 454                 RATE_IN_242X},
 455
 456         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 457                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 458                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 459                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 460                 RATE_IN_242X},
 461
 462         /* PRCM II - SLOW */
 463         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 464                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 465                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 466                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 467                 RATE_IN_242X},
 468
 469         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 470                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 471                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 472                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 473                 RATE_IN_242X},
 474
 475         /* PRCM III - SLOW */
 476         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 477                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 478                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 479                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 480                 RATE_IN_242X},
 481
 482         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 483                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 484                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 485                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 486                 RATE_IN_242X},
 487
 488         /* PRCM-VII (boot-bypass) */
 489         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 490                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 491                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 492                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
 493                 RATE_IN_242X},
 494
 495         /* PRCM-VII (boot-bypass) */
 496         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 497                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 498                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 499                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
 500                 RATE_IN_242X},
 501
 502         /* PRCM #3 - ratio2 (ES2) - FAST */
 503         {S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 504                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 505                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 506                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 507                 V24XX_SDRC_RFR_CTRL_110MHz,
 508                 RATE_IN_243X},
 509
 510         /* PRCM #5a - ratio1 - FAST */
 511         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 512                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 513                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 514                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 515                 V24XX_SDRC_RFR_CTRL_133MHz,
 516                 RATE_IN_243X},
 517
 518         /* PRCM #5b - ratio1 - FAST */
 519         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 520                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 521                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 522                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 523                 V24XX_SDRC_RFR_CTRL_100MHz,
 524                 RATE_IN_243X},
 525
 526         /* PRCM #3 - ratio2 (ES2) - SLOW */
 527         {S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 528                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 529                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 530                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 531                 V24XX_SDRC_RFR_CTRL_110MHz,
 532                 RATE_IN_243X},
 533
 534         /* PRCM #5a - ratio1 - SLOW */
 535         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 536                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 537                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 538                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 539                 V24XX_SDRC_RFR_CTRL_133MHz,
 540                 RATE_IN_243X},
 541
 542         /* PRCM #5b - ratio1 - SLOW*/
 543         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 544                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 545                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 546                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 547                 V24XX_SDRC_RFR_CTRL_100MHz,
 548                 RATE_IN_243X},
 549
 550         /* PRCM-boot/bypass */
 551         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 552                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 553                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 554                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 555                 V24XX_SDRC_RFR_CTRL_BYPASS,
 556                 RATE_IN_243X},
 557
 558         /* PRCM-boot/bypass */
 559         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 560                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 561                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 562                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 563                 V24XX_SDRC_RFR_CTRL_BYPASS,
 564                 RATE_IN_243X},
 565
 566         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 567 };
 568
 569 /*-------------------------------------------------------------------------
 570  * 24xx clock tree.
 571  *
 572  * NOTE:In many cases here we are assigning a 'default' parent. In many
 573  *      cases the parent is selectable. The get/set parent calls will also
 574  *      switch sources.
 575  *
 576  *      Many some clocks say always_enabled, but they can be auto idled for
 577  *      power savings. They will always be available upon clock request.
 578  *
 579  *      Several sources are given initial rates which may be wrong, this will
 580  *      be fixed up in the init func.
 581  *
 582  *      Things are broadly separated below by clock domains. It is
 583  *      noteworthy that most periferals have dependencies on multiple clock
 584  *      domains. Many get their interface clocks from the L4 domain, but get
 585  *      functional clocks from fixed sources or other core domain derived
 586  *      clocks.
 587  *-------------------------------------------------------------------------*/
 588
 589 /* Base external input clocks */
 590 static struct clk func_32k_ck = {
 591         .name           = "func_32k_ck",
 592         .rate           = 32000,
 593         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 594                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 595         .recalc         = &propagate_rate,
 596 };
 597
 598 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 599 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 600         .name           = "osc_ck",
 601         .rate           = 26000000,             /* fixed up in clock init */
 602         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 603                                 RATE_FIXED | RATE_PROPAGATES,
 604         .recalc         = &propagate_rate,
 605 };
 606
 607 /* With out modem likely 12MHz, with modem likely 13MHz */
 608 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 609         .name           = "sys_ck",             /* ~ ref_clk also */
 610         .parent         = &osc_ck,
 611         .rate           = 13000000,
 612         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 613                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 614         .rate_offset    = OMAP_SYSCLKDIV_SHIFT, /* sysclkdiv 1 or 2, already handled or no boot */
 615         .recalc         = &omap2_sys_clk_recalc,
 616 };
 617
 618 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 619         .name           = "alt_ck",
 620         .rate           = 54000000,
 621         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 622                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 623         .recalc         = &propagate_rate,
 624 };
 625
 626 /*
 627  * Analog domain root source clocks
 628  */
 629
 630 /* dpll_ck, is broken out in to special cases through clksel */
 631 /* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
 632  * deal with this
 633  */
 634 static struct clk dpll_ck = {
 635         .name           = "dpll_ck",
 636         .parent         = &sys_ck,              /* Can be func_32k also */
 637         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 638                                 RATE_PROPAGATES | RATE_CKCTL | CM_PLL_SEL1 |
 639                                 ALWAYS_ENABLED,
 640         .recalc         = &omap2_dpll_recalc,
 641 };
 642
 643 static struct clk apll96_ck = {
 644         .name           = "apll96_ck",
 645         .parent         = &sys_ck,
 646         .rate           = 96000000,
 647         .flags          = CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X |
 648                                 RATE_FIXED | RATE_PROPAGATES,
 649         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 650         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 651         .recalc         = &propagate_rate,
 652 };
 653
 654 static struct clk apll54_ck = {
 655         .name           = "apll54_ck",
 656         .parent         = &sys_ck,
 657         .rate           = 54000000,
 658         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 659                                 RATE_FIXED | RATE_PROPAGATES,
 660         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 661         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 662         .recalc         = &propagate_rate,
 663 };
 664
 665 /*
 666  * PRCM digital base sources
 667  */
 668
 669 /* func_54m_ck */
 670
 671 static const struct clksel_rate func_54m_apll54_rates[] = {
 672         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 673         { .div = 0 },
 674 };
 675
 676 static const struct clksel_rate func_54m_alt_rates[] = {
 677         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 678         { .div = 0 },
 679 };
 680
 681 static const struct clksel func_54m_clksel[] = {
 682         { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
 683         { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
 684         { .parent = NULL },
 685 };
 686
 687 static struct clk func_54m_ck = {
 688         .name           = "func_54m_ck",
 689         .parent         = &apll54_ck,   /* can also be alt_clk */
 690         .rate           = 54000000,
 691         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 692                                 RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES |
 693                                 PARENT_CONTROLS_CLOCK,
 694         .src_offset     = OMAP24XX_54M_SOURCE_SHIFT,
 695         .init           = &omap2_init_clksel_parent,
 696         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 697         .clksel_mask    = OMAP24XX_54M_SOURCE,
 698         .clksel         = func_54m_clksel,
 699         .recalc         = &propagate_rate,
 700 };
 701
 702 static struct clk core_ck = {
 703         .name           = "core_ck",
 704         .parent         = &dpll_ck,             /* can also be 32k */
 705         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 706                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 707         .recalc         = &followparent_recalc,
 708 };
 709
 710 /* func_96m_ck */
 711 static const struct clksel_rate func_96m_apll96_rates[] = {
 712         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 713         { .div = 0 },
 714 };
 715
 716 static const struct clksel_rate func_96m_alt_rates[] = {
 717         { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
 718         { .div = 0 },
 719 };
 720
 721 static const struct clksel func_96m_clksel[] = {
 722         { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
 723         { .parent = &alt_ck,    .rates = func_96m_alt_rates },
 724         { .parent = NULL }
 725 };
 726
 727 /* The parent of this clock is not selectable on 2420. */
 728 static struct clk func_96m_ck = {
 729         .name           = "func_96m_ck",
 730         .parent         = &apll96_ck,
 731         .rate           = 96000000,
 732         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 733                                 RATE_FIXED | RATE_PROPAGATES |
 734                                 PARENT_CONTROLS_CLOCK,
 735         .init           = &omap2_init_clksel_parent,
 736         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 737         .clksel_mask    = OMAP2430_96M_SOURCE,
 738         .clksel         = func_96m_clksel,
 739         .recalc         = &propagate_rate,
 740 };
 741
 742 /* func_48m_ck */
 743
 744 static const struct clksel_rate func_48m_apll96_rates[] = {
 745         { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 746         { .div = 0 },
 747 };
 748
 749 static const struct clksel_rate func_48m_alt_rates[] = {
 750         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 751         { .div = 0 },
 752 };
 753
 754 static const struct clksel func_48m_clksel[] = {
 755         { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
 756         { .parent = &alt_ck, .rates = func_48m_alt_rates },
 757         { .parent = NULL }
 758 };
 759
 760 static struct clk func_48m_ck = {
 761         .name           = "func_48m_ck",
 762         .parent         = &apll96_ck,    /* 96M or Alt */
 763         .rate           = 48000000,
 764         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 765                                 RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES |
 766                                 PARENT_CONTROLS_CLOCK,
 767         .src_offset     = OMAP24XX_48M_SOURCE_SHIFT,
 768         .init           = &omap2_init_clksel_parent,
 769         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 770         .clksel_mask    = OMAP24XX_48M_SOURCE,
 771         .clksel         = func_48m_clksel,
 772         .recalc         = &propagate_rate,
 773 };
 774
 775 static struct clk func_12m_ck = {
 776         .name           = "func_12m_ck",
 777         .parent         = &func_48m_ck,
 778         .fixed_div      = 4,
 779         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 780                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 781         .recalc         = &omap2_fixed_divisor_recalc,
 782 };
 783
 784 /* Secure timer, only available in secure mode */
 785 static struct clk wdt1_osc_ck = {
 786         .name           = "ck_wdt1_osc",
 787         .parent         = &osc_ck,
 788         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 789         .recalc         = &followparent_recalc,
 790 };
 791
 792 /*
 793  * The common_clkout* clksel_rate structs are common to
 794  * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
 795  * sys_clkout2_* are 2420-only, so the
 796  * clksel_rate flags fields are inaccurate for those clocks. This is
 797  * harmless since access to those clocks are gated by the struct clk
 798  * flags fields, which mark them as 2420-only.
 799  */
 800 static const struct clksel_rate common_clkout_src_core_rates[] = {
 801         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 802         { .div = 0 }
 803 };
 804
 805 static const struct clksel_rate common_clkout_src_sys_rates[] = {
 806         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 807         { .div = 0 }
 808 };
 809
 810 static const struct clksel_rate common_clkout_src_96m_rates[] = {
 811         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 812         { .div = 0 }
 813 };
 814
 815 static const struct clksel_rate common_clkout_src_54m_rates[] = {
 816         { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
 817         { .div = 0 }
 818 };
 819
 820 static const struct clksel common_clkout_src_clksel[] = {
 821         { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
 822         { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
 823         { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
 824         { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
 825         { .parent = NULL }
 826 };
 827
 828 static struct clk sys_clkout_src = {
 829         .name           = "sys_clkout_src",
 830         .parent         = &func_54m_ck,
 831         .rate           = 54000000,
 832         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 833                                 CM_SYSCLKOUT_SEL1 | RATE_CKCTL |
 834                                 RATE_PROPAGATES,
 835         .src_offset     = OMAP24XX_CLKOUT_SOURCE_SHIFT,
 836         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 837         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 838         .init           = &omap2_init_clksel_parent,
 839         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 840         .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
 841         .clksel         = common_clkout_src_clksel,
 842         .recalc         = &propagate_rate,
 843 };
 844
 845 static const struct clksel_rate common_clkout_rates[] = {
 846         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 847         { .div = 2, .val = 1, .flags = RATE_IN_24XX },
 848         { .div = 4, .val = 2, .flags = RATE_IN_24XX },
 849         { .div = 8, .val = 3, .flags = RATE_IN_24XX },
 850         { .div = 16, .val = 4, .flags = RATE_IN_24XX },
 851         { .div = 0 },
 852 };
 853
 854 static const struct clksel sys_clkout_clksel[] = {
 855         { .parent = &sys_clkout_src, .rates = common_clkout_rates },
 856         { .parent = NULL }
 857 };
 858
 859 static struct clk sys_clkout = {
 860         .name           = "sys_clkout",
 861         .parent         = &sys_clkout_src,
 862         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 863                                 CM_SYSCLKOUT_SEL1 | RATE_CKCTL |
 864                                 PARENT_CONTROLS_CLOCK,
 865         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 866         .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
 867         .clksel         = sys_clkout_clksel,
 868         .rate_offset    = OMAP24XX_CLKOUT_DIV_SHIFT,
 869         .recalc         = &omap2_clksel_recalc,
 870 };
 871
 872 /* In 2430, new in 2420 ES2 */
 873 static struct clk sys_clkout2_src = {
 874         .name           = "sys_clkout2_src",
 875         .parent         = &func_54m_ck,
 876         .src_offset     = OMAP2420_CLKOUT2_SOURCE_SHIFT,
 877         .flags          = CLOCK_IN_OMAP242X | CM_SYSCLKOUT_SEL1 | RATE_CKCTL |
 878                                 RATE_PROPAGATES,
 879         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 880         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 881         .init           = &omap2_init_clksel_parent,
 882         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 883         .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
 884         .clksel         = common_clkout_src_clksel,
 885         .recalc         = &propagate_rate,
 886 };
 887
 888 static const struct clksel sys_clkout2_clksel[] = {
 889         { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
 890         { .parent = NULL }
 891 };
 892
 893 /* In 2430, new in 2420 ES2 */
 894 static struct clk sys_clkout2 = {
 895         .name           = "sys_clkout2",
 896         .parent         = &sys_clkout2_src,
 897         .flags          = CLOCK_IN_OMAP242X | CM_SYSCLKOUT_SEL1 | RATE_CKCTL |
 898                                 PARENT_CONTROLS_CLOCK,
 899         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 900         .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
 901         .clksel         = sys_clkout2_clksel,
 902         .rate_offset    = OMAP2420_CLKOUT2_DIV_SHIFT,
 903         .recalc         = &propagate_rate,
 904 };
 905
 906 static struct clk emul_ck = {
 907         .name           = "emul_ck",
 908         .parent         = &func_54m_ck,
 909         .flags          = CLOCK_IN_OMAP242X,
 910         .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL,
 911         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 912         .recalc         = &followparent_recalc,
 913
 914 };
 915
 916 /*
 917  * MPU clock domain
 918  *      Clocks:
 919  *              MPU_FCLK, MPU_ICLK
 920  *              INT_M_FCLK, INT_M_I_CLK
 921  *
 922  * - Individual clocks are hardware managed.
 923  * - Base divider comes from: CM_CLKSEL_MPU
 924  *
 925  */
 926 static const struct clksel_rate mpu_core_rates[] = {
 927         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 928         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 929         { .div = 4, .val = 4, .flags = RATE_IN_242X },
 930         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 931         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 932         { .div = 0 },
 933 };
 934
 935 static const struct clksel mpu_clksel[] = {
 936         { .parent = &core_ck, .rates = mpu_core_rates },
 937         { .parent = NULL }
 938 };
 939
 940 static struct clk mpu_ck = {    /* Control cpu */
 941         .name           = "mpu_ck",
 942         .parent         = &core_ck,
 943         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL |
 944                                 ALWAYS_ENABLED | CM_MPU_SEL1 | DELAYED_APP |
 945                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
 946         .rate_offset    = OMAP24XX_CLKSEL_MPU_SHIFT,    /* bits 0-4 */
 947         .init           = &omap2_init_clksel_parent,
 948         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
 949         .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
 950         .clksel         = mpu_clksel,
 951         .recalc         = &omap2_clksel_recalc,
 952 };
 953
 954 /*
 955  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
 956  * Clocks:
 957  *      2430: IVA2.1_FCLK, IVA2.1_ICLK
 958  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
 959  */
 960 /* XXX Okay, this is dumb.  iva2_1fck and dsp_fck are the same clock.
 961  * they should just be treated as such.
 962  */
 963
 964 /* iva2_1_fck */
 965 static const struct clksel_rate iva2_1_fck_core_rates[] = {
 966         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 967         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 968         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
 969         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
 970         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 971         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 972         { .div = 12, .val = 12, .flags = RATE_IN_242X },
 973         { .div = 0 },
 974 };
 975
 976 static const struct clksel iva2_1_fck_clksel[] = {
 977         { .parent = &core_ck, .rates = iva2_1_fck_core_rates },
 978         { .parent = NULL }
 979 };
 980
 981 static struct clk iva2_1_fck = {
 982         .name           = "iva2_1_fck",
 983         .parent         = &core_ck,
 984         .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
 985                                 DELAYED_APP | RATE_PROPAGATES |
 986                                 CONFIG_PARTICIPANT,
 987         .rate_offset    = OMAP24XX_CLKSEL_DSP_SHIFT,
 988         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 989         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
 990         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
 991         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
 992         .clksel         = iva2_1_fck_clksel,
 993         .recalc         = &omap2_clksel_recalc,
 994 };
 995
 996 /* iva2_1_ick */
 997 static const struct clksel_rate iva2_1_ick_core_rates[] = {
 998         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 999         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1000         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1001         { .div = 0 },
1002 };
1003
1004 static const struct clksel iva2_1_ick_clksel[] = {
1005         { .parent = &core_ck, .rates = iva2_1_ick_core_rates },
1006         { .parent = NULL }
1007 };
1008
1009 static struct clk iva2_1_ick = {
1010         .name           = "iva2_1_ick",
1011         .parent         = &iva2_1_fck,
1012         .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
1013                                 DELAYED_APP | CONFIG_PARTICIPANT,
1014         .rate_offset    = OMAP24XX_CLKSEL_DSP_IF_SHIFT,
1015         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1016         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1017         .clksel         = iva2_1_ick_clksel,
1018         .recalc         = &omap2_clksel_recalc,
1019 };
1020
1021 /*
1022  * Won't be too specific here. The core clock comes into this block
1023  * it is divided then tee'ed. One branch goes directly to xyz enable
1024  * controls. The other branch gets further divided by 2 then possibly
1025  * routed into a synchronizer and out of clocks abc.
1026  */
1027 static const struct clksel_rate dsp_fck_core_rates[] = {
1028         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1029         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1030         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1031         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1032         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1033         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1034         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1035         { .div = 0 },
1036 };
1037
1038 static const struct clksel dsp_fck_clksel[] = {
1039         { .parent = &core_ck, .rates = dsp_fck_core_rates },
1040         { .parent = NULL }
1041 };
1042
1043 static struct clk dsp_fck = {
1044         .name           = "dsp_fck",
1045         .parent         = &core_ck,
1046         .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
1047                         DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
1048         .rate_offset    = OMAP24XX_CLKSEL_DSP_SHIFT,
1049         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
1050         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1051         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1052         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
1053         .clksel         = dsp_fck_clksel,
1054         .recalc         = &omap2_clksel_recalc,
1055 };
1056
1057 static const struct clksel_rate dsp_ick_core_rates[] = {
1058         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1059         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1060         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1061         { .div = 0 },
1062 };
1063
1064 static const struct clksel dsp_ick_clksel[] = {
1065         { .parent = &core_ck, .rates = dsp_ick_core_rates },
1066         { .parent = NULL }
1067 };
1068
1069 static struct clk dsp_ick = {
1070         .name           = "dsp_ick",     /* apparently ipi and isp */
1071         .parent         = &core_ck,
1072         .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
1073                                 DELAYED_APP | CONFIG_PARTICIPANT,
1074         .rate_offset    = OMAP24XX_CLKSEL_DSP_IF_SHIFT,
1075         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
1076         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,            /* for ipi */
1077         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1078         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1079         .clksel         = dsp_ick_clksel,
1080         .recalc         = &omap2_clksel_recalc,
1081 };
1082
1083 static const struct clksel_rate iva1_ifck_core_rates[] = {
1084         { .div = 1, .val = 1, .flags = RATE_IN_242X | DEFAULT_RATE },
1085         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1086         { .div = 3, .val = 3, .flags = RATE_IN_242X },
1087         { .div = 4, .val = 4, .flags = RATE_IN_242X },
1088         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1089         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1090         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1091         { .div = 0 },
1092 };
1093
1094 static const struct clksel iva1_ifck_clksel[] = {
1095         { .parent = &core_ck, .rates = iva1_ifck_core_rates },
1096         { .parent = NULL }
1097 };
1098
1099 static struct clk iva1_ifck = {
1100         .name           = "iva1_ifck",
1101         .parent         = &core_ck,
1102         .flags          = CLOCK_IN_OMAP242X | CM_DSP_SEL1 | RATE_CKCTL |
1103                         CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
1104         .rate_offset    = OMAP2420_CLKSEL_IVA_SHIFT,
1105         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
1106         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
1107         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1108         .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
1109         .clksel         = iva1_ifck_clksel,
1110         .recalc         = &omap2_clksel_recalc,
1111 };
1112
1113 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1114 static struct clk iva1_mpu_int_ifck = {
1115         .name           = "iva1_mpu_int_ifck",
1116         .parent         = &iva1_ifck,
1117         .flags          = CLOCK_IN_OMAP242X,
1118         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
1119         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
1120         .fixed_div      = 2,
1121         .recalc         = &omap2_fixed_divisor_recalc,
1122 };
1123
1124 /*
1125  * L3 clock domain
1126  * L3 clocks are used for both interface and functional clocks to
1127  * multiple entities. Some of these clocks are completely managed
1128  * by hardware, and some others allow software control. Hardware
1129  * managed ones general are based on directly CLK_REQ signals and
1130  * various auto idle settings. The functional spec sets many of these
1131  * as 'tie-high' for their enables.
1132  *
1133  * I-CLOCKS:
1134  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1135  *      CAM, HS-USB.
1136  * F-CLOCK
1137  *      SSI.
1138  *
1139  * GPMC memories and SDRC have timing and clock sensitive registers which
1140  * may very well need notification when the clock changes. Currently for low
1141  * operating points, these are taken care of in sleep.S.
1142  */
1143 static const struct clksel_rate core_l3_core_rates[] = {
1144         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1145         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1146         { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1147         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1148         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1149         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1150         { .div = 16, .val = 16, .flags = RATE_IN_242X },
1151         { .div = 0 }
1152 };
1153
1154 static const struct clksel core_l3_clksel[] = {
1155         { .parent = &core_ck, .rates = core_l3_core_rates },
1156         { .parent = NULL }
1157 };
1158
1159 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
1160         .name           = "core_l3_ck",
1161         .parent         = &core_ck,
1162         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1163                                 RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
1164                                 DELAYED_APP | CONFIG_PARTICIPANT |
1165                                 RATE_PROPAGATES,
1166         .rate_offset    = OMAP24XX_CLKSEL_L3_SHIFT,
1167         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1168         .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
1169         .clksel         = core_l3_clksel,
1170         .recalc         = &omap2_clksel_recalc,
1171 };
1172
1173 /* usb_l4_ick */
1174 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1175         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1176         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1177         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1178         { .div = 0 }
1179 };
1180
1181 static const struct clksel usb_l4_ick_clksel[] = {
1182         { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1183         { .parent = NULL },
1184 };
1185
1186 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
1187         .name           = "usb_l4_ick",
1188         .parent         = &core_l3_ck,
1189         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1190                                 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP |
1191                                 CONFIG_PARTICIPANT,
1192         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1193         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1194         .rate_offset    = OMAP24XX_CLKSEL_USB_SHIFT,
1195         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1196         .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
1197         .clksel         = usb_l4_ick_clksel,
1198         .recalc         = &omap2_clksel_recalc,
1199 };
1200
1201 /*
1202  * SSI is in L3 management domain, its direct parent is core not l3,
1203  * many core power domain entities are grouped into the L3 clock
1204  * domain.
1205  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
1206  *
1207  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1208  */
1209 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1210         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1211         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1212         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1213         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1214         { .div = 5, .val = 5, .flags = RATE_IN_243X },
1215         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1216         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1217         { .div = 0 }
1218 };
1219
1220 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1221         { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1222         { .parent = NULL }
1223 };
1224
1225 static struct clk ssi_ssr_sst_fck = {
1226         .name           = "ssi_fck",
1227         .parent         = &core_ck,
1228         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1229                                 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
1230         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),       /* bit 1 */
1231         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1232         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1233         .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
1234         .clksel         = ssi_ssr_sst_fck_clksel,
1235         .rate_offset    = OMAP24XX_CLKSEL_SSI_SHIFT,
1236         .recalc         = &omap2_clksel_recalc,
1237 };
1238
1239 /*
1240  * GFX clock domain
1241  *      Clocks:
1242  * GFX_FCLK, GFX_ICLK
1243  * GFX_CG1(2d), GFX_CG2(3d)
1244  *
1245  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1246  * The 2d and 3d clocks run at a hardware determined
1247  * divided value of fclk.
1248  *
1249  */
1250 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1251
1252 /*
1253  * These clksel_rate/clksel structs are shared between gfx_3d_fck and
1254  * gfx_2d_fck
1255  */
1256 static const struct clksel_rate gfx_fck_core_l3_rates[] = {
1257         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1258         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1259         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1260         { .div = 4, .val = 4, .flags = RATE_IN_243X },
1261         { .div = 0 }
1262 };
1263
1264 static const struct clksel gfx_fck_clksel[] = {
1265         { .parent = &core_l3_ck, .rates = gfx_fck_core_l3_rates },
1266         { .parent = NULL },
1267 };
1268
1269 static struct clk gfx_3d_fck = {
1270         .name           = "gfx_3d_fck",
1271         .parent         = &core_l3_ck,
1272         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1273                                 RATE_CKCTL | CM_GFX_SEL1,
1274         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
1275         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
1276         .rate_offset    = OMAP_CLKSEL_GFX_SHIFT,
1277         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1278         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1279         .clksel         = gfx_fck_clksel,
1280         .recalc         = &omap2_clksel_recalc,
1281 };
1282
1283 static struct clk gfx_2d_fck = {
1284         .name           = "gfx_2d_fck",
1285         .parent         = &core_l3_ck,
1286         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1287                                 RATE_CKCTL | CM_GFX_SEL1,
1288         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
1289         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
1290         .rate_offset    = OMAP_CLKSEL_GFX_SHIFT,
1291         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1292         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1293         .clksel         = gfx_fck_clksel,
1294         .recalc         = &omap2_clksel_recalc,
1295 };
1296
1297 static struct clk gfx_ick = {
1298         .name           = "gfx_ick",            /* From l3 */
1299         .parent         = &core_l3_ck,
1300         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1301         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),  /* bit 0 */
1302         .enable_bit     = OMAP_EN_GFX_SHIFT,
1303         .recalc         = &followparent_recalc,
1304 };
1305
1306 /*
1307  * Modem clock domain (2430)
1308  *      CLOCKS:
1309  *              MDM_OSC_CLK
1310  *              MDM_ICLK
1311  * These clocks are usable in chassis mode only.
1312  */
1313 static const struct clksel_rate mdm_ick_core_rates[] = {
1314         { .div = 1, .val = 1, .flags = RATE_IN_243X },
1315         { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1316         { .div = 6, .val = 6, .flags = RATE_IN_243X },
1317         { .div = 9, .val = 9, .flags = RATE_IN_243X },
1318         { .div = 0 }
1319 };
1320
1321 static const struct clksel mdm_ick_clksel[] = {
1322         { .parent = &core_ck, .rates = mdm_ick_core_rates },
1323         { .parent = NULL }
1324 };
1325
1326 static struct clk mdm_ick = {           /* used both as a ick and fck */
1327         .name           = "mdm_ick",
1328         .parent         = &core_ck,
1329         .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_MODEM_SEL1 |
1330                                 DELAYED_APP | CONFIG_PARTICIPANT,
1331         .rate_offset    = OMAP2430_CLKSEL_MDM_SHIFT,
1332         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1333         .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1334         .clksel_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
1335         .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
1336         .clksel         = mdm_ick_clksel,
1337         .recalc         = &omap2_clksel_recalc,
1338 };
1339
1340 static struct clk mdm_osc_ck = {
1341         .name           = "mdm_osc_ck",
1342         .parent         = &osc_ck,
1343         .flags          = CLOCK_IN_OMAP243X,
1344         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, OMAP24XX_CM_FCLKEN),
1345         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
1346         .recalc         = &followparent_recalc,
1347 };
1348
1349 /*
1350  * L4 clock management domain
1351  *
1352  * This domain contains lots of interface clocks from the L4 interface, some
1353  * functional clocks.   Fixed APLL functional source clocks are managed in
1354  * this domain.
1355  */
1356 static const struct clksel_rate l4_core_l3_rates[] = {
1357         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1358         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1359         { .div = 0 }
1360 };
1361
1362 static const struct clksel l4_clksel[] = {
1363         { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1364         { .parent = NULL }
1365 };
1366
1367 static struct clk l4_ck = {             /* used both as an ick and fck */
1368         .name           = "l4_ck",
1369         .parent         = &core_l3_ck,
1370         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1371                                 RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
1372                                 DELAYED_APP | RATE_PROPAGATES,
1373         .rate_offset    = OMAP24XX_CLKSEL_L4_SHIFT,
1374         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1375         .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
1376         .clksel         = l4_clksel,
1377         .recalc         = &omap2_clksel_recalc,
1378 };
1379
1380 static struct clk ssi_l4_ick = {
1381         .name           = "ssi_l4_ick",
1382         .parent         = &l4_ck,
1383         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1384         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),        /* bit 1 */
1385         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1386         .recalc         = &followparent_recalc,
1387 };
1388
1389 /*
1390  * DSS clock domain
1391  * CLOCKs:
1392  * DSS_L4_ICLK, DSS_L3_ICLK,
1393  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1394  *
1395  * DSS is both initiator and target.
1396  */
1397 /* XXX Add RATE_NOT_VALIDATED */
1398
1399 static const struct clksel_rate dss1_fck_sys_rates[] = {
1400         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1401         { .div = 0 }
1402 };
1403
1404 static const struct clksel_rate dss1_fck_core_rates[] = {
1405         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1406         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1407         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1408         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1409         { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1410         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1411         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1412         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1413         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1414         { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1415         { .div = 0 }
1416 };
1417
1418 static const struct clksel dss1_fck_clksel[] = {
1419         { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
1420         { .parent = &core_ck, .rates = dss1_fck_core_rates },
1421         { .parent = NULL },
1422 };
1423
1424 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1425         .name           = "dss_ick",
1426         .parent         = &l4_ck,       /* really both l3 and l4 */
1427         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1428         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1429         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1430         .recalc         = &followparent_recalc,
1431 };
1432
1433 static struct clk dss1_fck = {
1434         .name           = "dss1_fck",
1435         .parent         = &core_ck,             /* Core or sys */
1436         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1437                                 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
1438         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1439         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1440         .rate_offset    = OMAP24XX_CLKSEL_DSS1_SHIFT,
1441         .src_offset     = OMAP24XX_CLKSEL_DSS1_SHIFT,
1442         .init           = &omap2_init_clksel_parent,
1443         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1444         .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
1445         .clksel         = dss1_fck_clksel,
1446         .recalc         = &omap2_clksel_recalc,
1447 };
1448
1449 static const struct clksel_rate dss2_fck_sys_rates[] = {
1450         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1451         { .div = 0 }
1452 };
1453
1454 static const struct clksel_rate dss2_fck_48m_rates[] = {
1455         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1456         { .div = 0 }
1457 };
1458
1459 static const struct clksel dss2_fck_clksel[] = {
1460         { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
1461         { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1462         { .parent = NULL }
1463 };
1464
1465 static struct clk dss2_fck = {          /* Alt clk used in power management */
1466         .name           = "dss2_fck",
1467         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1468         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1469                                 RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED |
1470                                 DELAYED_APP,
1471         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1472         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
1473         .src_offset     = OMAP24XX_CLKSEL_DSS2_SHIFT,
1474         .init           = &omap2_init_clksel_parent,
1475         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1476         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
1477         .clksel         = dss2_fck_clksel,
1478         .recalc         = &followparent_recalc,
1479 };
1480
1481 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1482         .name           = "dss_54m_fck",        /* 54m tv clk */
1483         .parent         = &func_54m_ck,
1484         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1485         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1486         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
1487         .recalc         = &followparent_recalc,
1488 };
1489
1490 /*
1491  * CORE power domain ICLK & FCLK defines.
1492  * Many of the these can have more than one possible parent. Entries
1493  * here will likely have an L4 interface parent, and may have multiple
1494  * functional clock parents.
1495  */
1496 static const struct clksel_rate gpt_32k_rates[] = {
1497         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1498         { .div = 0 }
1499 };
1500
1501 static const struct clksel_rate gpt_sys_rates[] = {
1502         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1503         { .div = 0 }
1504 };
1505
1506 static const struct clksel_rate gpt_alt_rates[] = {
1507         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1508         { .div = 0 }
1509 };
1510
1511 static const struct clksel gpt_clksel[] = {
1512         { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1513         { .parent = &sys_ck,      .rates = gpt_sys_rates },
1514         { .parent = &alt_ck,      .rates = gpt_alt_rates },
1515         { .parent = NULL },
1516 };
1517
1518 static struct clk gpt1_ick = {
1519         .name           = "gpt1_ick",
1520         .parent         = &l4_ck,
1521         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1522         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), /* Bit0 */
1523         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1524         .recalc         = &followparent_recalc,
1525 };
1526
1527 static struct clk gpt1_fck = {
1528         .name           = "gpt1_fck",
1529         .parent         = &func_32k_ck,
1530         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1531                                 CM_WKUP_SEL1,
1532         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),        /* Bit0 */
1533         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1534         .src_offset     = OMAP24XX_CLKSEL_GPT1_SHIFT,
1535         .init           = &omap2_init_clksel_parent,
1536         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1537         .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
1538         .clksel         = gpt_clksel,
1539         .recalc         = &followparent_recalc,
1540 };
1541
1542 static struct clk gpt2_ick = {
1543         .name           = "gpt2_ick",
1544         .parent         = &l4_ck,
1545         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1546         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit4 */
1547         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1548         .recalc         = &followparent_recalc,
1549 };
1550
1551 static struct clk gpt2_fck = {
1552         .name           = "gpt2_fck",
1553         .parent         = &func_32k_ck,
1554         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1555                                 CM_CORE_SEL2,
1556         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1557         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1558         .src_offset     = OMAP24XX_CLKSEL_GPT2_SHIFT,
1559         .init           = &omap2_init_clksel_parent,
1560         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1561         .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
1562         .clksel         = gpt_clksel,
1563         .recalc         = &followparent_recalc,
1564 };
1565
1566 static struct clk gpt3_ick = {
1567         .name           = "gpt3_ick",
1568         .parent         = &l4_ck,
1569         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1570         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit5 */
1571         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1572         .recalc         = &followparent_recalc,
1573 };
1574
1575 static struct clk gpt3_fck = {
1576         .name           = "gpt3_fck",
1577         .parent         = &func_32k_ck,
1578         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1579                                 CM_CORE_SEL2,
1580         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1581         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1582         .src_offset     = OMAP24XX_CLKSEL_GPT3_SHIFT,
1583         .init           = &omap2_init_clksel_parent,
1584         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1585         .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
1586         .clksel         = gpt_clksel,
1587         .recalc         = &followparent_recalc,
1588 };
1589
1590 static struct clk gpt4_ick = {
1591         .name           = "gpt4_ick",
1592         .parent         = &l4_ck,
1593         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1594         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit6 */
1595         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1596         .recalc         = &followparent_recalc,
1597 };
1598
1599 static struct clk gpt4_fck = {
1600         .name           = "gpt4_fck",
1601         .parent         = &func_32k_ck,
1602         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1603                                 CM_CORE_SEL2,
1604         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1605         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1606         .src_offset     = OMAP24XX_CLKSEL_GPT4_SHIFT,
1607         .init           = &omap2_init_clksel_parent,
1608         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1609         .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
1610         .clksel         = gpt_clksel,
1611         .recalc         = &followparent_recalc,
1612 };
1613
1614 static struct clk gpt5_ick = {
1615         .name           = "gpt5_ick",
1616         .parent         = &l4_ck,
1617         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1618         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* Bit7 */
1619         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1620         .recalc         = &followparent_recalc,
1621 };
1622
1623 static struct clk gpt5_fck = {
1624         .name           = "gpt5_fck",
1625         .parent         = &func_32k_ck,
1626         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1627                                 CM_CORE_SEL2,
1628         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1629         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1630         .src_offset     = OMAP24XX_CLKSEL_GPT5_SHIFT,
1631         .init           = &omap2_init_clksel_parent,
1632         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1633         .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
1634         .clksel         = gpt_clksel,
1635         .recalc         = &followparent_recalc,
1636 };
1637
1638 static struct clk gpt6_ick = {
1639         .name           = "gpt6_ick",
1640         .parent         = &l4_ck,
1641         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1642         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit8 */
1643         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1644         .recalc         = &followparent_recalc,
1645 };
1646
1647 static struct clk gpt6_fck = {
1648         .name           = "gpt6_fck",
1649         .parent         = &func_32k_ck,
1650         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1651                                 CM_CORE_SEL2,
1652         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1653         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1654         .src_offset     = OMAP24XX_CLKSEL_GPT6_SHIFT,
1655         .init           = &omap2_init_clksel_parent,
1656         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1657         .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
1658         .clksel         = gpt_clksel,
1659         .recalc         = &followparent_recalc,
1660 };
1661
1662 static struct clk gpt7_ick = {
1663         .name           = "gpt7_ick",
1664         .parent         = &l4_ck,
1665         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1666         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit9 */
1667         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1668         .recalc         = &followparent_recalc,
1669 };
1670
1671 static struct clk gpt7_fck = {
1672         .name           = "gpt7_fck",
1673         .parent         = &func_32k_ck,
1674         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1675                                 CM_CORE_SEL2,
1676         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1677         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1678         .src_offset     = OMAP24XX_CLKSEL_GPT7_SHIFT,
1679         .init           = &omap2_init_clksel_parent,
1680         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1681         .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
1682         .clksel         = gpt_clksel,
1683         .recalc         = &followparent_recalc,
1684 };
1685
1686 static struct clk gpt8_ick = {
1687         .name           = "gpt8_ick",
1688         .parent         = &l4_ck,
1689         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1690         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit10 */
1691         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1692         .recalc         = &followparent_recalc,
1693 };
1694
1695 static struct clk gpt8_fck = {
1696         .name           = "gpt8_fck",
1697         .parent         = &func_32k_ck,
1698         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1699                                 CM_CORE_SEL2,
1700         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1701         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1702         .src_offset     = OMAP24XX_CLKSEL_GPT8_SHIFT,
1703         .init           = &omap2_init_clksel_parent,
1704         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1705         .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
1706         .clksel         = gpt_clksel,
1707         .recalc         = &followparent_recalc,
1708 };
1709
1710 static struct clk gpt9_ick = {
1711         .name           = "gpt9_ick",
1712         .parent         = &l4_ck,
1713         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1714         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1715         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1716         .recalc         = &followparent_recalc,
1717 };
1718
1719 static struct clk gpt9_fck = {
1720         .name           = "gpt9_fck",
1721         .parent         = &func_32k_ck,
1722         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1723                                         CM_CORE_SEL2,
1724         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1725         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1726         .src_offset     = OMAP24XX_CLKSEL_GPT9_SHIFT,
1727         .init           = &omap2_init_clksel_parent,
1728         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1729         .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
1730         .clksel         = gpt_clksel,
1731         .recalc         = &followparent_recalc,
1732 };
1733
1734 static struct clk gpt10_ick = {
1735         .name           = "gpt10_ick",
1736         .parent         = &l4_ck,
1737         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1738         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1739         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1740         .recalc         = &followparent_recalc,
1741 };
1742
1743 static struct clk gpt10_fck = {
1744         .name           = "gpt10_fck",
1745         .parent         = &func_32k_ck,
1746         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1747                                         CM_CORE_SEL2,
1748         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1749         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1750         .src_offset     = OMAP24XX_CLKSEL_GPT10_SHIFT,
1751         .init           = &omap2_init_clksel_parent,
1752         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1753         .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
1754         .clksel         = gpt_clksel,
1755         .recalc         = &followparent_recalc,
1756 };
1757
1758 static struct clk gpt11_ick = {
1759         .name           = "gpt11_ick",
1760         .parent         = &l4_ck,
1761         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1762         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1763         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1764         .recalc         = &followparent_recalc,
1765 };
1766
1767 static struct clk gpt11_fck = {
1768         .name           = "gpt11_fck",
1769         .parent         = &func_32k_ck,
1770         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1771                                         CM_CORE_SEL2,
1772         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1773         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1774         .src_offset     = OMAP24XX_CLKSEL_GPT11_SHIFT,
1775         .init           = &omap2_init_clksel_parent,
1776         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1777         .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
1778         .clksel         = gpt_clksel,
1779         .recalc         = &followparent_recalc,
1780 };
1781
1782 static struct clk gpt12_ick = {
1783         .name           = "gpt12_ick",
1784         .parent         = &l4_ck,
1785         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1786         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit14 */
1787         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1788         .recalc         = &followparent_recalc,
1789 };
1790
1791 static struct clk gpt12_fck = {
1792         .name           = "gpt12_fck",
1793         .parent         = &func_32k_ck,
1794         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1795                                         CM_CORE_SEL2,
1796         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1797         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1798         .src_offset     = OMAP24XX_CLKSEL_GPT12_SHIFT,
1799         .init           = &omap2_init_clksel_parent,
1800         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1801         .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
1802         .clksel         = gpt_clksel,
1803         .recalc         = &followparent_recalc,
1804 };
1805
1806 static struct clk mcbsp1_ick = {
1807         .name           = "mcbsp1_ick",
1808         .parent         = &l4_ck,
1809         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1810         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1811         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1812         .recalc         = &followparent_recalc,
1813 };
1814
1815 static struct clk mcbsp1_fck = {
1816         .name           = "mcbsp1_fck",
1817         .parent         = &func_96m_ck,
1818         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1819         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1820         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1821         .recalc         = &followparent_recalc,
1822 };
1823
1824 static struct clk mcbsp2_ick = {
1825         .name           = "mcbsp2_ick",
1826         .parent         = &l4_ck,
1827         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1828         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1829         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1830         .recalc         = &followparent_recalc,
1831 };
1832
1833 static struct clk mcbsp2_fck = {
1834         .name           = "mcbsp2_fck",
1835         .parent         = &func_96m_ck,
1836         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1837         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1838         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1839         .recalc         = &followparent_recalc,
1840 };
1841
1842 static struct clk mcbsp3_ick = {
1843         .name           = "mcbsp3_ick",
1844         .parent         = &l4_ck,
1845         .flags          = CLOCK_IN_OMAP243X,
1846         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1847         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1848         .recalc         = &followparent_recalc,
1849 };
1850
1851 static struct clk mcbsp3_fck = {
1852         .name           = "mcbsp3_fck",
1853         .parent         = &func_96m_ck,
1854         .flags          = CLOCK_IN_OMAP243X,
1855         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1856         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1857         .recalc         = &followparent_recalc,
1858 };
1859
1860 static struct clk mcbsp4_ick = {
1861         .name           = "mcbsp4_ick",
1862         .parent         = &l4_ck,
1863         .flags          = CLOCK_IN_OMAP243X,
1864         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1865         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1866         .recalc         = &followparent_recalc,
1867 };
1868
1869 static struct clk mcbsp4_fck = {
1870         .name           = "mcbsp4_fck",
1871         .parent         = &func_96m_ck,
1872         .flags          = CLOCK_IN_OMAP243X,
1873         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1874         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1875         .recalc         = &followparent_recalc,
1876 };
1877
1878 static struct clk mcbsp5_ick = {
1879         .name           = "mcbsp5_ick",
1880         .parent         = &l4_ck,
1881         .flags          = CLOCK_IN_OMAP243X,
1882         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1883         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1884         .recalc         = &followparent_recalc,
1885 };
1886
1887 static struct clk mcbsp5_fck = {
1888         .name           = "mcbsp5_fck",
1889         .parent         = &func_96m_ck,
1890         .flags          = CLOCK_IN_OMAP243X,
1891         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1892         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1893         .recalc         = &followparent_recalc,
1894 };
1895
1896 static struct clk mcspi1_ick = {
1897         .name           = "mcspi_ick",
1898         .id             = 1,
1899         .parent         = &l4_ck,
1900         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1901         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1902         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1903         .recalc         = &followparent_recalc,
1904 };
1905
1906 static struct clk mcspi1_fck = {
1907         .name           = "mcspi_fck",
1908         .id             = 1,
1909         .parent         = &func_48m_ck,
1910         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1911         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1912         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1913         .recalc         = &followparent_recalc,
1914 };
1915
1916 static struct clk mcspi2_ick = {
1917         .name           = "mcspi_ick",
1918         .id             = 2,
1919         .parent         = &l4_ck,
1920         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1921         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1922         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1923         .recalc         = &followparent_recalc,
1924 };
1925
1926 static struct clk mcspi2_fck = {
1927         .name           = "mcspi_fck",
1928         .id             = 2,
1929         .parent         = &func_48m_ck,
1930         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1931         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1932         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1933         .recalc         = &followparent_recalc,
1934 };
1935
1936 static struct clk mcspi3_ick = {
1937         .name           = "mcspi_ick",
1938         .id             = 3,
1939         .parent         = &l4_ck,
1940         .flags          = CLOCK_IN_OMAP243X,
1941         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1942         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1943         .recalc         = &followparent_recalc,
1944 };
1945
1946 static struct clk mcspi3_fck = {
1947         .name           = "mcspi_fck",
1948         .id             = 3,
1949         .parent         = &func_48m_ck,
1950         .flags          = CLOCK_IN_OMAP243X,
1951         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1952         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1953         .recalc         = &followparent_recalc,
1954 };
1955
1956 static struct clk uart1_ick = {
1957         .name           = "uart1_ick",
1958         .parent         = &l4_ck,
1959         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1960         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1961         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1962         .recalc         = &followparent_recalc,
1963 };
1964
1965 static struct clk uart1_fck = {
1966         .name           = "uart1_fck",
1967         .parent         = &func_48m_ck,
1968         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1969         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1970         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1971         .recalc         = &followparent_recalc,
1972 };
1973
1974 static struct clk uart2_ick = {
1975         .name           = "uart2_ick",
1976         .parent         = &l4_ck,
1977         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1978         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1979         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1980         .recalc         = &followparent_recalc,
1981 };
1982
1983 static struct clk uart2_fck = {
1984         .name           = "uart2_fck",
1985         .parent         = &func_48m_ck,
1986         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1987         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1988         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1989         .recalc         = &followparent_recalc,
1990 };
1991
1992 static struct clk uart3_ick = {
1993         .name           = "uart3_ick",
1994         .parent         = &l4_ck,
1995         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1996         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1997         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1998         .recalc         = &followparent_recalc,
1999 };
2000
2001 static struct clk uart3_fck = {
2002         .name           = "uart3_fck",
2003         .parent         = &func_48m_ck,
2004         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2005         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2006         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
2007         .recalc         = &followparent_recalc,
2008 };
2009
2010 static struct clk gpios_ick = {
2011         .name           = "gpios_ick",
2012         .parent         = &l4_ck,
2013         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2014         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2015         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2016         .recalc         = &followparent_recalc,
2017 };
2018
2019 static struct clk gpios_fck = {
2020         .name           = "gpios_fck",
2021         .parent         = &func_32k_ck,
2022         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2023         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
2024         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2025         .recalc         = &followparent_recalc,
2026 };
2027
2028 static struct clk mpu_wdt_ick = {
2029         .name           = "mpu_wdt_ick",
2030         .parent         = &l4_ck,
2031         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2032         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2033         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2034         .recalc         = &followparent_recalc,
2035 };
2036
2037 static struct clk mpu_wdt_fck = {
2038         .name           = "mpu_wdt_fck",
2039         .parent         = &func_32k_ck,
2040         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2041         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
2042         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2043         .recalc         = &followparent_recalc,
2044 };
2045
2046 static struct clk sync_32k_ick = {
2047         .name           = "sync_32k_ick",
2048         .parent         = &l4_ck,
2049         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2050         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2051         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
2052         .recalc         = &followparent_recalc,
2053 };
2054 static struct clk wdt1_ick = {
2055         .name           = "wdt1_ick",
2056         .parent         = &l4_ck,
2057         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2058         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2059         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
2060         .recalc         = &followparent_recalc,
2061 };
2062 static struct clk omapctrl_ick = {
2063         .name           = "omapctrl_ick",
2064         .parent         = &l4_ck,
2065         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2066         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2067         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
2068         .recalc         = &followparent_recalc,
2069 };
2070 static struct clk icr_ick = {
2071         .name           = "icr_ick",
2072         .parent         = &l4_ck,
2073         .flags          = CLOCK_IN_OMAP243X,
2074         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2075         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
2076         .recalc         = &followparent_recalc,
2077 };
2078
2079 static struct clk cam_ick = {
2080         .name           = "cam_ick",
2081         .parent         = &l4_ck,
2082         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2083         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2084         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2085         .recalc         = &followparent_recalc,
2086 };
2087
2088 static struct clk cam_fck = {
2089         .name           = "cam_fck",
2090         .parent         = &func_96m_ck,
2091         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2092         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2093         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2094         .recalc         = &followparent_recalc,
2095 };
2096
2097 static struct clk mailboxes_ick = {
2098         .name           = "mailboxes_ick",
2099         .parent         = &l4_ck,
2100         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2101         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2102         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
2103         .recalc         = &followparent_recalc,
2104 };
2105
2106 static struct clk wdt4_ick = {
2107         .name           = "wdt4_ick",
2108         .parent         = &l4_ck,
2109         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2110         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2111         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2112         .recalc         = &followparent_recalc,
2113 };
2114
2115 static struct clk wdt4_fck = {
2116         .name           = "wdt4_fck",
2117         .parent         = &func_32k_ck,
2118         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2119         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2120         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2121         .recalc         = &followparent_recalc,
2122 };
2123
2124 static struct clk wdt3_ick = {
2125         .name           = "wdt3_ick",
2126         .parent         = &l4_ck,
2127         .flags          = CLOCK_IN_OMAP242X,
2128         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2129         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2130         .recalc         = &followparent_recalc,
2131 };
2132
2133 static struct clk wdt3_fck = {
2134         .name           = "wdt3_fck",
2135         .parent         = &func_32k_ck,
2136         .flags          = CLOCK_IN_OMAP242X,
2137         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2138         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2139         .recalc         = &followparent_recalc,
2140 };
2141
2142 static struct clk mspro_ick = {
2143         .name           = "mspro_ick",
2144         .parent         = &l4_ck,
2145         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2146         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2147         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2148         .recalc         = &followparent_recalc,
2149 };
2150
2151 static struct clk mspro_fck = {
2152         .name           = "mspro_fck",
2153         .parent         = &func_96m_ck,
2154         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2155         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2156         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2157         .recalc         = &followparent_recalc,
2158 };
2159
2160 static struct clk mmc_ick = {
2161         .name           = "mmc_ick",
2162         .parent         = &l4_ck,
2163         .flags          = CLOCK_IN_OMAP242X,
2164         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2165         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2166         .recalc         = &followparent_recalc,
2167 };
2168
2169 static struct clk mmc_fck = {
2170         .name           = "mmc_fck",
2171         .parent         = &func_96m_ck,
2172         .flags          = CLOCK_IN_OMAP242X,
2173         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2174         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2175         .recalc         = &followparent_recalc,
2176 };
2177
2178 static struct clk fac_ick = {
2179         .name           = "fac_ick",
2180         .parent         = &l4_ck,
2181         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2182         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2183         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2184         .recalc         = &followparent_recalc,
2185 };
2186
2187 static struct clk fac_fck = {
2188         .name           = "fac_fck",
2189         .parent         = &func_12m_ck,
2190         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2191         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2192         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2193         .recalc         = &followparent_recalc,
2194 };
2195
2196 static struct clk eac_ick = {
2197         .name           = "eac_ick",
2198         .parent         = &l4_ck,
2199         .flags          = CLOCK_IN_OMAP242X,
2200         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2201         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2202         .recalc         = &followparent_recalc,
2203 };
2204
2205 static struct clk eac_fck = {
2206         .name           = "eac_fck",
2207         .parent         = &func_96m_ck,
2208         .flags          = CLOCK_IN_OMAP242X,
2209         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2210         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2211         .recalc         = &followparent_recalc,
2212 };
2213
2214 static struct clk hdq_ick = {
2215         .name           = "hdq_ick",
2216         .parent         = &l4_ck,
2217         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2218         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2219         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2220         .recalc         = &followparent_recalc,
2221 };
2222
2223 static struct clk hdq_fck = {
2224         .name           = "hdq_fck",
2225         .parent         = &func_12m_ck,
2226         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2227         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2228         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2229         .recalc         = &followparent_recalc,
2230 };
2231
2232 static struct clk i2c2_ick = {
2233         .name           = "i2c_ick",
2234         .id             = 2,
2235         .parent         = &l4_ck,
2236         .flags          = CLOCK_IN_OMAP242X,
2237         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2238         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2239         .recalc         = &followparent_recalc,
2240 };
2241
2242 static struct clk i2c2_fck = {
2243         .name           = "i2c_fck",
2244         .id             = 2,
2245         .parent         = &func_12m_ck,
2246         .flags          = CLOCK_IN_OMAP242X,
2247         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2248         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2249         .recalc         = &followparent_recalc,
2250 };
2251
2252 static struct clk i2chs2_fck = {
2253         .name           = "i2chs_fck",
2254         .id             = 2,
2255         .parent         = &func_96m_ck,
2256         .flags          = CLOCK_IN_OMAP243X,
2257         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2258         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
2259         .recalc         = &followparent_recalc,
2260 };
2261
2262 static struct clk i2c1_ick = {
2263         .name           = "i2c_ick",
2264         .id             = 1,
2265         .parent         = &l4_ck,
2266         .flags          = CLOCK_IN_OMAP242X,
2267         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2268         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2269         .recalc         = &followparent_recalc,
2270 };
2271
2272 static struct clk i2c1_fck = {
2273         .name           = "i2c_fck",
2274         .id             = 1,
2275         .parent         = &func_12m_ck,
2276         .flags          = CLOCK_IN_OMAP242X,
2277         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2278         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2279         .recalc         = &followparent_recalc,
2280 };
2281
2282 static struct clk i2chs1_fck = {
2283         .name           = "i2chs_fck",
2284         .id             = 1,
2285         .parent         = &func_96m_ck,
2286         .flags          = CLOCK_IN_OMAP243X,
2287         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2288         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
2289         .recalc         = &followparent_recalc,
2290 };
2291
2292 static struct clk vlynq_ick = {
2293         .name           = "vlynq_ick",
2294         .parent         = &core_l3_ck,
2295         .flags          = CLOCK_IN_OMAP242X,
2296         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2297         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2298         .recalc         = &followparent_recalc,
2299 };
2300
2301 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2302         { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2303         { .div = 0 }
2304 };
2305
2306 static const struct clksel_rate vlynq_fck_core_rates[] = {
2307         { .div = 1, .val = 1, .flags = RATE_IN_242X },
2308         { .div = 2, .val = 2, .flags = RATE_IN_242X },
2309         { .div = 3, .val = 3, .flags = RATE_IN_242X },
2310         { .div = 4, .val = 4, .flags = RATE_IN_242X },
2311         { .div = 6, .val = 6, .flags = RATE_IN_242X },
2312         { .div = 8, .val = 8, .flags = RATE_IN_242X },
2313         { .div = 9, .val = 9, .flags = RATE_IN_242X },
2314         { .div = 12, .val = 12, .flags = RATE_IN_242X },
2315         { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2316         { .div = 18, .val = 18, .flags = RATE_IN_242X },
2317         { .div = 0 }
2318 };
2319
2320 static const struct clksel vlynq_fck_clksel[] = {
2321         { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2322         { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
2323         { .parent = NULL }
2324 };
2325
2326 static struct clk vlynq_fck = {
2327         .name           = "vlynq_fck",
2328         .parent         = &func_96m_ck,
2329         .flags          = CLOCK_IN_OMAP242X  | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
2330         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2331         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2332         .src_offset     = OMAP2420_CLKSEL_VLYNQ_SHIFT,
2333         .init           = &omap2_init_clksel_parent,
2334         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
2335         .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
2336         .clksel         = vlynq_fck_clksel,
2337         .recalc         = &omap2_clksel_recalc,
2338 };
2339
2340 static struct clk sdrc_ick = {
2341         .name           = "sdrc_ick",
2342         .parent         = &l4_ck,
2343         .flags          = CLOCK_IN_OMAP243X,
2344         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP2430_CM_ICLKEN3),
2345         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
2346         .recalc         = &followparent_recalc,
2347 };
2348
2349 static struct clk des_ick = {
2350         .name           = "des_ick",
2351         .parent         = &l4_ck,
2352         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2353         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2354         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
2355         .recalc         = &followparent_recalc,
2356 };
2357
2358 static struct clk sha_ick = {
2359         .name           = "sha_ick",
2360         .parent         = &l4_ck,
2361         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2362         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2363         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
2364         .recalc         = &followparent_recalc,
2365 };
2366
2367 static struct clk rng_ick = {
2368         .name           = "rng_ick",
2369         .parent         = &l4_ck,
2370         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2371         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2372         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
2373         .recalc         = &followparent_recalc,
2374 };
2375
2376 static struct clk aes_ick = {
2377         .name           = "aes_ick",
2378         .parent         = &l4_ck,
2379         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2380         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2381         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
2382         .recalc         = &followparent_recalc,
2383 };
2384
2385 static struct clk pka_ick = {
2386         .name           = "pka_ick",
2387         .parent         = &l4_ck,
2388         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2389         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2390         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
2391         .recalc         = &followparent_recalc,
2392 };
2393
2394 static struct clk usb_fck = {
2395         .name           = "usb_fck",
2396         .parent         = &func_48m_ck,
2397         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2398         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2399         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
2400         .recalc         = &followparent_recalc,
2401 };
2402
2403 static struct clk usbhs_ick = {
2404         .name           = "usbhs_ick",
2405         .parent         = &core_l3_ck,
2406         .flags          = CLOCK_IN_OMAP243X,
2407         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2408         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
2409         .recalc         = &followparent_recalc,
2410 };
2411
2412 static struct clk mmchs1_ick = {
2413         .name           = "mmchs1_ick",
2414         .parent         = &l4_ck,
2415         .flags          = CLOCK_IN_OMAP243X,
2416         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2417         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2418         .recalc         = &followparent_recalc,
2419 };
2420
2421 static struct clk mmchs1_fck = {
2422         .name           = "mmchs1_fck",
2423         .parent         = &func_96m_ck,
2424         .flags          = CLOCK_IN_OMAP243X,
2425         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2426         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2427         .recalc         = &followparent_recalc,
2428 };
2429
2430 static struct clk mmchs2_ick = {
2431         .name           = "mmchs2_ick",
2432         .parent         = &l4_ck,
2433         .flags          = CLOCK_IN_OMAP243X,
2434         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2435         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2436         .recalc         = &followparent_recalc,
2437 };
2438
2439 static struct clk mmchs2_fck = {
2440         .name           = "mmchs2_fck",
2441         .parent         = &func_96m_ck,
2442         .flags          = CLOCK_IN_OMAP243X,
2443         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2444         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2445         .recalc         = &followparent_recalc,
2446 };
2447
2448 static struct clk gpio5_ick = {
2449         .name           = "gpio5_ick",
2450         .parent         = &l4_ck,
2451         .flags          = CLOCK_IN_OMAP243X,
2452         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2453         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2454         .recalc         = &followparent_recalc,
2455 };
2456
2457 static struct clk gpio5_fck = {
2458         .name           = "gpio5_fck",
2459         .parent         = &func_32k_ck,
2460         .flags          = CLOCK_IN_OMAP243X,
2461         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2462         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2463         .recalc         = &followparent_recalc,
2464 };
2465
2466 static struct clk mdm_intc_ick = {
2467         .name           = "mdm_intc_ick",
2468         .parent         = &l4_ck,
2469         .flags          = CLOCK_IN_OMAP243X,
2470         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2471         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
2472         .recalc         = &followparent_recalc,
2473 };
2474
2475 static struct clk mmchsdb1_fck = {
2476         .name           = "mmchsdb1_fck",
2477         .parent         = &func_32k_ck,
2478         .flags          = CLOCK_IN_OMAP243X,
2479         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2480         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
2481         .recalc         = &followparent_recalc,
2482 };
2483
2484 static struct clk mmchsdb2_fck = {
2485         .name           = "mmchsdb2_fck",
2486         .parent         = &func_32k_ck,
2487         .flags          = CLOCK_IN_OMAP243X,
2488         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2489         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
2490         .recalc         = &followparent_recalc,
2491 };
2492
2493 /*
2494  * This clock is a composite clock which does entire set changes then
2495  * forces a rebalance. It keys on the MPU speed, but it really could
2496  * be any key speed part of a set in the rate table.
2497  *
2498  * to really change a set, you need memory table sets which get changed
2499  * in sram, pre-notifiers & post notifiers, changing the top set, without
2500  * having low level display recalc's won't work... this is why dpm notifiers
2501  * work, isr's off, walk a list of clocks already _off_ and not messing with
2502  * the bus.
2503  *
2504  * This clock should have no parent. It embodies the entire upper level
2505  * active set. A parent will mess up some of the init also.
2506  */
2507 static struct clk virt_prcm_set = {
2508         .name           = "virt_prcm_set",
2509         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2510                                 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
2511         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
2512         .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
2513         .set_rate       = &omap2_select_table_rate,
2514         .round_rate     = &omap2_round_to_table_rate,
2515 };
2516
2517 static struct clk *onchip_clks[] __initdata = {
2518         /* external root sources */
2519         &func_32k_ck,
2520         &osc_ck,
2521         &sys_ck,
2522         &alt_ck,
2523         /* internal analog sources */
2524         &dpll_ck,
2525         &apll96_ck,
2526         &apll54_ck,
2527         /* internal prcm root sources */
2528         &func_54m_ck,
2529         &core_ck,
2530         &func_96m_ck,
2531         &func_48m_ck,
2532         &func_12m_ck,
2533         &wdt1_osc_ck,
2534         &sys_clkout_src,
2535         &sys_clkout,
2536         &sys_clkout2_src,
2537         &sys_clkout2,
2538         &emul_ck,
2539         /* mpu domain clocks */
2540         &mpu_ck,
2541         /* dsp domain clocks */
2542         &iva2_1_fck,            /* 2430 */
2543         &iva2_1_ick,
2544         &dsp_ick,               /* 2420 */
2545         &dsp_fck,
2546         &iva1_ifck,
2547         &iva1_mpu_int_ifck,
2548         /* GFX domain clocks */
2549         &gfx_3d_fck,
2550         &gfx_2d_fck,
2551         &gfx_ick,
2552         /* Modem domain clocks */
2553         &mdm_ick,
2554         &mdm_osc_ck,
2555         /* DSS domain clocks */
2556         &dss_ick,
2557         &dss1_fck,
2558         &dss2_fck,
2559         &dss_54m_fck,
2560         /* L3 domain clocks */
2561         &core_l3_ck,
2562         &ssi_ssr_sst_fck,
2563         &usb_l4_ick,
2564         /* L4 domain clocks */
2565         &l4_ck,                 /* used as both core_l4 and wu_l4 */
2566         &ssi_l4_ick,
2567         /* virtual meta-group clock */
2568         &virt_prcm_set,
2569         /* general l4 interface ck, multi-parent functional clk */
2570         &gpt1_ick,
2571         &gpt1_fck,
2572         &gpt2_ick,
2573         &gpt2_fck,
2574         &gpt3_ick,
2575         &gpt3_fck,
2576         &gpt4_ick,
2577         &gpt4_fck,
2578         &gpt5_ick,
2579         &gpt5_fck,
2580         &gpt6_ick,
2581         &gpt6_fck,
2582         &gpt7_ick,
2583         &gpt7_fck,
2584         &gpt8_ick,
2585         &gpt8_fck,
2586         &gpt9_ick,
2587         &gpt9_fck,
2588         &gpt10_ick,
2589         &gpt10_fck,
2590         &gpt11_ick,
2591         &gpt11_fck,
2592         &gpt12_ick,
2593         &gpt12_fck,
2594         &mcbsp1_ick,
2595         &mcbsp1_fck,
2596         &mcbsp2_ick,
2597         &mcbsp2_fck,
2598         &mcbsp3_ick,
2599         &mcbsp3_fck,
2600         &mcbsp4_ick,
2601         &mcbsp4_fck,
2602         &mcbsp5_ick,
2603         &mcbsp5_fck,
2604         &mcspi1_ick,
2605         &mcspi1_fck,
2606         &mcspi2_ick,
2607         &mcspi2_fck,
2608         &mcspi3_ick,
2609         &mcspi3_fck,
2610         &uart1_ick,
2611         &uart1_fck,
2612         &uart2_ick,
2613         &uart2_fck,
2614         &uart3_ick,
2615         &uart3_fck,
2616         &gpios_ick,
2617         &gpios_fck,
2618         &mpu_wdt_ick,
2619         &mpu_wdt_fck,
2620         &sync_32k_ick,
2621         &wdt1_ick,
2622         &omapctrl_ick,
2623         &icr_ick,
2624         &cam_fck,
2625         &cam_ick,
2626         &mailboxes_ick,
2627         &wdt4_ick,
2628         &wdt4_fck,
2629         &wdt3_ick,
2630         &wdt3_fck,
2631         &mspro_ick,
2632         &mspro_fck,
2633         &mmc_ick,
2634         &mmc_fck,
2635         &fac_ick,
2636         &fac_fck,
2637         &eac_ick,
2638         &eac_fck,
2639         &hdq_ick,
2640         &hdq_fck,
2641         &i2c1_ick,
2642         &i2c1_fck,
2643         &i2chs1_fck,
2644         &i2c2_ick,
2645         &i2c2_fck,
2646         &i2chs2_fck,
2647         &vlynq_ick,
2648         &vlynq_fck,
2649         &sdrc_ick,
2650         &des_ick,
2651         &sha_ick,
2652         &rng_ick,
2653         &aes_ick,
2654         &pka_ick,
2655         &usb_fck,
2656         &usbhs_ick,
2657         &mmchs1_ick,
2658         &mmchs1_fck,
2659         &mmchs2_ick,
2660         &mmchs2_fck,
2661         &gpio5_ick,
2662         &gpio5_fck,
2663         &mdm_intc_ick,
2664         &mmchsdb1_fck,
2665         &mmchsdb2_fck,
2666 };
2667
2668 #endif