arch/arm/mach-omap2/clock.h

   1 /*
   2  *  linux/arch/arm/mach-omap24xx/clock.h
   3  *
   4  *  Copyright (C) 2005 Texas Instruments Inc.
   5  *  Richard Woodruff <r-woodruff2@ti.com>
   6  *  Created for OMAP2.
   7  *
   8  *  Copyright (C) 2004 Nokia corporation
   9  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  10  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
  18 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
  19
  20 #include "prm.h"
  21 #include "cm.h"
  22
  23 static void omap2_sys_clk_recalc(struct clk * clk);
  24 static void omap2_clksel_recalc(struct clk * clk);
  25 static void omap2_followparent_recalc(struct clk * clk);
  26 static void omap2_propagate_rate(struct clk * clk);
  27 static void omap2_mpu_recalc(struct clk * clk);
  28 static int omap2_select_table_rate(struct clk * clk, unsigned long rate);
  29 static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate);
  30 static void omap2_clk_disable(struct clk *clk);
  31 static void omap2_sys_clk_recalc(struct clk * clk);
  32 static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val);
  33 static u32 omap2_clksel_get_divisor(struct clk *clk);
  34
  35 /* REVISIT: should use a clock flag for this, not a magic number */
  36 #define PARENT_CONTROLS_CLOCK   0xff
  37
  38 #define RATE_IN_242X    (1 << 0)
  39 #define RATE_IN_243X    (1 << 1)
  40
  41 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  42  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  43  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  44  */
  45 struct prcm_config {
  46         unsigned long xtal_speed;       /* crystal rate */
  47         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  48         unsigned long mpu_speed;        /* speed of MPU */
  49         unsigned long cm_clksel_mpu;    /* mpu divider */
  50         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  51         unsigned long cm_clksel_gfx;    /* gfx dividers */
  52         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  53         unsigned long cm_clksel1_pll;   /* m,n */
  54         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  55         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  56         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  57         unsigned char flags;
  58 };
  59
  60 /* Mask for clksel which support parent settign in set_rate */
  61 #define SRC_SEL_MASK (CM_CORE_SEL1 | CM_CORE_SEL2 | CM_WKUP_SEL1 | \
  62                         CM_PLL_SEL1 | CM_PLL_SEL2 | CM_SYSCLKOUT_SEL1)
  63
  64 /* Mask for clksel regs which support rate operations */
  65 #define SRC_RATE_SEL_MASK (CM_MPU_SEL1 | CM_DSP_SEL1 | CM_GFX_SEL1 | \
  66                         CM_MODEM_SEL1 | CM_CORE_SEL1 | CM_CORE_SEL2 | \
  67                         CM_WKUP_SEL1 | CM_PLL_SEL1 | CM_PLL_SEL2 | \
  68                         CM_SYSCLKOUT_SEL1)
  69
  70 /*
  71  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  72  * These configurations are characterized by voltage and speed for clocks.
  73  * The device is only validated for certain combinations. One way to express
  74  * these combinations is via the 'ratio's' which the clocks operate with
  75  * respect to each other. These ratio sets are for a given voltage/DPLL
  76  * setting. All configurations can be described by a DPLL setting and a ratio
  77  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  78  *
  79  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  80  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  81  * 2430 (iva2.1, NOdsp, mdm)
  82  */
  83
  84 /* Core fields for cm_clksel, not ratio governed */
  85 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  86 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  87 #define RX_CLKSEL_SSI                   (0x5 << 20)
  88
  89 /*-------------------------------------------------------------------------
  90  * Voltage/DPLL ratios
  91  *-------------------------------------------------------------------------*/
  92
  93 /* 2430 Ratio's, 2430-Ratio Config 1 */
  94 #define R1_CLKSEL_L3                    (4 << 0)
  95 #define R1_CLKSEL_L4                    (2 << 5)
  96 #define R1_CLKSEL_USB                   (4 << 25)
  97 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
  98                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  99                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
 100 #define R1_CLKSEL_MPU                   (2 << 0)
 101 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
 102 #define R1_CLKSEL_DSP                   (2 << 0)
 103 #define R1_CLKSEL_DSP_IF                (2 << 5)
 104 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
 105 #define R1_CLKSEL_GFX                   (2 << 0)
 106 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
 107 #define R1_CLKSEL_MDM                   (4 << 0)
 108 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
 109
 110 /* 2430-Ratio Config 2 */
 111 #define R2_CLKSEL_L3                    (6 << 0)
 112 #define R2_CLKSEL_L4                    (2 << 5)
 113 #define R2_CLKSEL_USB                   (2 << 25)
 114 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
 115                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 116                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
 117 #define R2_CLKSEL_MPU                   (2 << 0)
 118 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 119 #define R2_CLKSEL_DSP                   (2 << 0)
 120 #define R2_CLKSEL_DSP_IF                (3 << 5)
 121 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 122 #define R2_CLKSEL_GFX                   (2 << 0)
 123 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 124 #define R2_CLKSEL_MDM                   (6 << 0)
 125 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 126
 127 /* 2430-Ratio Bootm (BYPASS) */
 128 #define RB_CLKSEL_L3                    (1 << 0)
 129 #define RB_CLKSEL_L4                    (1 << 5)
 130 #define RB_CLKSEL_USB                   (1 << 25)
 131 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 132                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 133                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 134 #define RB_CLKSEL_MPU                   (1 << 0)
 135 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 136 #define RB_CLKSEL_DSP                   (1 << 0)
 137 #define RB_CLKSEL_DSP_IF                (1 << 5)
 138 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 139 #define RB_CLKSEL_GFX                   (1 << 0)
 140 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 141 #define RB_CLKSEL_MDM                   (1 << 0)
 142 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 143
 144 /* 2420 Ratio Equivalents */
 145 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 146 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 147
 148 /* 2420-PRCM III 532MHz core */
 149 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 150 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 151 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 152 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 153                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 154                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 155                                         RIII_CLKSEL_L3
 156 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 157 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 158 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 159 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 160 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 161 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 162 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 163 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 164                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 165                                         RIII_CLKSEL_DSP
 166 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 167 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 168
 169 /* 2420-PRCM II 600MHz core */
 170 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 171 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 172 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 173 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 174                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 175                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 176                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 177 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 178 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 179 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 180 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 181 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 182 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 183 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 184 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 185                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 186                                         RII_CLKSEL_DSP
 187 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 188 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 189
 190 /* 2420-PRCM I 660MHz core */
 191 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 192 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 193 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 194 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 195                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 196                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 197                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 198 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 199 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 200 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 201 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 202 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 203 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 204 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 205 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 206                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 207                                         RI_CLKSEL_DSP
 208 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 209 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 210
 211 /* 2420-PRCM VII (boot) */
 212 #define RVII_CLKSEL_L3                  (1 << 0)
 213 #define RVII_CLKSEL_L4                  (1 << 5)
 214 #define RVII_CLKSEL_DSS1                (1 << 8)
 215 #define RVII_CLKSEL_DSS2                (0 << 13)
 216 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 217 #define RVII_CLKSEL_SSI                 (1 << 20)
 218 #define RVII_CLKSEL_USB                 (1 << 25)
 219
 220 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 221                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 222                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 223
 224 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 225 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 226
 227 #define RVII_CLKSEL_DSP                 (1 << 0)
 228 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 229 #define RVII_SYNC_DSP                   (0 << 7)
 230 #define RVII_CLKSEL_IVA                 (1 << 8)
 231 #define RVII_SYNC_IVA                   (0 << 13)
 232 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 233                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 234
 235 #define RVII_CLKSEL_GFX                 (1 << 0)
 236 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 237
 238 /*-------------------------------------------------------------------------
 239  * 2430 Target modes: Along with each configuration the CPU has several
 240  * modes which goes along with them. Modes mainly are the addition of
 241  * describe DPLL combinations to go along with a ratio.
 242  *-------------------------------------------------------------------------*/
 243
 244 /* Hardware governed */
 245 #define MX_48M_SRC                      (0 << 3)
 246 #define MX_54M_SRC                      (0 << 5)
 247 #define MX_APLLS_CLIKIN_12              (3 << 23)
 248 #define MX_APLLS_CLIKIN_13              (2 << 23)
 249 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 250
 251 /*
 252  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 253  * #2   (ratio1) baseport-target
 254  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 255  */
 256 #define M5A_DPLL_MULT_12                (133 << 12)
 257 #define M5A_DPLL_DIV_12                 (5 << 8)
 258 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 259                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 260                                         MX_APLLS_CLIKIN_12
 261 #define M5A_DPLL_MULT_13                (266 << 12)
 262 #define M5A_DPLL_DIV_13                 (12 << 8)
 263 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 264                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 265                                         MX_APLLS_CLIKIN_13
 266 #define M5A_DPLL_MULT_19                (180 << 12)
 267 #define M5A_DPLL_DIV_19                 (12 << 8)
 268 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 269                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 270                                         MX_APLLS_CLIKIN_19_2
 271 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 272 #define M5B_DPLL_MULT_12                (50 << 12)
 273 #define M5B_DPLL_DIV_12                 (2 << 8)
 274 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 275                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 276                                         MX_APLLS_CLIKIN_12
 277 #define M5B_DPLL_MULT_13                (200 << 12)
 278 #define M5B_DPLL_DIV_13                 (12 << 8)
 279
 280 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 281                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 282                                         MX_APLLS_CLIKIN_13
 283 #define M5B_DPLL_MULT_19                (125 << 12)
 284 #define M5B_DPLL_DIV_19                 (31 << 8)
 285 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 286                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 287                                         MX_APLLS_CLIKIN_19_2
 288 /*
 289  * #4   (ratio2)
 290  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 291  */
 292 #define M3_DPLL_MULT_12                 (55 << 12)
 293 #define M3_DPLL_DIV_12                  (1 << 8)
 294 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 295                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 296                                         MX_APLLS_CLIKIN_12
 297 #define M3_DPLL_MULT_13                 (330 << 12)
 298 #define M3_DPLL_DIV_13                  (12 << 8)
 299 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 300                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 301                                         MX_APLLS_CLIKIN_13
 302 #define M3_DPLL_MULT_19                 (275 << 12)
 303 #define M3_DPLL_DIV_19                  (15 << 8)
 304 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 305                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 306                                         MX_APLLS_CLIKIN_19_2
 307 /* boot (boot) */
 308 #define MB_DPLL_MULT                    (1 << 12)
 309 #define MB_DPLL_DIV                     (0 << 8)
 310 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 311                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 312
 313 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 314                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 315
 316 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 317                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 318
 319 /*
 320  * 2430 - chassis (sedna)
 321  * 165 (ratio1) same as above #2
 322  * 150 (ratio1)
 323  * 133 (ratio2) same as above #4
 324  * 110 (ratio2) same as above #3
 325  * 104 (ratio2)
 326  * boot (boot)
 327  */
 328
 329 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 330 #define MI_DPLL_MULT_12                 (55 << 12)
 331 #define MI_DPLL_DIV_12                  (1 << 8)
 332 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 333                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 334                                         MX_APLLS_CLIKIN_12
 335
 336 /*
 337  * 2420 Equivalent - mode registers
 338  * PRCM II , target DPLL = 2*300MHz = 600MHz
 339  */
 340 #define MII_DPLL_MULT_12                (50 << 12)
 341 #define MII_DPLL_DIV_12                 (1 << 8)
 342 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 343                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 344                                         MX_APLLS_CLIKIN_12
 345 #define MII_DPLL_MULT_13                (300 << 12)
 346 #define MII_DPLL_DIV_13                 (12 << 8)
 347 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 348                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 349                                         MX_APLLS_CLIKIN_13
 350
 351 /* PRCM III target DPLL = 2*266 = 532MHz*/
 352 #define MIII_DPLL_MULT_12               (133 << 12)
 353 #define MIII_DPLL_DIV_12                (5 << 8)
 354 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 355                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 356                                         MX_APLLS_CLIKIN_12
 357 #define MIII_DPLL_MULT_13               (266 << 12)
 358 #define MIII_DPLL_DIV_13                (12 << 8)
 359 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 360                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 361                                         MX_APLLS_CLIKIN_13
 362
 363 /* PRCM VII (boot bypass) */
 364 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 365 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 366
 367 /* High and low operation value */
 368 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 369 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 370
 371 /*
 372  * These represent optimal values for common parts, it won't work for all.
 373  * As long as you scale down, most parameters are still work, they just
 374  * become sub-optimal. The RFR value goes in the opposite direction. If you
 375  * don't adjust it down as your clock period increases the refresh interval
 376  * will not be met. Setting all parameters for complete worst case may work,
 377  * but may cut memory performance by 2x. Due to errata the DLLs need to be
 378  * unlocked and their value needs run time calibration. A dynamic call is
 379  * need for that as no single right value exists acorss production samples.
 380  *
 381  * Only the FULL speed values are given. Current code is such that rate
 382  * changes must be made at DPLLoutx2. The actual value adjustment for low
 383  * frequency operation will be handled by omap_set_performance()
 384  *
 385  * By having the boot loader boot up in the fastest L4 speed available likely
 386  * will result in something which you can switch between.
 387  */
 388 #define V24XX_SDRC_RFR_CTRL_165MHz      (0x00044c00 | 1)
 389 #define V24XX_SDRC_RFR_CTRL_133MHz      (0x0003de00 | 1)
 390 #define V24XX_SDRC_RFR_CTRL_100MHz      (0x0002da01 | 1)
 391 #define V24XX_SDRC_RFR_CTRL_110MHz      (0x0002da01 | 1) /* Need to calc */
 392 #define V24XX_SDRC_RFR_CTRL_BYPASS      (0x00005000 | 1) /* Need to calc */
 393
 394 /* MPU speed defines */
 395 #define S12M    12000000
 396 #define S13M    13000000
 397 #define S19M    19200000
 398 #define S26M    26000000
 399 #define S100M   100000000
 400 #define S133M   133000000
 401 #define S150M   150000000
 402 #define S165M   165000000
 403 #define S200M   200000000
 404 #define S266M   266000000
 405 #define S300M   300000000
 406 #define S330M   330000000
 407 #define S400M   400000000
 408 #define S532M   532000000
 409 #define S600M   600000000
 410 #define S660M   660000000
 411
 412 /*-------------------------------------------------------------------------
 413  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 414  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 415  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 416  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 417  *
 418  * Filling in table based on H4 boards and 2430-SDPs variants available.
 419  * There are quite a few more rates combinations which could be defined.
 420  *
 421  * When multiple values are defined the start up will try and choose the
 422  * fastest one. If a 'fast' value is defined, then automatically, the /2
 423  * one should be included as it can be used.    Generally having more that
 424  * one fast set does not make sense, as static timings need to be changed
 425  * to change the set.    The exception is the bypass setting which is
 426  * availble for low power bypass.
 427  *
 428  * Note: This table needs to be sorted, fastest to slowest.
 429  *-------------------------------------------------------------------------*/
 430 static struct prcm_config rate_table[] = {
 431         /* PRCM I - FAST */
 432         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 433                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 434                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 435                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_165MHz,
 436                 RATE_IN_242X},
 437
 438         /* PRCM II - FAST */
 439         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 440                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 441                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 442                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 443                 RATE_IN_242X},
 444
 445         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 446                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 447                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 448                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 449                 RATE_IN_242X},
 450
 451         /* PRCM III - FAST */
 452         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 453                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 454                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 455                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 456                 RATE_IN_242X},
 457
 458         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 459                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 460                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 461                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 462                 RATE_IN_242X},
 463
 464         /* PRCM II - SLOW */
 465         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 466                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 467                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 468                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 469                 RATE_IN_242X},
 470
 471         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 472                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 473                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 474                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 475                 RATE_IN_242X},
 476
 477         /* PRCM III - SLOW */
 478         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 479                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 480                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 481                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 482                 RATE_IN_242X},
 483
 484         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 485                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 486                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 487                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 488                 RATE_IN_242X},
 489
 490         /* PRCM-VII (boot-bypass) */
 491         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 492                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 493                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 494                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
 495                 RATE_IN_242X},
 496
 497         /* PRCM-VII (boot-bypass) */
 498         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 499                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 500                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 501                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
 502                 RATE_IN_242X},
 503
 504         /* PRCM #3 - ratio2 (ES2) - FAST */
 505         {S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 506                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 507                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 508                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 509                 V24XX_SDRC_RFR_CTRL_110MHz,
 510                 RATE_IN_243X},
 511
 512         /* PRCM #5a - ratio1 - FAST */
 513         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 514                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 515                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 516                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 517                 V24XX_SDRC_RFR_CTRL_133MHz,
 518                 RATE_IN_243X},
 519
 520         /* PRCM #5b - ratio1 - FAST */
 521         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 522                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 523                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 524                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 525                 V24XX_SDRC_RFR_CTRL_100MHz,
 526                 RATE_IN_243X},
 527
 528         /* PRCM #3 - ratio2 (ES2) - SLOW */
 529         {S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 530                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 531                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 532                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 533                 V24XX_SDRC_RFR_CTRL_110MHz,
 534                 RATE_IN_243X},
 535
 536         /* PRCM #5a - ratio1 - SLOW */
 537         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 538                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 539                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 540                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 541                 V24XX_SDRC_RFR_CTRL_133MHz,
 542                 RATE_IN_243X},
 543
 544         /* PRCM #5b - ratio1 - SLOW*/
 545         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 546                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 547                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 548                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 549                 V24XX_SDRC_RFR_CTRL_100MHz,
 550                 RATE_IN_243X},
 551
 552         /* PRCM-boot/bypass */
 553         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 554                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 555                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 556                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 557                 V24XX_SDRC_RFR_CTRL_BYPASS,
 558                 RATE_IN_243X},
 559
 560         /* PRCM-boot/bypass */
 561         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 562                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 563                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 564                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 565                 V24XX_SDRC_RFR_CTRL_BYPASS,
 566                 RATE_IN_243X},
 567
 568         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 569 };
 570
 571 /*-------------------------------------------------------------------------
 572  * 24xx clock tree.
 573  *
 574  * NOTE:In many cases here we are assigning a 'default' parent. In many
 575  *      cases the parent is selectable. The get/set parent calls will also
 576  *      switch sources.
 577  *
 578  *      Many some clocks say always_enabled, but they can be auto idled for
 579  *      power savings. They will always be available upon clock request.
 580  *
 581  *      Several sources are given initial rates which may be wrong, this will
 582  *      be fixed up in the init func.
 583  *
 584  *      Things are broadly separated below by clock domains. It is
 585  *      noteworthy that most periferals have dependencies on multiple clock
 586  *      domains. Many get their interface clocks from the L4 domain, but get
 587  *      functional clocks from fixed sources or other core domain derived
 588  *      clocks.
 589  *-------------------------------------------------------------------------*/
 590
 591 /* Base external input clocks */
 592 static struct clk func_32k_ck = {
 593         .name           = "func_32k_ck",
 594         .rate           = 32000,
 595         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 596                                 RATE_FIXED | ALWAYS_ENABLED,
 597 };
 598
 599 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 600 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 601         .name           = "osc_ck",
 602         .rate           = 26000000,             /* fixed up in clock init */
 603         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 604                                 RATE_FIXED | RATE_PROPAGATES,
 605 };
 606
 607 /* With out modem likely 12MHz, with modem likely 13MHz */
 608 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 609         .name           = "sys_ck",             /* ~ ref_clk also */
 610         .parent         = &osc_ck,
 611         .rate           = 13000000,
 612         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 613                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 614         .rate_offset    = 6, /* sysclkdiv 1 or 2, already handled or no boot */
 615         .recalc         = &omap2_sys_clk_recalc,
 616 };
 617
 618 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 619         .name           = "alt_ck",
 620         .rate           = 54000000,
 621         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 622                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 623         .recalc         = &omap2_propagate_rate,
 624 };
 625
 626 /*
 627  * Analog domain root source clocks
 628  */
 629
 630 /* dpll_ck, is broken out in to special cases through clksel */
 631 static struct clk dpll_ck = {
 632         .name           = "dpll_ck",
 633         .parent         = &sys_ck,              /* Can be func_32k also */
 634         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 635                                 RATE_PROPAGATES | RATE_CKCTL | CM_PLL_SEL1,
 636         .recalc         = &omap2_clksel_recalc,
 637 };
 638
 639 static struct clk apll96_ck = {
 640         .name           = "apll96_ck",
 641         .parent         = &sys_ck,
 642         .rate           = 96000000,
 643         .flags          = CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X |
 644                                 RATE_FIXED | RATE_PROPAGATES,
 645         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 646         .enable_bit     = 0x2,
 647         .recalc         = &omap2_propagate_rate,
 648 };
 649
 650 static struct clk apll54_ck = {
 651         .name           = "apll54_ck",
 652         .parent         = &sys_ck,
 653         .rate           = 54000000,
 654         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 655                                 RATE_FIXED | RATE_PROPAGATES,
 656         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 657         .enable_bit     = 0x6,
 658         .recalc         = &omap2_propagate_rate,
 659 };
 660
 661 /*
 662  * PRCM digital base sources
 663  */
 664 static struct clk func_54m_ck = {
 665         .name           = "func_54m_ck",
 666         .parent         = &apll54_ck,   /* can also be alt_clk */
 667         .rate           = 54000000,
 668         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 669                                 RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
 670         .src_offset     = 5,
 671         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 672         .enable_bit     = PARENT_CONTROLS_CLOCK,
 673         .recalc         = &omap2_propagate_rate,
 674 };
 675
 676 static struct clk core_ck = {
 677         .name           = "core_ck",
 678         .parent         = &dpll_ck,             /* can also be 32k */
 679         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 680                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 681         .recalc         = &omap2_propagate_rate,
 682 };
 683
 684 static struct clk sleep_ck = {          /* sys_clk or 32k */
 685         .name           = "sleep_ck",
 686         .parent         = &func_32k_ck,
 687         .rate           = 32000,
 688         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 689         .recalc         = &omap2_propagate_rate,
 690 };
 691
 692 static struct clk func_96m_ck = {
 693         .name           = "func_96m_ck",
 694         .parent         = &apll96_ck,
 695         .rate           = 96000000,
 696         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 697                                 RATE_FIXED | RATE_PROPAGATES,
 698         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 699         .enable_bit     = PARENT_CONTROLS_CLOCK,
 700         .recalc         = &omap2_propagate_rate,
 701 };
 702
 703 static struct clk func_48m_ck = {
 704         .name           = "func_48m_ck",
 705         .parent         = &apll96_ck,    /* 96M or Alt */
 706         .rate           = 48000000,
 707         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 708                                 RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
 709         .src_offset     = 3,
 710         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 711         .enable_bit     = PARENT_CONTROLS_CLOCK,
 712         .recalc         = &omap2_propagate_rate,
 713 };
 714
 715 static struct clk func_12m_ck = {
 716         .name           = "func_12m_ck",
 717         .parent         = &func_48m_ck,
 718         .rate           = 12000000,
 719         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 720                                 RATE_FIXED | RATE_PROPAGATES,
 721         .recalc         = &omap2_propagate_rate,
 722         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 723         .enable_bit     = PARENT_CONTROLS_CLOCK,
 724 };
 725
 726 /* Secure timer, only available in secure mode */
 727 static struct clk wdt1_osc_ck = {
 728         .name           = "ck_wdt1_osc",
 729         .parent         = &osc_ck,
 730         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 731         .recalc         = &omap2_followparent_recalc,
 732 };
 733
 734 static struct clk sys_clkout = {
 735         .name           = "sys_clkout",
 736         .parent         = &func_54m_ck,
 737         .rate           = 54000000,
 738         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 739                                 CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
 740         .src_offset     = 0,
 741         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 742         .enable_bit     = 7,
 743         .rate_offset    = 3,
 744         .recalc         = &omap2_clksel_recalc,
 745 };
 746
 747 /* In 2430, new in 2420 ES2 */
 748 static struct clk sys_clkout2 = {
 749         .name           = "sys_clkout2",
 750         .parent         = &func_54m_ck,
 751         .rate           = 54000000,
 752         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 753                                 CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
 754         .src_offset     = 8,
 755         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 756         .enable_bit     = 15,
 757         .rate_offset    = 11,
 758         .recalc         = &omap2_clksel_recalc,
 759 };
 760
 761 static struct clk emul_ck = {
 762         .name           = "emul_ck",
 763         .parent         = &func_54m_ck,
 764         .flags          = CLOCK_IN_OMAP242X,
 765         .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL,
 766         .enable_bit     = 0,
 767         .recalc         = &omap2_propagate_rate,
 768
 769 };
 770
 771 /*
 772  * MPU clock domain
 773  *      Clocks:
 774  *              MPU_FCLK, MPU_ICLK
 775  *              INT_M_FCLK, INT_M_I_CLK
 776  *
 777  * - Individual clocks are hardware managed.
 778  * - Base divider comes from: CM_CLKSEL_MPU
 779  *
 780  */
 781 static struct clk mpu_ck = {    /* Control cpu */
 782         .name           = "mpu_ck",
 783         .parent         = &core_ck,
 784         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL |
 785                                 ALWAYS_ENABLED | CM_MPU_SEL1 | DELAYED_APP |
 786                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
 787         .rate_offset    = 0,    /* bits 0-4 */
 788         .recalc         = &omap2_clksel_recalc,
 789 };
 790
 791 /*
 792  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
 793  * Clocks:
 794  *      2430: IVA2.1_FCLK, IVA2.1_ICLK
 795  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
 796  */
 797 static struct clk iva2_1_fck = {
 798         .name           = "iva2_1_fck",
 799         .parent         = &core_ck,
 800         .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
 801                                 DELAYED_APP | RATE_PROPAGATES |
 802                                 CONFIG_PARTICIPANT,
 803         .rate_offset    = 0,
 804         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 805         .enable_bit     = 0,
 806         .recalc         = &omap2_clksel_recalc,
 807 };
 808
 809 static struct clk iva2_1_ick = {
 810         .name           = "iva2_1_ick",
 811         .parent         = &iva2_1_fck,
 812         .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
 813                                 DELAYED_APP | CONFIG_PARTICIPANT,
 814         .rate_offset    = 5,
 815         .recalc         = &omap2_clksel_recalc,
 816 };
 817
 818 /*
 819  * Won't be too specific here. The core clock comes into this block
 820  * it is divided then tee'ed. One branch goes directly to xyz enable
 821  * controls. The other branch gets further divided by 2 then possibly
 822  * routed into a synchronizer and out of clocks abc.
 823  */
 824 static struct clk dsp_fck = {
 825         .name           = "dsp_fck",
 826         .parent         = &core_ck,
 827         .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
 828                         DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
 829         .rate_offset    = 0,
 830         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 831         .enable_bit     = 0,
 832         .recalc         = &omap2_clksel_recalc,
 833 };
 834
 835 static struct clk dsp_ick = {
 836         .name           = "dsp_ick",     /* apparently ipi and isp */
 837         .parent         = &dsp_fck,
 838         .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
 839                                 DELAYED_APP | CONFIG_PARTICIPANT,
 840         .rate_offset    = 5,
 841         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
 842         .enable_bit     = 1,            /* for ipi */
 843         .recalc         = &omap2_clksel_recalc,
 844 };
 845
 846 static struct clk iva1_ifck = {
 847         .name           = "iva1_ifck",
 848         .parent         = &core_ck,
 849         .flags          = CLOCK_IN_OMAP242X | CM_DSP_SEL1 | RATE_CKCTL |
 850                         CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
 851         .rate_offset    = 8,
 852         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 853         .enable_bit     = 10,
 854         .recalc         = &omap2_clksel_recalc,
 855 };
 856
 857 /* IVA1 mpu/int/i/f clocks are /2 of parent */
 858 static struct clk iva1_mpu_int_ifck = {
 859         .name           = "iva1_mpu_int_ifck",
 860         .parent         = &iva1_ifck,
 861         .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1,
 862         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 863         .enable_bit     = 8,
 864         .recalc         = &omap2_clksel_recalc,
 865 };
 866
 867 /*
 868  * L3 clock domain
 869  * L3 clocks are used for both interface and functional clocks to
 870  * multiple entities. Some of these clocks are completely managed
 871  * by hardware, and some others allow software control. Hardware
 872  * managed ones general are based on directly CLK_REQ signals and
 873  * various auto idle settings. The functional spec sets many of these
 874  * as 'tie-high' for their enables.
 875  *
 876  * I-CLOCKS:
 877  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
 878  *      CAM, HS-USB.
 879  * F-CLOCK
 880  *      SSI.
 881  *
 882  * GPMC memories and SDRC have timing and clock sensitive registers which
 883  * may very well need notification when the clock changes. Currently for low
 884  * operating points, these are taken care of in sleep.S.
 885  */
 886 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
 887         .name           = "core_l3_ck",
 888         .parent         = &core_ck,
 889         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 890                                 RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
 891                                 DELAYED_APP | CONFIG_PARTICIPANT |
 892                                 RATE_PROPAGATES,
 893         .rate_offset    = 0,
 894         .recalc         = &omap2_clksel_recalc,
 895 };
 896
 897 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
 898         .name           = "usb_l4_ick",
 899         .parent         = &core_l3_ck,
 900         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 901                                 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP |
 902                                 CONFIG_PARTICIPANT,
 903         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 904         .enable_bit     = 0,
 905         .rate_offset    = 25,
 906         .recalc         = &omap2_clksel_recalc,
 907 };
 908
 909 /*
 910  * SSI is in L3 management domain, its direct parent is core not l3,
 911  * many core power domain entities are grouped into the L3 clock
 912  * domain.
 913  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
 914  *
 915  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
 916  */
 917 static struct clk ssi_ssr_sst_fck = {
 918         .name           = "ssi_fck",
 919         .parent         = &core_ck,
 920         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 921                                 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
 922         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),       /* bit 1 */
 923         .enable_bit     = 1,
 924         .rate_offset    = 20,
 925         .recalc         = &omap2_clksel_recalc,
 926 };
 927
 928 /*
 929  * GFX clock domain
 930  *      Clocks:
 931  * GFX_FCLK, GFX_ICLK
 932  * GFX_CG1(2d), GFX_CG2(3d)
 933  *
 934  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
 935  * The 2d and 3d clocks run at a hardware determined
 936  * divided value of fclk.
 937  *
 938  */
 939 static struct clk gfx_3d_fck = {
 940         .name           = "gfx_3d_fck",
 941         .parent         = &core_l3_ck,
 942         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 943                                 RATE_CKCTL | CM_GFX_SEL1,
 944         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
 945         .enable_bit     = 2,
 946         .rate_offset    = 0,
 947         .recalc         = &omap2_clksel_recalc,
 948 };
 949
 950 static struct clk gfx_2d_fck = {
 951         .name           = "gfx_2d_fck",
 952         .parent         = &core_l3_ck,
 953         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 954                                 RATE_CKCTL | CM_GFX_SEL1,
 955         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
 956         .enable_bit     = 1,
 957         .rate_offset    = 0,
 958         .recalc         = &omap2_clksel_recalc,
 959 };
 960
 961 static struct clk gfx_ick = {
 962         .name           = "gfx_ick",            /* From l3 */
 963         .parent         = &core_l3_ck,
 964         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 965                                 RATE_CKCTL,
 966         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),  /* bit 0 */
 967         .enable_bit     = 0,
 968         .recalc         = &omap2_followparent_recalc,
 969 };
 970
 971 /*
 972  * Modem clock domain (2430)
 973  *      CLOCKS:
 974  *              MDM_OSC_CLK
 975  *              MDM_ICLK
 976  */
 977 static struct clk mdm_ick = {           /* used both as a ick and fck */
 978         .name           = "mdm_ick",
 979         .parent         = &core_ck,
 980         .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_MODEM_SEL1 |
 981                                 DELAYED_APP | CONFIG_PARTICIPANT,
 982         .rate_offset    = 0,
 983         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
 984         .enable_bit     = 0,
 985         .recalc         = &omap2_clksel_recalc,
 986 };
 987
 988 static struct clk mdm_osc_ck = {
 989         .name           = "mdm_osc_ck",
 990         .rate           = 26000000,
 991         .parent         = &osc_ck,
 992         .flags          = CLOCK_IN_OMAP243X | RATE_FIXED,
 993         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, OMAP24XX_CM_FCLKEN),
 994         .enable_bit     = 1,
 995         .recalc         = &omap2_followparent_recalc,
 996 };
 997
 998 /*
 999  * L4 clock management domain
1000  *
1001  * This domain contains lots of interface clocks from the L4 interface, some
1002  * functional clocks.   Fixed APLL functional source clocks are managed in
1003  * this domain.
1004  */
1005 static struct clk l4_ck = {             /* used both as an ick and fck */
1006         .name           = "l4_ck",
1007         .parent         = &core_l3_ck,
1008         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1009                                 RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
1010                                 DELAYED_APP | RATE_PROPAGATES,
1011         .rate_offset    = 5,
1012         .recalc         = &omap2_clksel_recalc,
1013 };
1014
1015 static struct clk ssi_l4_ick = {
1016         .name           = "ssi_l4_ick",
1017         .parent         = &l4_ck,
1018         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
1019         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),        /* bit 1 */
1020         .enable_bit     = 1,
1021         .recalc         = &omap2_followparent_recalc,
1022 };
1023
1024 /*
1025  * DSS clock domain
1026  * CLOCKs:
1027  * DSS_L4_ICLK, DSS_L3_ICLK,
1028  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1029  *
1030  * DSS is both initiator and target.
1031  */
1032 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1033         .name           = "dss_ick",
1034         .parent         = &l4_ck,       /* really both l3 and l4 */
1035         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
1036         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1037         .enable_bit     = 0,
1038         .recalc         = &omap2_followparent_recalc,
1039 };
1040
1041 static struct clk dss1_fck = {
1042         .name           = "dss1_fck",
1043         .parent         = &core_ck,             /* Core or sys */
1044         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1045                                 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
1046         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1047         .enable_bit     = 0,
1048         .rate_offset    = 8,
1049         .src_offset     = 8,
1050         .recalc         = &omap2_clksel_recalc,
1051 };
1052
1053 static struct clk dss2_fck = {          /* Alt clk used in power management */
1054         .name           = "dss2_fck",
1055         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1056         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1057                                 RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED |
1058                                 DELAYED_APP,
1059         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1060         .enable_bit     = 1,
1061         .src_offset     = 13,
1062         .recalc         = &omap2_followparent_recalc,
1063 };
1064
1065 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1066         .name           = "dss_54m_fck",        /* 54m tv clk */
1067         .parent         = &func_54m_ck,
1068         .rate           = 54000000,
1069         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1070                                 RATE_FIXED | RATE_PROPAGATES,
1071         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1072         .enable_bit     = 2,
1073         .recalc         = &omap2_propagate_rate,
1074 };
1075
1076 /*
1077  * CORE power domain ICLK & FCLK defines.
1078  * Many of the these can have more than one possible parent. Entries
1079  * here will likely have an L4 interface parent, and may have multiple
1080  * functional clock parents.
1081  */
1082 static struct clk gpt1_ick = {
1083         .name           = "gpt1_ick",
1084         .parent         = &l4_ck,
1085         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1086         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), /* Bit0 */
1087         .enable_bit     = 0,
1088         .recalc         = &omap2_followparent_recalc,
1089 };
1090
1091 static struct clk gpt1_fck = {
1092         .name           = "gpt1_fck",
1093         .parent         = &func_32k_ck,
1094         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1095                                 CM_WKUP_SEL1,
1096         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),        /* Bit0 */
1097         .enable_bit     = 0,
1098         .src_offset     = 0,
1099         .recalc         = &omap2_followparent_recalc,
1100 };
1101
1102 static struct clk gpt2_ick = {
1103         .name           = "gpt2_ick",
1104         .parent         = &l4_ck,
1105         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1106         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit4 */
1107         .enable_bit     = 4,
1108         .recalc         = &omap2_followparent_recalc,
1109 };
1110
1111 static struct clk gpt2_fck = {
1112         .name           = "gpt2_fck",
1113         .parent         = &func_32k_ck,
1114         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1115                                 CM_CORE_SEL2,
1116         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1117         .enable_bit     = 4,
1118         .src_offset     = 2,
1119         .recalc         = &omap2_followparent_recalc,
1120 };
1121
1122 static struct clk gpt3_ick = {
1123         .name           = "gpt3_ick",
1124         .parent         = &l4_ck,
1125         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1126         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit5 */
1127         .enable_bit     = 5,
1128         .recalc         = &omap2_followparent_recalc,
1129 };
1130
1131 static struct clk gpt3_fck = {
1132         .name           = "gpt3_fck",
1133         .parent         = &func_32k_ck,
1134         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1135                                 CM_CORE_SEL2,
1136         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1137         .enable_bit     = 5,
1138         .src_offset     = 4,
1139         .recalc         = &omap2_followparent_recalc,
1140 };
1141
1142 static struct clk gpt4_ick = {
1143         .name           = "gpt4_ick",
1144         .parent         = &l4_ck,
1145         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1146         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit6 */
1147         .enable_bit     = 6,
1148         .recalc         = &omap2_followparent_recalc,
1149 };
1150
1151 static struct clk gpt4_fck = {
1152         .name           = "gpt4_fck",
1153         .parent         = &func_32k_ck,
1154         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1155                                 CM_CORE_SEL2,
1156         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1157         .enable_bit     = 6,
1158         .src_offset     = 6,
1159         .recalc         = &omap2_followparent_recalc,
1160 };
1161
1162 static struct clk gpt5_ick = {
1163         .name           = "gpt5_ick",
1164         .parent         = &l4_ck,
1165         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1166         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* Bit7 */
1167         .enable_bit     = 7,
1168         .recalc         = &omap2_followparent_recalc,
1169 };
1170
1171 static struct clk gpt5_fck = {
1172         .name           = "gpt5_fck",
1173         .parent         = &func_32k_ck,
1174         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1175                                 CM_CORE_SEL2,
1176         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1177         .enable_bit     = 7,
1178         .src_offset     = 8,
1179         .recalc         = &omap2_followparent_recalc,
1180 };
1181
1182 static struct clk gpt6_ick = {
1183         .name           = "gpt6_ick",
1184         .parent         = &l4_ck,
1185         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1186         .enable_bit     = 8,
1187         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit8 */
1188         .recalc         = &omap2_followparent_recalc,
1189 };
1190
1191 static struct clk gpt6_fck = {
1192         .name           = "gpt6_fck",
1193         .parent         = &func_32k_ck,
1194         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1195                                 CM_CORE_SEL2,
1196         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1197         .enable_bit     = 8,
1198         .src_offset     = 10,
1199         .recalc         = &omap2_followparent_recalc,
1200 };
1201
1202 static struct clk gpt7_ick = {
1203         .name           = "gpt7_ick",
1204         .parent         = &l4_ck,
1205         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1206         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit9 */
1207         .enable_bit     = 9,
1208         .recalc         = &omap2_followparent_recalc,
1209 };
1210
1211 static struct clk gpt7_fck = {
1212         .name           = "gpt7_fck",
1213         .parent         = &func_32k_ck,
1214         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1215                                 CM_CORE_SEL2,
1216         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1217         .enable_bit     = 9,
1218         .src_offset     = 12,
1219         .recalc         = &omap2_followparent_recalc,
1220 };
1221
1222 static struct clk gpt8_ick = {
1223         .name           = "gpt8_ick",
1224         .parent         = &l4_ck,
1225         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1226         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit10 */
1227         .enable_bit     = 10,
1228         .recalc         = &omap2_followparent_recalc,
1229 };
1230
1231 static struct clk gpt8_fck = {
1232         .name           = "gpt8_fck",
1233         .parent         = &func_32k_ck,
1234         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1235                                 CM_CORE_SEL2,
1236         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1237         .enable_bit     = 10,
1238         .src_offset     = 14,
1239         .recalc         = &omap2_followparent_recalc,
1240 };
1241
1242 static struct clk gpt9_ick = {
1243         .name           = "gpt9_ick",
1244         .parent         = &l4_ck,
1245         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1246         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1247         .enable_bit     = 11,
1248         .recalc         = &omap2_followparent_recalc,
1249 };
1250
1251 static struct clk gpt9_fck = {
1252         .name           = "gpt9_fck",
1253         .parent         = &func_32k_ck,
1254         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1255                                         CM_CORE_SEL2,
1256         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1257         .enable_bit     = 11,
1258         .src_offset     = 16,
1259         .recalc         = &omap2_followparent_recalc,
1260 };
1261
1262 static struct clk gpt10_ick = {
1263         .name           = "gpt10_ick",
1264         .parent         = &l4_ck,
1265         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1266         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1267         .enable_bit     = 12,
1268         .recalc         = &omap2_followparent_recalc,
1269 };
1270
1271 static struct clk gpt10_fck = {
1272         .name           = "gpt10_fck",
1273         .parent         = &func_32k_ck,
1274         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1275                                         CM_CORE_SEL2,
1276         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1277         .enable_bit     = 12,
1278         .src_offset     = 18,
1279         .recalc         = &omap2_followparent_recalc,
1280 };
1281
1282 static struct clk gpt11_ick = {
1283         .name           = "gpt11_ick",
1284         .parent         = &l4_ck,
1285         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1286         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1287         .enable_bit     = 13,
1288         .recalc         = &omap2_followparent_recalc,
1289 };
1290
1291 static struct clk gpt11_fck = {
1292         .name           = "gpt11_fck",
1293         .parent         = &func_32k_ck,
1294         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1295                                         CM_CORE_SEL2,
1296         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1297         .enable_bit     = 13,
1298         .src_offset     = 20,
1299         .recalc         = &omap2_followparent_recalc,
1300 };
1301
1302 static struct clk gpt12_ick = {
1303         .name           = "gpt12_ick",
1304         .parent         = &l4_ck,
1305         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1306         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit14 */
1307         .enable_bit     = 14,
1308         .recalc         = &omap2_followparent_recalc,
1309 };
1310
1311 static struct clk gpt12_fck = {
1312         .name           = "gpt12_fck",
1313         .parent         = &func_32k_ck,
1314         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1315                                         CM_CORE_SEL2,
1316         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1317         .enable_bit     = 14,
1318         .src_offset     = 22,
1319         .recalc         = &omap2_followparent_recalc,
1320 };
1321
1322 static struct clk mcbsp1_ick = {
1323         .name           = "mcbsp1_ick",
1324         .parent         = &l4_ck,
1325         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1326         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit16 */
1327         .enable_bit     = 15,
1328         .recalc         = &omap2_followparent_recalc,
1329 };
1330
1331 static struct clk mcbsp1_fck = {
1332         .name           = "mcbsp1_fck",
1333         .parent         = &func_96m_ck,
1334         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1335         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1336         .enable_bit     = 15,
1337         .recalc         = &omap2_followparent_recalc,
1338 };
1339
1340 static struct clk mcbsp2_ick = {
1341         .name           = "mcbsp2_ick",
1342         .parent         = &l4_ck,
1343         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1344         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1345         .enable_bit     = 16,
1346         .recalc         = &omap2_followparent_recalc,
1347 };
1348
1349 static struct clk mcbsp2_fck = {
1350         .name           = "mcbsp2_fck",
1351         .parent         = &func_96m_ck,
1352         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1353         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1354         .enable_bit     = 16,
1355         .recalc         = &omap2_followparent_recalc,
1356 };
1357
1358 static struct clk mcbsp3_ick = {
1359         .name           = "mcbsp3_ick",
1360         .parent         = &l4_ck,
1361         .flags          = CLOCK_IN_OMAP243X,
1362         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1363         .enable_bit     = 3,
1364         .recalc         = &omap2_followparent_recalc,
1365 };
1366
1367 static struct clk mcbsp3_fck = {
1368         .name           = "mcbsp3_fck",
1369         .parent         = &func_96m_ck,
1370         .flags          = CLOCK_IN_OMAP243X,
1371         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1372         .enable_bit     = 3,
1373         .recalc         = &omap2_followparent_recalc,
1374 };
1375
1376 static struct clk mcbsp4_ick = {
1377         .name           = "mcbsp4_ick",
1378         .parent         = &l4_ck,
1379         .flags          = CLOCK_IN_OMAP243X,
1380         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1381         .enable_bit     = 4,
1382         .recalc         = &omap2_followparent_recalc,
1383 };
1384
1385 static struct clk mcbsp4_fck = {
1386         .name           = "mcbsp4_fck",
1387         .parent         = &func_96m_ck,
1388         .flags          = CLOCK_IN_OMAP243X,
1389         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1390         .enable_bit     = 4,
1391         .recalc         = &omap2_followparent_recalc,
1392 };
1393
1394 static struct clk mcbsp5_ick = {
1395         .name           = "mcbsp5_ick",
1396         .parent         = &l4_ck,
1397         .flags          = CLOCK_IN_OMAP243X,
1398         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1399         .enable_bit     = 5,
1400         .recalc         = &omap2_followparent_recalc,
1401 };
1402
1403 static struct clk mcbsp5_fck = {
1404         .name           = "mcbsp5_fck",
1405         .parent         = &func_96m_ck,
1406         .flags          = CLOCK_IN_OMAP243X,
1407         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1408         .enable_bit     = 5,
1409         .recalc         = &omap2_followparent_recalc,
1410 };
1411
1412 static struct clk mcspi1_ick = {
1413         .name           = "mcspi_ick",
1414         .id             = 1,
1415         .parent         = &l4_ck,
1416         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1417         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1418         .enable_bit     = 17,
1419         .recalc         = &omap2_followparent_recalc,
1420 };
1421
1422 static struct clk mcspi1_fck = {
1423         .name           = "mcspi_fck",
1424         .id             = 1,
1425         .parent         = &func_48m_ck,
1426         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1427         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1428         .enable_bit     = 17,
1429         .recalc         = &omap2_followparent_recalc,
1430 };
1431
1432 static struct clk mcspi2_ick = {
1433         .name           = "mcspi_ick",
1434         .id             = 2,
1435         .parent         = &l4_ck,
1436         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1437         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1438         .enable_bit     = 18,
1439         .recalc         = &omap2_followparent_recalc,
1440 };
1441
1442 static struct clk mcspi2_fck = {
1443         .name           = "mcspi_fck",
1444         .id             = 2,
1445         .parent         = &func_48m_ck,
1446         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1447         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1448         .enable_bit     = 18,
1449         .recalc         = &omap2_followparent_recalc,
1450 };
1451
1452 static struct clk mcspi3_ick = {
1453         .name           = "mcspi_ick",
1454         .id             = 3,
1455         .parent         = &l4_ck,
1456         .flags          = CLOCK_IN_OMAP243X,
1457         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1458         .enable_bit     = 9,
1459         .recalc         = &omap2_followparent_recalc,
1460 };
1461
1462 static struct clk mcspi3_fck = {
1463         .name           = "mcspi_fck",
1464         .id             = 3,
1465         .parent         = &func_48m_ck,
1466         .flags          = CLOCK_IN_OMAP243X,
1467         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1468         .enable_bit     = 9,
1469         .recalc         = &omap2_followparent_recalc,
1470 };
1471
1472 static struct clk uart1_ick = {
1473         .name           = "uart1_ick",
1474         .parent         = &l4_ck,
1475         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1476         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1477         .enable_bit     = 21,
1478         .recalc         = &omap2_followparent_recalc,
1479 };
1480
1481 static struct clk uart1_fck = {
1482         .name           = "uart1_fck",
1483         .parent         = &func_48m_ck,
1484         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1485         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1486         .enable_bit     = 21,
1487         .recalc         = &omap2_followparent_recalc,
1488 };
1489
1490 static struct clk uart2_ick = {
1491         .name           = "uart2_ick",
1492         .parent         = &l4_ck,
1493         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1494         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1495         .enable_bit     = 22,
1496         .recalc         = &omap2_followparent_recalc,
1497 };
1498
1499 static struct clk uart2_fck = {
1500         .name           = "uart2_fck",
1501         .parent         = &func_48m_ck,
1502         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1503         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1504         .enable_bit     = 22,
1505         .recalc         = &omap2_followparent_recalc,
1506 };
1507
1508 static struct clk uart3_ick = {
1509         .name           = "uart3_ick",
1510         .parent         = &l4_ck,
1511         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1512         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1513         .enable_bit     = 2,
1514         .recalc         = &omap2_followparent_recalc,
1515 };
1516
1517 static struct clk uart3_fck = {
1518         .name           = "uart3_fck",
1519         .parent         = &func_48m_ck,
1520         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1521         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1522         .enable_bit     = 2,
1523         .recalc         = &omap2_followparent_recalc,
1524 };
1525
1526 static struct clk gpios_ick = {
1527         .name           = "gpios_ick",
1528         .parent         = &l4_ck,
1529         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1530         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1531         .enable_bit     = 2,
1532         .recalc         = &omap2_followparent_recalc,
1533 };
1534
1535 static struct clk gpios_fck = {
1536         .name           = "gpios_fck",
1537         .parent         = &func_32k_ck,
1538         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1539         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
1540         .enable_bit     = 2,
1541         .recalc         = &omap2_followparent_recalc,
1542 };
1543
1544 static struct clk mpu_wdt_ick = {
1545         .name           = "mpu_wdt_ick",
1546         .parent         = &l4_ck,
1547         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1548         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1549         .enable_bit     = 3,
1550         .recalc         = &omap2_followparent_recalc,
1551 };
1552
1553 static struct clk mpu_wdt_fck = {
1554         .name           = "mpu_wdt_fck",
1555         .parent         = &func_32k_ck,
1556         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1557         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
1558         .enable_bit     = 3,
1559         .recalc         = &omap2_followparent_recalc,
1560 };
1561
1562 static struct clk sync_32k_ick = {
1563         .name           = "sync_32k_ick",
1564         .parent         = &l4_ck,
1565         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1566         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1567         .enable_bit     = 1,
1568         .recalc         = &omap2_followparent_recalc,
1569 };
1570 static struct clk wdt1_ick = {
1571         .name           = "wdt1_ick",
1572         .parent         = &l4_ck,
1573         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1574         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1575         .enable_bit     = 4,
1576         .recalc         = &omap2_followparent_recalc,
1577 };
1578 static struct clk omapctrl_ick = {
1579         .name           = "omapctrl_ick",
1580         .parent         = &l4_ck,
1581         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1582         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1583         .enable_bit     = 5,
1584         .recalc         = &omap2_followparent_recalc,
1585 };
1586 static struct clk icr_ick = {
1587         .name           = "icr_ick",
1588         .parent         = &l4_ck,
1589         .flags          = CLOCK_IN_OMAP243X,
1590         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1591         .enable_bit     = 6,
1592         .recalc         = &omap2_followparent_recalc,
1593 };
1594
1595 static struct clk cam_ick = {
1596         .name           = "cam_ick",
1597         .parent         = &l4_ck,
1598         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1599         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1600         .enable_bit     = 31,
1601         .recalc         = &omap2_followparent_recalc,
1602 };
1603
1604 static struct clk cam_fck = {
1605         .name           = "cam_fck",
1606         .parent         = &func_96m_ck,
1607         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1608         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1609         .enable_bit     = 31,
1610         .recalc         = &omap2_followparent_recalc,
1611 };
1612
1613 static struct clk mailboxes_ick = {
1614         .name           = "mailboxes_ick",
1615         .parent         = &l4_ck,
1616         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1617         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1618         .enable_bit     = 30,
1619         .recalc         = &omap2_followparent_recalc,
1620 };
1621
1622 static struct clk wdt4_ick = {
1623         .name           = "wdt4_ick",
1624         .parent         = &l4_ck,
1625         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1626         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1627         .enable_bit     = 29,
1628         .recalc         = &omap2_followparent_recalc,
1629 };
1630
1631 static struct clk wdt4_fck = {
1632         .name           = "wdt4_fck",
1633         .parent         = &func_32k_ck,
1634         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1635         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1636         .enable_bit     = 29,
1637         .recalc         = &omap2_followparent_recalc,
1638 };
1639
1640 static struct clk wdt3_ick = {
1641         .name           = "wdt3_ick",
1642         .parent         = &l4_ck,
1643         .flags          = CLOCK_IN_OMAP242X,
1644         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1645         .enable_bit     = 28,
1646         .recalc         = &omap2_followparent_recalc,
1647 };
1648
1649 static struct clk wdt3_fck = {
1650         .name           = "wdt3_fck",
1651         .parent         = &func_32k_ck,
1652         .flags          = CLOCK_IN_OMAP242X,
1653         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1654         .enable_bit     = 28,
1655         .recalc         = &omap2_followparent_recalc,
1656 };
1657
1658 static struct clk mspro_ick = {
1659         .name           = "mspro_ick",
1660         .parent         = &l4_ck,
1661         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1662         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1663         .enable_bit     = 27,
1664         .recalc         = &omap2_followparent_recalc,
1665 };
1666
1667 static struct clk mspro_fck = {
1668         .name           = "mspro_fck",
1669         .parent         = &func_96m_ck,
1670         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1671         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1672         .enable_bit     = 27,
1673         .recalc         = &omap2_followparent_recalc,
1674 };
1675
1676 static struct clk mmc_ick = {
1677         .name           = "mmc_ick",
1678         .parent         = &l4_ck,
1679         .flags          = CLOCK_IN_OMAP242X,
1680         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1681         .enable_bit     = 26,
1682         .recalc         = &omap2_followparent_recalc,
1683 };
1684
1685 static struct clk mmc_fck = {
1686         .name           = "mmc_fck",
1687         .parent         = &func_96m_ck,
1688         .flags          = CLOCK_IN_OMAP242X,
1689         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1690         .enable_bit     = 26,
1691         .recalc         = &omap2_followparent_recalc,
1692 };
1693
1694 static struct clk fac_ick = {
1695         .name           = "fac_ick",
1696         .parent         = &l4_ck,
1697         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1698         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1699         .enable_bit     = 25,
1700         .recalc         = &omap2_followparent_recalc,
1701 };
1702
1703 static struct clk fac_fck = {
1704         .name           = "fac_fck",
1705         .parent         = &func_12m_ck,
1706         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1707         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1708         .enable_bit     = 25,
1709         .recalc         = &omap2_followparent_recalc,
1710 };
1711
1712 static struct clk eac_ick = {
1713         .name           = "eac_ick",
1714         .parent         = &l4_ck,
1715         .flags          = CLOCK_IN_OMAP242X,
1716         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1717         .enable_bit     = 24,
1718         .recalc         = &omap2_followparent_recalc,
1719 };
1720
1721 static struct clk eac_fck = {
1722         .name           = "eac_fck",
1723         .parent         = &func_96m_ck,
1724         .flags          = CLOCK_IN_OMAP242X,
1725         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1726         .enable_bit     = 24,
1727         .recalc         = &omap2_followparent_recalc,
1728 };
1729
1730 static struct clk hdq_ick = {
1731         .name           = "hdq_ick",
1732         .parent         = &l4_ck,
1733         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1734         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1735         .enable_bit     = 23,
1736         .recalc         = &omap2_followparent_recalc,
1737 };
1738
1739 static struct clk hdq_fck = {
1740         .name           = "hdq_fck",
1741         .parent         = &func_12m_ck,
1742         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1743         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1744         .enable_bit     = 23,
1745         .recalc         = &omap2_followparent_recalc,
1746 };
1747
1748 static struct clk i2c2_ick = {
1749         .name           = "i2c_ick",
1750         .id             = 2,
1751         .parent         = &l4_ck,
1752         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1753         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1754         .enable_bit     = 20,
1755         .recalc         = &omap2_followparent_recalc,
1756 };
1757
1758 static struct clk i2c2_fck = {
1759         .name           = "i2c_fck",
1760         .id             = 2,
1761         .parent         = &func_12m_ck,
1762         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1763         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1764         .enable_bit     = 20,
1765         .recalc         = &omap2_followparent_recalc,
1766 };
1767
1768 static struct clk i2chs2_fck = {
1769         .name           = "i2chs_fck",
1770         .id             = 2,
1771         .parent         = &func_96m_ck,
1772         .flags          = CLOCK_IN_OMAP243X,
1773         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1774         .enable_bit     = 20,
1775         .recalc         = &omap2_followparent_recalc,
1776 };
1777
1778 static struct clk i2c1_ick = {
1779         .name           = "i2c_ick",
1780         .id             = 1,
1781         .parent         = &l4_ck,
1782         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1783         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1784         .enable_bit     = 19,
1785         .recalc         = &omap2_followparent_recalc,
1786 };
1787
1788 static struct clk i2c1_fck = {
1789         .name           = "i2c_fck",
1790         .id             = 1,
1791         .parent         = &func_12m_ck,
1792         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1793         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1794         .enable_bit     = 19,
1795         .recalc         = &omap2_followparent_recalc,
1796 };
1797
1798 static struct clk i2chs1_fck = {
1799         .name           = "i2chs_fck",
1800         .id             = 1,
1801         .parent         = &func_96m_ck,
1802         .flags          = CLOCK_IN_OMAP243X,
1803         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1804         .enable_bit     = 19,
1805         .recalc         = &omap2_followparent_recalc,
1806 };
1807
1808 static struct clk vlynq_ick = {
1809         .name           = "vlynq_ick",
1810         .parent         = &core_l3_ck,
1811         .flags          = CLOCK_IN_OMAP242X,
1812         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1813         .enable_bit     = 3,
1814         .recalc         = &omap2_followparent_recalc,
1815 };
1816
1817 static struct clk vlynq_fck = {
1818         .name           = "vlynq_fck",
1819         .parent         = &func_96m_ck,
1820         .flags          = CLOCK_IN_OMAP242X  | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
1821         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1822         .enable_bit     = 3,
1823         .src_offset     = 15,
1824         .recalc         = &omap2_followparent_recalc,
1825 };
1826
1827 static struct clk sdrc_ick = {
1828         .name           = "sdrc_ick",
1829         .parent         = &l4_ck,
1830         .flags          = CLOCK_IN_OMAP243X,
1831         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP2430_CM_ICLKEN3),
1832         .enable_bit     = 2,
1833         .recalc         = &omap2_followparent_recalc,
1834 };
1835
1836 static struct clk des_ick = {
1837         .name           = "des_ick",
1838         .parent         = &l4_ck,
1839         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1840         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1841         .enable_bit     = 0,
1842         .recalc         = &omap2_followparent_recalc,
1843 };
1844
1845 static struct clk sha_ick = {
1846         .name           = "sha_ick",
1847         .parent         = &l4_ck,
1848         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1849         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1850         .enable_bit     = 1,
1851         .recalc         = &omap2_followparent_recalc,
1852 };
1853
1854 static struct clk rng_ick = {
1855         .name           = "rng_ick",
1856         .parent         = &l4_ck,
1857         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1858         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1859         .enable_bit     = 2,
1860         .recalc         = &omap2_followparent_recalc,
1861 };
1862
1863 static struct clk aes_ick = {
1864         .name           = "aes_ick",
1865         .parent         = &l4_ck,
1866         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1867         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1868         .enable_bit     = 3,
1869         .recalc         = &omap2_followparent_recalc,
1870 };
1871
1872 static struct clk pka_ick = {
1873         .name           = "pka_ick",
1874         .parent         = &l4_ck,
1875         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1876         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1877         .enable_bit     = 4,
1878         .recalc         = &omap2_followparent_recalc,
1879 };
1880
1881 static struct clk usb_fck = {
1882         .name           = "usb_fck",
1883         .parent         = &func_48m_ck,
1884         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1885         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1886         .enable_bit     = 0,
1887         .recalc         = &omap2_followparent_recalc,
1888 };
1889
1890 static struct clk usbhs_ick = {
1891         .name           = "usbhs_ick",
1892         .parent         = &core_l3_ck,
1893         .flags          = CLOCK_IN_OMAP243X,
1894         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1895         .enable_bit     = 6,
1896         .recalc         = &omap2_followparent_recalc,
1897 };
1898
1899 static struct clk mmchs1_ick = {
1900         .name           = "mmchs1_ick",
1901         .parent         = &l4_ck,
1902         .flags          = CLOCK_IN_OMAP243X,
1903         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1904         .enable_bit     = 7,
1905         .recalc         = &omap2_followparent_recalc,
1906 };
1907
1908 static struct clk mmchs1_fck = {
1909         .name           = "mmchs1_fck",
1910         .parent         = &func_96m_ck,
1911         .flags          = CLOCK_IN_OMAP243X,
1912         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1913         .enable_bit     = 7,
1914         .recalc         = &omap2_followparent_recalc,
1915 };
1916
1917 static struct clk mmchs2_ick = {
1918         .name           = "mmchs2_ick",
1919         .parent         = &l4_ck,
1920         .flags          = CLOCK_IN_OMAP243X,
1921         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1922         .enable_bit     = 8,
1923         .recalc         = &omap2_followparent_recalc,
1924 };
1925
1926 static struct clk mmchs2_fck = {
1927         .name           = "mmchs2_fck",
1928         .parent         = &func_96m_ck,
1929         .flags          = CLOCK_IN_OMAP243X,
1930         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1931         .enable_bit     = 8,
1932         .recalc         = &omap2_followparent_recalc,
1933 };
1934
1935 static struct clk gpio5_ick = {
1936         .name           = "gpio5_ick",
1937         .parent         = &l4_ck,
1938         .flags          = CLOCK_IN_OMAP243X,
1939         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1940         .enable_bit     = 10,
1941         .recalc         = &omap2_followparent_recalc,
1942 };
1943
1944 static struct clk gpio5_fck = {
1945         .name           = "gpio5_fck",
1946         .parent         = &func_32k_ck,
1947         .flags          = CLOCK_IN_OMAP243X,
1948         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1949         .enable_bit     = 10,
1950         .recalc         = &omap2_followparent_recalc,
1951 };
1952
1953 static struct clk mdm_intc_ick = {
1954         .name           = "mdm_intc_ick",
1955         .parent         = &l4_ck,
1956         .flags          = CLOCK_IN_OMAP243X,
1957         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1958         .enable_bit     = 11,
1959         .recalc         = &omap2_followparent_recalc,
1960 };
1961
1962 static struct clk mmchsdb1_fck = {
1963         .name           = "mmchsdb1_fck",
1964         .parent         = &func_32k_ck,
1965         .flags          = CLOCK_IN_OMAP243X,
1966         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1967         .enable_bit     = 16,
1968         .recalc         = &omap2_followparent_recalc,
1969 };
1970
1971 static struct clk mmchsdb2_fck = {
1972         .name           = "mmchsdb2_fck",
1973         .parent         = &func_32k_ck,
1974         .flags          = CLOCK_IN_OMAP243X,
1975         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1976         .enable_bit     = 17,
1977         .recalc         = &omap2_followparent_recalc,
1978 };
1979
1980 /*
1981  * This clock is a composite clock which does entire set changes then
1982  * forces a rebalance. It keys on the MPU speed, but it really could
1983  * be any key speed part of a set in the rate table.
1984  *
1985  * to really change a set, you need memory table sets which get changed
1986  * in sram, pre-notifiers & post notifiers, changing the top set, without
1987  * having low level display recalc's won't work... this is why dpm notifiers
1988  * work, isr's off, walk a list of clocks already _off_ and not messing with
1989  * the bus.
1990  *
1991  * This clock should have no parent. It embodies the entire upper level
1992  * active set. A parent will mess up some of the init also.
1993  */
1994 static struct clk virt_prcm_set = {
1995         .name           = "virt_prcm_set",
1996         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1997                                 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
1998         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
1999         .recalc         = &omap2_mpu_recalc,    /* sets are keyed on mpu rate */
2000         .set_rate       = &omap2_select_table_rate,
2001         .round_rate     = &omap2_round_to_table_rate,
2002 };
2003
2004 static struct clk *onchip_clks[] = {
2005         /* external root sources */
2006         &func_32k_ck,
2007         &osc_ck,
2008         &sys_ck,
2009         &alt_ck,
2010         /* internal analog sources */
2011         &dpll_ck,
2012         &apll96_ck,
2013         &apll54_ck,
2014         /* internal prcm root sources */
2015         &func_54m_ck,
2016         &core_ck,
2017         &sleep_ck,
2018         &func_96m_ck,
2019         &func_48m_ck,
2020         &func_12m_ck,
2021         &wdt1_osc_ck,
2022         &sys_clkout,
2023         &sys_clkout2,
2024         &emul_ck,
2025         /* mpu domain clocks */
2026         &mpu_ck,
2027         /* dsp domain clocks */
2028         &iva2_1_fck,            /* 2430 */
2029         &iva2_1_ick,
2030         &dsp_ick,               /* 2420 */
2031         &dsp_fck,
2032         &iva1_ifck,
2033         &iva1_mpu_int_ifck,
2034         /* GFX domain clocks */
2035         &gfx_3d_fck,
2036         &gfx_2d_fck,
2037         &gfx_ick,
2038         /* Modem domain clocks */
2039         &mdm_ick,
2040         &mdm_osc_ck,
2041         /* DSS domain clocks */
2042         &dss_ick,
2043         &dss1_fck,
2044         &dss2_fck,
2045         &dss_54m_fck,
2046         /* L3 domain clocks */
2047         &core_l3_ck,
2048         &ssi_ssr_sst_fck,
2049         &usb_l4_ick,
2050         /* L4 domain clocks */
2051         &l4_ck,                 /* used as both core_l4 and wu_l4 */
2052         &ssi_l4_ick,
2053         /* virtual meta-group clock */
2054         &virt_prcm_set,
2055         /* general l4 interface ck, multi-parent functional clk */
2056         &gpt1_ick,
2057         &gpt1_fck,
2058         &gpt2_ick,
2059         &gpt2_fck,
2060         &gpt3_ick,
2061         &gpt3_fck,
2062         &gpt4_ick,
2063         &gpt4_fck,
2064         &gpt5_ick,
2065         &gpt5_fck,
2066         &gpt6_ick,
2067         &gpt6_fck,
2068         &gpt7_ick,
2069         &gpt7_fck,
2070         &gpt8_ick,
2071         &gpt8_fck,
2072         &gpt9_ick,
2073         &gpt9_fck,
2074         &gpt10_ick,
2075         &gpt10_fck,
2076         &gpt11_ick,
2077         &gpt11_fck,
2078         &gpt12_ick,
2079         &gpt12_fck,
2080         &mcbsp1_ick,
2081         &mcbsp1_fck,
2082         &mcbsp2_ick,
2083         &mcbsp2_fck,
2084         &mcbsp3_ick,
2085         &mcbsp3_fck,
2086         &mcbsp4_ick,
2087         &mcbsp4_fck,
2088         &mcbsp5_ick,
2089         &mcbsp5_fck,
2090         &mcspi1_ick,
2091         &mcspi1_fck,
2092         &mcspi2_ick,
2093         &mcspi2_fck,
2094         &mcspi3_ick,
2095         &mcspi3_fck,
2096         &uart1_ick,
2097         &uart1_fck,
2098         &uart2_ick,
2099         &uart2_fck,
2100         &uart3_ick,
2101         &uart3_fck,
2102         &gpios_ick,
2103         &gpios_fck,
2104         &mpu_wdt_ick,
2105         &mpu_wdt_fck,
2106         &sync_32k_ick,
2107         &wdt1_ick,
2108         &omapctrl_ick,
2109         &icr_ick,
2110         &cam_fck,
2111         &cam_ick,
2112         &mailboxes_ick,
2113         &wdt4_ick,
2114         &wdt4_fck,
2115         &wdt3_ick,
2116         &wdt3_fck,
2117         &mspro_ick,
2118         &mspro_fck,
2119         &mmc_ick,
2120         &mmc_fck,
2121         &fac_ick,
2122         &fac_fck,
2123         &eac_ick,
2124         &eac_fck,
2125         &hdq_ick,
2126         &hdq_fck,
2127         &i2c1_ick,
2128         &i2c1_fck,
2129         &i2chs1_fck,
2130         &i2c2_ick,
2131         &i2c2_fck,
2132         &i2chs2_fck,
2133         &vlynq_ick,
2134         &vlynq_fck,
2135         &sdrc_ick,
2136         &des_ick,
2137         &sha_ick,
2138         &rng_ick,
2139         &aes_ick,
2140         &pka_ick,
2141         &usb_fck,
2142         &usbhs_ick,
2143         &mmchs1_ick,
2144         &mmchs1_fck,
2145         &mmchs2_ick,
2146         &mmchs2_fck,
2147         &gpio5_ick,
2148         &gpio5_fck,
2149         &mdm_intc_ick,
2150         &mmchsdb1_fck,
2151         &mmchsdb2_fck,
2152 };
2153
2154 #endif