arch/arm/mach-omap2/clock.h

   1 /*
   2  *  linux/arch/arm/mach-omap24xx/clock.h
   3  *
   4  *  Copyright (C) 2005 Texas Instruments Inc.
   5  *  Richard Woodruff <r-woodruff2@ti.com>
   6  *  Created for OMAP2.
   7  *
   8  *  Copyright (C) 2004 Nokia corporation
   9  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  10  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
  18 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
  19
  20 static void omap2_sys_clk_recalc(struct clk * clk);
  21 static void omap2_clksel_recalc(struct clk * clk);
  22 static void omap2_followparent_recalc(struct clk * clk);
  23 static void omap2_propagate_rate(struct clk * clk);
  24 static void omap2_mpu_recalc(struct clk * clk);
  25 static int omap2_select_table_rate(struct clk * clk, unsigned long rate);
  26 static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate);
  27 static void omap2_clk_disable(struct clk *clk);
  28 static void omap2_sys_clk_recalc(struct clk * clk);
  29 static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val);
  30 static u32 omap2_clksel_get_divisor(struct clk *clk);
  31
  32 /* REVISIT: should use a clock flag for this, not a magic number */
  33 #define PARENT_CONTROLS_CLOCK   0xff
  34
  35 #define RATE_IN_242X    (1 << 0)
  36 #define RATE_IN_243X    (1 << 1)
  37
  38 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  39  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  40  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  41  */
  42 struct prcm_config {
  43         unsigned long xtal_speed;       /* crystal rate */
  44         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  45         unsigned long mpu_speed;        /* speed of MPU */
  46         unsigned long cm_clksel_mpu;    /* mpu divider */
  47         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  48         unsigned long cm_clksel_gfx;    /* gfx dividers */
  49         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  50         unsigned long cm_clksel1_pll;   /* m,n */
  51         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  52         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  53         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  54         unsigned char flags;
  55 };
  56
  57 /* Mask for clksel which support parent settign in set_rate */
  58 #define SRC_SEL_MASK (CM_CORE_SEL1 | CM_CORE_SEL2 | CM_WKUP_SEL1 | \
  59                         CM_PLL_SEL1 | CM_PLL_SEL2 | CM_SYSCLKOUT_SEL1)
  60
  61 /* Mask for clksel regs which support rate operations */
  62 #define SRC_RATE_SEL_MASK (CM_MPU_SEL1 | CM_DSP_SEL1 | CM_GFX_SEL1 | \
  63                         CM_MODEM_SEL1 | CM_CORE_SEL1 | CM_CORE_SEL2 | \
  64                         CM_WKUP_SEL1 | CM_PLL_SEL1 | CM_PLL_SEL2 | \
  65                         CM_SYSCLKOUT_SEL1)
  66
  67 /*
  68  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  69  * These configurations are characterized by voltage and speed for clocks.
  70  * The device is only validated for certain combinations. One way to express
  71  * these combinations is via the 'ratio's' which the clocks operate with
  72  * respect to each other. These ratio sets are for a given voltage/DPLL
  73  * setting. All configurations can be described by a DPLL setting and a ratio
  74  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  75  *
  76  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  77  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  78  * 2430 (iva2.1, NOdsp, mdm)
  79  */
  80
  81 /* Core fields for cm_clksel, not ratio governed */
  82 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  83 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  84 #define RX_CLKSEL_SSI                   (0x5 << 20)
  85
  86 /*-------------------------------------------------------------------------
  87  * Voltage/DPLL ratios
  88  *-------------------------------------------------------------------------*/
  89
  90 /* 2430 Ratio's, 2430-Ratio Config 1 */
  91 #define R1_CLKSEL_L3                    (4 << 0)
  92 #define R1_CLKSEL_L4                    (2 << 5)
  93 #define R1_CLKSEL_USB                   (4 << 25)
  94 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
  95                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  96                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
  97 #define R1_CLKSEL_MPU                   (2 << 0)
  98 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
  99 #define R1_CLKSEL_DSP                   (2 << 0)
 100 #define R1_CLKSEL_DSP_IF                (2 << 5)
 101 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
 102 #define R1_CLKSEL_GFX                   (2 << 0)
 103 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
 104 #define R1_CLKSEL_MDM                   (4 << 0)
 105 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
 106
 107 /* 2430-Ratio Config 2 */
 108 #define R2_CLKSEL_L3                    (6 << 0)
 109 #define R2_CLKSEL_L4                    (2 << 5)
 110 #define R2_CLKSEL_USB                   (2 << 25)
 111 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
 112                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 113                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
 114 #define R2_CLKSEL_MPU                   (2 << 0)
 115 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 116 #define R2_CLKSEL_DSP                   (2 << 0)
 117 #define R2_CLKSEL_DSP_IF                (3 << 5)
 118 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 119 #define R2_CLKSEL_GFX                   (2 << 0)
 120 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 121 #define R2_CLKSEL_MDM                   (6 << 0)
 122 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 123
 124 /* 2430-Ratio Bootm (BYPASS) */
 125 #define RB_CLKSEL_L3                    (1 << 0)
 126 #define RB_CLKSEL_L4                    (1 << 5)
 127 #define RB_CLKSEL_USB                   (1 << 25)
 128 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 129                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 130                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 131 #define RB_CLKSEL_MPU                   (1 << 0)
 132 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 133 #define RB_CLKSEL_DSP                   (1 << 0)
 134 #define RB_CLKSEL_DSP_IF                (1 << 5)
 135 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 136 #define RB_CLKSEL_GFX                   (1 << 0)
 137 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 138 #define RB_CLKSEL_MDM                   (1 << 0)
 139 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 140
 141 /* 2420 Ratio Equivalents */
 142 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 143 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 144
 145 /* 2420-PRCM III 532MHz core */
 146 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 147 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 148 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 149 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 150                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 151                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 152                                         RIII_CLKSEL_L3
 153 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 154 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 155 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 156 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 157 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 158 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 159 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 160 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 161                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 162                                         RIII_CLKSEL_DSP
 163 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 164 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 165
 166 /* 2420-PRCM II 600MHz core */
 167 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 168 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 169 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 170 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 171                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 172                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 173                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 174 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 175 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 176 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 177 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 178 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 179 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 180 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 181 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 182                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 183                                         RII_CLKSEL_DSP
 184 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 185 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 186
 187 /* 2420-PRCM I 660MHz core */
 188 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 189 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 190 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 191 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 192                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 193                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 194                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 195 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 196 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 197 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 198 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 199 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 200 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 201 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 202 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 203                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 204                                         RI_CLKSEL_DSP
 205 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 206 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 207
 208 /* 2420-PRCM VII (boot) */
 209 #define RVII_CLKSEL_L3                  (1 << 0)
 210 #define RVII_CLKSEL_L4                  (1 << 5)
 211 #define RVII_CLKSEL_DSS1                (1 << 8)
 212 #define RVII_CLKSEL_DSS2                (0 << 13)
 213 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 214 #define RVII_CLKSEL_SSI                 (1 << 20)
 215 #define RVII_CLKSEL_USB                 (1 << 25)
 216
 217 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 218                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 219                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 220
 221 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 222 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 223
 224 #define RVII_CLKSEL_DSP                 (1 << 0)
 225 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 226 #define RVII_SYNC_DSP                   (0 << 7)
 227 #define RVII_CLKSEL_IVA                 (1 << 8)
 228 #define RVII_SYNC_IVA                   (0 << 13)
 229 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 230                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 231
 232 #define RVII_CLKSEL_GFX                 (1 << 0)
 233 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 234
 235 /*-------------------------------------------------------------------------
 236  * 2430 Target modes: Along with each configuration the CPU has several
 237  * modes which goes along with them. Modes mainly are the addition of
 238  * describe DPLL combinations to go along with a ratio.
 239  *-------------------------------------------------------------------------*/
 240
 241 /* Hardware governed */
 242 #define MX_48M_SRC                      (0 << 3)
 243 #define MX_54M_SRC                      (0 << 5)
 244 #define MX_APLLS_CLIKIN_12              (3 << 23)
 245 #define MX_APLLS_CLIKIN_13              (2 << 23)
 246 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 247
 248 /*
 249  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 250  * #2   (ratio1) baseport-target
 251  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 252  */
 253 #define M5A_DPLL_MULT_12                (133 << 12)
 254 #define M5A_DPLL_DIV_12                 (5 << 8)
 255 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 256                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 257                                         MX_APLLS_CLIKIN_12
 258 #define M5A_DPLL_MULT_13                (266 << 12)
 259 #define M5A_DPLL_DIV_13                 (12 << 8)
 260 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 261                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 262                                         MX_APLLS_CLIKIN_13
 263 #define M5A_DPLL_MULT_19                (180 << 12)
 264 #define M5A_DPLL_DIV_19                 (12 << 8)
 265 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 266                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 267                                         MX_APLLS_CLIKIN_19_2
 268 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 269 #define M5B_DPLL_MULT_12                (50 << 12)
 270 #define M5B_DPLL_DIV_12                 (2 << 8)
 271 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 272                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 273                                         MX_APLLS_CLIKIN_12
 274 #define M5B_DPLL_MULT_13                (200 << 12)
 275 #define M5B_DPLL_DIV_13                 (12 << 8)
 276
 277 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 278                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 279                                         MX_APLLS_CLIKIN_13
 280 #define M5B_DPLL_MULT_19                (125 << 12)
 281 #define M5B_DPLL_DIV_19                 (31 << 8)
 282 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 283                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 284                                         MX_APLLS_CLIKIN_19_2
 285 /*
 286  * #4   (ratio2)
 287  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 288  */
 289 #define M3_DPLL_MULT_12                 (55 << 12)
 290 #define M3_DPLL_DIV_12                  (1 << 8)
 291 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 292                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 293                                         MX_APLLS_CLIKIN_12
 294 #define M3_DPLL_MULT_13                 (330 << 12)
 295 #define M3_DPLL_DIV_13                  (12 << 8)
 296 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 297                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 298                                         MX_APLLS_CLIKIN_13
 299 #define M3_DPLL_MULT_19                 (275 << 12)
 300 #define M3_DPLL_DIV_19                  (15 << 8)
 301 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 302                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 303                                         MX_APLLS_CLIKIN_19_2
 304 /* boot (boot) */
 305 #define MB_DPLL_MULT                    (1 << 12)
 306 #define MB_DPLL_DIV                     (0 << 8)
 307 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 308                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 309
 310 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 311                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 312
 313 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 314                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 315
 316 /*
 317  * 2430 - chassis (sedna)
 318  * 165 (ratio1) same as above #2
 319  * 150 (ratio1)
 320  * 133 (ratio2) same as above #4
 321  * 110 (ratio2) same as above #3
 322  * 104 (ratio2)
 323  * boot (boot)
 324  */
 325
 326 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 327 #define MI_DPLL_MULT_12                 (55 << 12)
 328 #define MI_DPLL_DIV_12                  (1 << 8)
 329 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 330                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 331                                         MX_APLLS_CLIKIN_12
 332
 333 /*
 334  * 2420 Equivalent - mode registers
 335  * PRCM II , target DPLL = 2*300MHz = 600MHz
 336  */
 337 #define MII_DPLL_MULT_12                (50 << 12)
 338 #define MII_DPLL_DIV_12                 (1 << 8)
 339 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 340                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 341                                         MX_APLLS_CLIKIN_12
 342 #define MII_DPLL_MULT_13                (300 << 12)
 343 #define MII_DPLL_DIV_13                 (12 << 8)
 344 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 345                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 346                                         MX_APLLS_CLIKIN_13
 347
 348 /* PRCM III target DPLL = 2*266 = 532MHz*/
 349 #define MIII_DPLL_MULT_12               (133 << 12)
 350 #define MIII_DPLL_DIV_12                (5 << 8)
 351 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 352                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 353                                         MX_APLLS_CLIKIN_12
 354 #define MIII_DPLL_MULT_13               (266 << 12)
 355 #define MIII_DPLL_DIV_13                (12 << 8)
 356 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 357                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 358                                         MX_APLLS_CLIKIN_13
 359
 360 /* PRCM VII (boot bypass) */
 361 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 362 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 363
 364 /* High and low operation value */
 365 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 366 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 367
 368 /*
 369  * These represent optimal values for common parts, it won't work for all.
 370  * As long as you scale down, most parameters are still work, they just
 371  * become sub-optimal. The RFR value goes in the opposite direction. If you
 372  * don't adjust it down as your clock period increases the refresh interval
 373  * will not be met. Setting all parameters for complete worst case may work,
 374  * but may cut memory performance by 2x. Due to errata the DLLs need to be
 375  * unlocked and their value needs run time calibration. A dynamic call is
 376  * need for that as no single right value exists acorss production samples.
 377  *
 378  * Only the FULL speed values are given. Current code is such that rate
 379  * changes must be made at DPLLoutx2. The actual value adjustment for low
 380  * frequency operation will be handled by omap_set_performance()
 381  *
 382  * By having the boot loader boot up in the fastest L4 speed available likely
 383  * will result in something which you can switch between.
 384  */
 385 #define V24XX_SDRC_RFR_CTRL_165MHz      (0x00044c00 | 1)
 386 #define V24XX_SDRC_RFR_CTRL_133MHz      (0x0003de00 | 1)
 387 #define V24XX_SDRC_RFR_CTRL_100MHz      (0x0002da01 | 1)
 388 #define V24XX_SDRC_RFR_CTRL_110MHz      (0x0002da01 | 1) /* Need to calc */
 389 #define V24XX_SDRC_RFR_CTRL_BYPASS      (0x00005000 | 1) /* Need to calc */
 390
 391 /* MPU speed defines */
 392 #define S12M    12000000
 393 #define S13M    13000000
 394 #define S19M    19200000
 395 #define S26M    26000000
 396 #define S100M   100000000
 397 #define S133M   133000000
 398 #define S150M   150000000
 399 #define S165M   165000000
 400 #define S200M   200000000
 401 #define S266M   266000000
 402 #define S300M   300000000
 403 #define S330M   330000000
 404 #define S400M   400000000
 405 #define S532M   532000000
 406 #define S600M   600000000
 407 #define S660M   660000000
 408
 409 /*-------------------------------------------------------------------------
 410  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 411  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 412  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 413  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 414  *
 415  * Filling in table based on H4 boards and 2430-SDPs variants available.
 416  * There are quite a few more rates combinations which could be defined.
 417  *
 418  * When multiple values are defined the start up will try and choose the
 419  * fastest one. If a 'fast' value is defined, then automatically, the /2
 420  * one should be included as it can be used.    Generally having more that
 421  * one fast set does not make sense, as static timings need to be changed
 422  * to change the set.    The exception is the bypass setting which is
 423  * availble for low power bypass.
 424  *
 425  * Note: This table needs to be sorted, fastest to slowest.
 426  *-------------------------------------------------------------------------*/
 427 static struct prcm_config rate_table[] = {
 428         /* PRCM I - FAST */
 429         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 430                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 431                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 432                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_165MHz,
 433                 RATE_IN_242X},
 434
 435         /* PRCM II - FAST */
 436         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 437                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 438                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 439                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 440                 RATE_IN_242X},
 441
 442         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 443                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 444                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 445                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 446                 RATE_IN_242X},
 447
 448         /* PRCM III - FAST */
 449         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 450                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 451                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 452                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 453                 RATE_IN_242X},
 454
 455         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 456                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 457                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 458                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 459                 RATE_IN_242X},
 460
 461         /* PRCM II - SLOW */
 462         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 463                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 464                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 465                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 466                 RATE_IN_242X},
 467
 468         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 469                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 470                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 471                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 472                 RATE_IN_242X},
 473
 474         /* PRCM III - SLOW */
 475         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 476                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 477                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 478                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 479                 RATE_IN_242X},
 480
 481         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 482                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 483                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 484                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 485                 RATE_IN_242X},
 486
 487         /* PRCM-VII (boot-bypass) */
 488         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 489                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 490                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 491                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
 492                 RATE_IN_242X},
 493
 494         /* PRCM-VII (boot-bypass) */
 495         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 496                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 497                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 498                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
 499                 RATE_IN_242X},
 500
 501         /* PRCM #3 - ratio2 (ES2) - FAST */
 502         {S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 503                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 504                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 505                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 506                 V24XX_SDRC_RFR_CTRL_110MHz,
 507                 RATE_IN_243X},
 508
 509         /* PRCM #5a - ratio1 - FAST */
 510         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 511                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 512                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 513                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 514                 V24XX_SDRC_RFR_CTRL_133MHz,
 515                 RATE_IN_243X},
 516
 517         /* PRCM #5b - ratio1 - FAST */
 518         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 519                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 520                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 521                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 522                 V24XX_SDRC_RFR_CTRL_100MHz,
 523                 RATE_IN_243X},
 524
 525         /* PRCM #3 - ratio2 (ES2) - SLOW */
 526         {S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 527                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 528                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 529                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 530                 V24XX_SDRC_RFR_CTRL_110MHz,
 531                 RATE_IN_243X},
 532
 533         /* PRCM #5a - ratio1 - SLOW */
 534         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 535                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 536                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 537                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 538                 V24XX_SDRC_RFR_CTRL_133MHz,
 539                 RATE_IN_243X},
 540
 541         /* PRCM #5b - ratio1 - SLOW*/
 542         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 543                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 544                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 545                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 546                 V24XX_SDRC_RFR_CTRL_100MHz,
 547                 RATE_IN_243X},
 548
 549         /* PRCM-boot/bypass */
 550         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 551                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 552                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 553                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 554                 V24XX_SDRC_RFR_CTRL_BYPASS,
 555                 RATE_IN_243X},
 556
 557         /* PRCM-boot/bypass */
 558         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 559                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 560                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 561                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 562                 V24XX_SDRC_RFR_CTRL_BYPASS,
 563                 RATE_IN_243X},
 564
 565         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 566 };
 567
 568 /*-------------------------------------------------------------------------
 569  * 24xx clock tree.
 570  *
 571  * NOTE:In many cases here we are assigning a 'default' parent. In many
 572  *      cases the parent is selectable. The get/set parent calls will also
 573  *      switch sources.
 574  *
 575  *      Many some clocks say always_enabled, but they can be auto idled for
 576  *      power savings. They will always be available upon clock request.
 577  *
 578  *      Several sources are given initial rates which may be wrong, this will
 579  *      be fixed up in the init func.
 580  *
 581  *      Things are broadly separated below by clock domains. It is
 582  *      noteworthy that most periferals have dependencies on multiple clock
 583  *      domains. Many get their interface clocks from the L4 domain, but get
 584  *      functional clocks from fixed sources or other core domain derived
 585  *      clocks.
 586  *-------------------------------------------------------------------------*/
 587
 588 /* Base external input clocks */
 589 static struct clk func_32k_ck = {
 590         .name           = "func_32k_ck",
 591         .rate           = 32000,
 592         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 593                                 RATE_FIXED | ALWAYS_ENABLED,
 594 };
 595
 596 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 597 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 598         .name           = "osc_ck",
 599         .rate           = 26000000,             /* fixed up in clock init */
 600         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 601                                 RATE_FIXED | RATE_PROPAGATES,
 602 };
 603
 604 /* With out modem likely 12MHz, with modem likely 13MHz */
 605 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 606         .name           = "sys_ck",             /* ~ ref_clk also */
 607         .parent         = &osc_ck,
 608         .rate           = 13000000,
 609         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 610                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 611         .rate_offset    = 6, /* sysclkdiv 1 or 2, already handled or no boot */
 612         .recalc         = &omap2_sys_clk_recalc,
 613 };
 614
 615 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 616         .name           = "alt_ck",
 617         .rate           = 54000000,
 618         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 619                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 620         .recalc         = &omap2_propagate_rate,
 621 };
 622
 623 /*
 624  * Analog domain root source clocks
 625  */
 626
 627 /* dpll_ck, is broken out in to special cases through clksel */
 628 static struct clk dpll_ck = {
 629         .name           = "dpll_ck",
 630         .parent         = &sys_ck,              /* Can be func_32k also */
 631         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 632                                 RATE_PROPAGATES | RATE_CKCTL | CM_PLL_SEL1,
 633         .recalc         = &omap2_clksel_recalc,
 634 };
 635
 636 static struct clk apll96_ck = {
 637         .name           = "apll96_ck",
 638         .parent         = &sys_ck,
 639         .rate           = 96000000,
 640         .flags          = CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X |
 641                                 RATE_FIXED | RATE_PROPAGATES,
 642         .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
 643         .enable_bit     = 0x2,
 644         .recalc         = &omap2_propagate_rate,
 645 };
 646
 647 static struct clk apll54_ck = {
 648         .name           = "apll54_ck",
 649         .parent         = &sys_ck,
 650         .rate           = 54000000,
 651         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 652                                 RATE_FIXED | RATE_PROPAGATES,
 653         .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
 654         .enable_bit     = 0x6,
 655         .recalc         = &omap2_propagate_rate,
 656 };
 657
 658 /*
 659  * PRCM digital base sources
 660  */
 661 static struct clk func_54m_ck = {
 662         .name           = "func_54m_ck",
 663         .parent         = &apll54_ck,   /* can also be alt_clk */
 664         .rate           = 54000000,
 665         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 666                                 RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
 667         .src_offset     = 5,
 668         .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
 669         .enable_bit     = PARENT_CONTROLS_CLOCK,
 670         .recalc         = &omap2_propagate_rate,
 671 };
 672
 673 static struct clk core_ck = {
 674         .name           = "core_ck",
 675         .parent         = &dpll_ck,             /* can also be 32k */
 676         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 677                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 678         .recalc         = &omap2_propagate_rate,
 679 };
 680
 681 static struct clk sleep_ck = {          /* sys_clk or 32k */
 682         .name           = "sleep_ck",
 683         .parent         = &func_32k_ck,
 684         .rate           = 32000,
 685         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 686         .recalc         = &omap2_propagate_rate,
 687 };
 688
 689 static struct clk func_96m_ck = {
 690         .name           = "func_96m_ck",
 691         .parent         = &apll96_ck,
 692         .rate           = 96000000,
 693         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 694                                 RATE_FIXED | RATE_PROPAGATES,
 695         .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
 696         .enable_bit     = PARENT_CONTROLS_CLOCK,
 697         .recalc         = &omap2_propagate_rate,
 698 };
 699
 700 static struct clk func_48m_ck = {
 701         .name           = "func_48m_ck",
 702         .parent         = &apll96_ck,    /* 96M or Alt */
 703         .rate           = 48000000,
 704         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 705                                 RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
 706         .src_offset     = 3,
 707         .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
 708         .enable_bit     = PARENT_CONTROLS_CLOCK,
 709         .recalc         = &omap2_propagate_rate,
 710 };
 711
 712 static struct clk func_12m_ck = {
 713         .name           = "func_12m_ck",
 714         .parent         = &func_48m_ck,
 715         .rate           = 12000000,
 716         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 717                                 RATE_FIXED | RATE_PROPAGATES,
 718         .recalc         = &omap2_propagate_rate,
 719         .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
 720         .enable_bit     = PARENT_CONTROLS_CLOCK,
 721 };
 722
 723 /* Secure timer, only available in secure mode */
 724 static struct clk wdt1_osc_ck = {
 725         .name           = "ck_wdt1_osc",
 726         .parent         = &osc_ck,
 727         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 728         .recalc         = &omap2_followparent_recalc,
 729 };
 730
 731 static struct clk sys_clkout = {
 732         .name           = "sys_clkout",
 733         .parent         = &func_54m_ck,
 734         .rate           = 54000000,
 735         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 736                                 CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
 737         .src_offset     = 0,
 738         .enable_reg     = (void __iomem *)&PRCM_CLKOUT_CTRL,
 739         .enable_bit     = 7,
 740         .rate_offset    = 3,
 741         .recalc         = &omap2_clksel_recalc,
 742 };
 743
 744 /* In 2430, new in 2420 ES2 */
 745 static struct clk sys_clkout2 = {
 746         .name           = "sys_clkout2",
 747         .parent         = &func_54m_ck,
 748         .rate           = 54000000,
 749         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 750                                 CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
 751         .src_offset     = 8,
 752         .enable_reg     = (void __iomem *)&PRCM_CLKOUT_CTRL,
 753         .enable_bit     = 15,
 754         .rate_offset    = 11,
 755         .recalc         = &omap2_clksel_recalc,
 756 };
 757
 758 static struct clk emul_ck = {
 759         .name           = "emul_ck",
 760         .parent         = &func_54m_ck,
 761         .flags          = CLOCK_IN_OMAP242X,
 762         .enable_reg     = (void __iomem *)&PRCM_CLKEMUL_CTRL,
 763         .enable_bit     = 0,
 764         .recalc         = &omap2_propagate_rate,
 765
 766 };
 767
 768 /*
 769  * MPU clock domain
 770  *      Clocks:
 771  *              MPU_FCLK, MPU_ICLK
 772  *              INT_M_FCLK, INT_M_I_CLK
 773  *
 774  * - Individual clocks are hardware managed.
 775  * - Base divider comes from: CM_CLKSEL_MPU
 776  *
 777  */
 778 static struct clk mpu_ck = {    /* Control cpu */
 779         .name           = "mpu_ck",
 780         .parent         = &core_ck,
 781         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL |
 782                                 ALWAYS_ENABLED | CM_MPU_SEL1 | DELAYED_APP |
 783                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
 784         .rate_offset    = 0,    /* bits 0-4 */
 785         .recalc         = &omap2_clksel_recalc,
 786 };
 787
 788 /*
 789  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
 790  * Clocks:
 791  *      2430: IVA2.1_FCLK, IVA2.1_ICLK
 792  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
 793  */
 794 static struct clk iva2_1_fck = {
 795         .name           = "iva2_1_fck",
 796         .parent         = &core_ck,
 797         .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
 798                                 DELAYED_APP | RATE_PROPAGATES |
 799                                 CONFIG_PARTICIPANT,
 800         .rate_offset    = 0,
 801         .enable_reg     = (void __iomem *)&CM_FCLKEN_DSP,
 802         .enable_bit     = 0,
 803         .recalc         = &omap2_clksel_recalc,
 804 };
 805
 806 static struct clk iva2_1_ick = {
 807         .name           = "iva2_1_ick",
 808         .parent         = &iva2_1_fck,
 809         .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
 810                                 DELAYED_APP | CONFIG_PARTICIPANT,
 811         .rate_offset    = 5,
 812         .recalc         = &omap2_clksel_recalc,
 813 };
 814
 815 /*
 816  * Won't be too specific here. The core clock comes into this block
 817  * it is divided then tee'ed. One branch goes directly to xyz enable
 818  * controls. The other branch gets further divided by 2 then possibly
 819  * routed into a synchronizer and out of clocks abc.
 820  */
 821 static struct clk dsp_fck = {
 822         .name           = "dsp_fck",
 823         .parent         = &core_ck,
 824         .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
 825                         DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
 826         .rate_offset    = 0,
 827         .enable_reg     = (void __iomem *)&CM_FCLKEN_DSP,
 828         .enable_bit     = 0,
 829         .recalc         = &omap2_clksel_recalc,
 830 };
 831
 832 static struct clk dsp_ick = {
 833         .name           = "dsp_ick",     /* apparently ipi and isp */
 834         .parent         = &dsp_fck,
 835         .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
 836                                 DELAYED_APP | CONFIG_PARTICIPANT,
 837         .rate_offset    = 5,
 838         .enable_reg     = (void __iomem *)&CM_ICLKEN_DSP,
 839         .enable_bit     = 1,            /* for ipi */
 840         .recalc         = &omap2_clksel_recalc,
 841 };
 842
 843 static struct clk iva1_ifck = {
 844         .name           = "iva1_ifck",
 845         .parent         = &core_ck,
 846         .flags          = CLOCK_IN_OMAP242X | CM_DSP_SEL1 | RATE_CKCTL |
 847                         CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
 848         .rate_offset    = 8,
 849         .enable_reg     = (void __iomem *)&CM_FCLKEN_DSP,
 850         .enable_bit     = 10,
 851         .recalc         = &omap2_clksel_recalc,
 852 };
 853
 854 /* IVA1 mpu/int/i/f clocks are /2 of parent */
 855 static struct clk iva1_mpu_int_ifck = {
 856         .name           = "iva1_mpu_int_ifck",
 857         .parent         = &iva1_ifck,
 858         .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1,
 859         .enable_reg     = (void __iomem *)&CM_FCLKEN_DSP,
 860         .enable_bit     = 8,
 861         .recalc         = &omap2_clksel_recalc,
 862 };
 863
 864 /*
 865  * L3 clock domain
 866  * L3 clocks are used for both interface and functional clocks to
 867  * multiple entities. Some of these clocks are completely managed
 868  * by hardware, and some others allow software control. Hardware
 869  * managed ones general are based on directly CLK_REQ signals and
 870  * various auto idle settings. The functional spec sets many of these
 871  * as 'tie-high' for their enables.
 872  *
 873  * I-CLOCKS:
 874  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
 875  *      CAM, HS-USB.
 876  * F-CLOCK
 877  *      SSI.
 878  *
 879  * GPMC memories and SDRC have timing and clock sensitive registers which
 880  * may very well need notification when the clock changes. Currently for low
 881  * operating points, these are taken care of in sleep.S.
 882  */
 883 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
 884         .name           = "core_l3_ck",
 885         .parent         = &core_ck,
 886         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 887                                 RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
 888                                 DELAYED_APP | CONFIG_PARTICIPANT |
 889                                 RATE_PROPAGATES,
 890         .rate_offset    = 0,
 891         .recalc         = &omap2_clksel_recalc,
 892 };
 893
 894 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
 895         .name           = "usb_l4_ick",
 896         .parent         = &core_l3_ck,
 897         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 898                                 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP |
 899                                 CONFIG_PARTICIPANT,
 900         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
 901         .enable_bit     = 0,
 902         .rate_offset    = 25,
 903         .recalc         = &omap2_clksel_recalc,
 904 };
 905
 906 /*
 907  * SSI is in L3 management domain, its direct parent is core not l3,
 908  * many core power domain entities are grouped into the L3 clock
 909  * domain.
 910  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
 911  *
 912  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
 913  */
 914 static struct clk ssi_ssr_sst_fck = {
 915         .name           = "ssi_fck",
 916         .parent         = &core_ck,
 917         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 918                                 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
 919         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,     /* bit 1 */
 920         .enable_bit     = 1,
 921         .rate_offset    = 20,
 922         .recalc         = &omap2_clksel_recalc,
 923 };
 924
 925 /*
 926  * GFX clock domain
 927  *      Clocks:
 928  * GFX_FCLK, GFX_ICLK
 929  * GFX_CG1(2d), GFX_CG2(3d)
 930  *
 931  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
 932  * The 2d and 3d clocks run at a hardware determined
 933  * divided value of fclk.
 934  *
 935  */
 936 static struct clk gfx_3d_fck = {
 937         .name           = "gfx_3d_fck",
 938         .parent         = &core_l3_ck,
 939         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 940                                 RATE_CKCTL | CM_GFX_SEL1,
 941         .enable_reg     = (void __iomem *)&CM_FCLKEN_GFX,
 942         .enable_bit     = 2,
 943         .rate_offset    = 0,
 944         .recalc         = &omap2_clksel_recalc,
 945 };
 946
 947 static struct clk gfx_2d_fck = {
 948         .name           = "gfx_2d_fck",
 949         .parent         = &core_l3_ck,
 950         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 951                                 RATE_CKCTL | CM_GFX_SEL1,
 952         .enable_reg     = (void __iomem *)&CM_FCLKEN_GFX,
 953         .enable_bit     = 1,
 954         .rate_offset    = 0,
 955         .recalc         = &omap2_clksel_recalc,
 956 };
 957
 958 static struct clk gfx_ick = {
 959         .name           = "gfx_ick",            /* From l3 */
 960         .parent         = &core_l3_ck,
 961         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 962                                 RATE_CKCTL,
 963         .enable_reg     = (void __iomem *)&CM_ICLKEN_GFX,       /* bit 0 */
 964         .enable_bit     = 0,
 965         .recalc         = &omap2_followparent_recalc,
 966 };
 967
 968 /*
 969  * Modem clock domain (2430)
 970  *      CLOCKS:
 971  *              MDM_OSC_CLK
 972  *              MDM_ICLK
 973  */
 974 static struct clk mdm_ick = {           /* used both as a ick and fck */
 975         .name           = "mdm_ick",
 976         .parent         = &core_ck,
 977         .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_MODEM_SEL1 |
 978                                 DELAYED_APP | CONFIG_PARTICIPANT,
 979         .rate_offset    = 0,
 980         .enable_reg     = (void __iomem *)&CM_ICLKEN_MDM,
 981         .enable_bit     = 0,
 982         .recalc         = &omap2_clksel_recalc,
 983 };
 984
 985 static struct clk mdm_osc_ck = {
 986         .name           = "mdm_osc_ck",
 987         .rate           = 26000000,
 988         .parent         = &osc_ck,
 989         .flags          = CLOCK_IN_OMAP243X | RATE_FIXED,
 990         .enable_reg     = (void __iomem *)&CM_FCLKEN_MDM,
 991         .enable_bit     = 1,
 992         .recalc         = &omap2_followparent_recalc,
 993 };
 994
 995 /*
 996  * L4 clock management domain
 997  *
 998  * This domain contains lots of interface clocks from the L4 interface, some
 999  * functional clocks.   Fixed APLL functional source clocks are managed in
1000  * this domain.
1001  */
1002 static struct clk l4_ck = {             /* used both as an ick and fck */
1003         .name           = "l4_ck",
1004         .parent         = &core_l3_ck,
1005         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1006                                 RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
1007                                 DELAYED_APP | RATE_PROPAGATES,
1008         .rate_offset    = 5,
1009         .recalc         = &omap2_clksel_recalc,
1010 };
1011
1012 static struct clk ssi_l4_ick = {
1013         .name           = "ssi_l4_ick",
1014         .parent         = &l4_ck,
1015         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
1016         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,     /* bit 1 */
1017         .enable_bit     = 1,
1018         .recalc         = &omap2_followparent_recalc,
1019 };
1020
1021 /*
1022  * DSS clock domain
1023  * CLOCKs:
1024  * DSS_L4_ICLK, DSS_L3_ICLK,
1025  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1026  *
1027  * DSS is both initiator and target.
1028  */
1029 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1030         .name           = "dss_ick",
1031         .parent         = &l4_ck,       /* really both l3 and l4 */
1032         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
1033         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1034         .enable_bit     = 0,
1035         .recalc         = &omap2_followparent_recalc,
1036 };
1037
1038 static struct clk dss1_fck = {
1039         .name           = "dss1_fck",
1040         .parent         = &core_ck,             /* Core or sys */
1041         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1042                                 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
1043         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1044         .enable_bit     = 0,
1045         .rate_offset    = 8,
1046         .src_offset     = 8,
1047         .recalc         = &omap2_clksel_recalc,
1048 };
1049
1050 static struct clk dss2_fck = {          /* Alt clk used in power management */
1051         .name           = "dss2_fck",
1052         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1053         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1054                                 RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED |
1055                                 DELAYED_APP,
1056         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1057         .enable_bit     = 1,
1058         .src_offset     = 13,
1059         .recalc         = &omap2_followparent_recalc,
1060 };
1061
1062 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1063         .name           = "dss_54m_fck",        /* 54m tv clk */
1064         .parent         = &func_54m_ck,
1065         .rate           = 54000000,
1066         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1067                                 RATE_FIXED | RATE_PROPAGATES,
1068         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1069         .enable_bit     = 2,
1070         .recalc         = &omap2_propagate_rate,
1071 };
1072
1073 /*
1074  * CORE power domain ICLK & FCLK defines.
1075  * Many of the these can have more than one possible parent. Entries
1076  * here will likely have an L4 interface parent, and may have multiple
1077  * functional clock parents.
1078  */
1079 static struct clk gpt1_ick = {
1080         .name           = "gpt1_ick",
1081         .parent         = &l4_ck,
1082         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1083         .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,      /* Bit0 */
1084         .enable_bit     = 0,
1085         .recalc         = &omap2_followparent_recalc,
1086 };
1087
1088 static struct clk gpt1_fck = {
1089         .name           = "gpt1_fck",
1090         .parent         = &func_32k_ck,
1091         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1092                                 CM_WKUP_SEL1,
1093         .enable_reg     = (void __iomem *)&CM_FCLKEN_WKUP,      /* Bit0 */
1094         .enable_bit     = 0,
1095         .src_offset     = 0,
1096         .recalc         = &omap2_followparent_recalc,
1097 };
1098
1099 static struct clk gpt2_ick = {
1100         .name           = "gpt2_ick",
1101         .parent         = &l4_ck,
1102         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1103         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,     /* Bit4 */
1104         .enable_bit     = 4,
1105         .recalc         = &omap2_followparent_recalc,
1106 };
1107
1108 static struct clk gpt2_fck = {
1109         .name           = "gpt2_fck",
1110         .parent         = &func_32k_ck,
1111         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1112                                 CM_CORE_SEL2,
1113         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1114         .enable_bit     = 4,
1115         .src_offset     = 2,
1116         .recalc         = &omap2_followparent_recalc,
1117 };
1118
1119 static struct clk gpt3_ick = {
1120         .name           = "gpt3_ick",
1121         .parent         = &l4_ck,
1122         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1123         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,     /* Bit5 */
1124         .enable_bit     = 5,
1125         .recalc         = &omap2_followparent_recalc,
1126 };
1127
1128 static struct clk gpt3_fck = {
1129         .name           = "gpt3_fck",
1130         .parent         = &func_32k_ck,
1131         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1132                                 CM_CORE_SEL2,
1133         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1134         .enable_bit     = 5,
1135         .src_offset     = 4,
1136         .recalc         = &omap2_followparent_recalc,
1137 };
1138
1139 static struct clk gpt4_ick = {
1140         .name           = "gpt4_ick",
1141         .parent         = &l4_ck,
1142         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1143         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,     /* Bit6 */
1144         .enable_bit     = 6,
1145         .recalc         = &omap2_followparent_recalc,
1146 };
1147
1148 static struct clk gpt4_fck = {
1149         .name           = "gpt4_fck",
1150         .parent         = &func_32k_ck,
1151         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1152                                 CM_CORE_SEL2,
1153         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1154         .enable_bit     = 6,
1155         .src_offset     = 6,
1156         .recalc         = &omap2_followparent_recalc,
1157 };
1158
1159 static struct clk gpt5_ick = {
1160         .name           = "gpt5_ick",
1161         .parent         = &l4_ck,
1162         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1163         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* Bit7 */
1164         .enable_bit     = 7,
1165         .recalc         = &omap2_followparent_recalc,
1166 };
1167
1168 static struct clk gpt5_fck = {
1169         .name           = "gpt5_fck",
1170         .parent         = &func_32k_ck,
1171         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1172                                 CM_CORE_SEL2,
1173         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1174         .enable_bit     = 7,
1175         .src_offset     = 8,
1176         .recalc         = &omap2_followparent_recalc,
1177 };
1178
1179 static struct clk gpt6_ick = {
1180         .name           = "gpt6_ick",
1181         .parent         = &l4_ck,
1182         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1183         .enable_bit     = 8,
1184         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* bit8 */
1185         .recalc         = &omap2_followparent_recalc,
1186 };
1187
1188 static struct clk gpt6_fck = {
1189         .name           = "gpt6_fck",
1190         .parent         = &func_32k_ck,
1191         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1192                                 CM_CORE_SEL2,
1193         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1194         .enable_bit     = 8,
1195         .src_offset     = 10,
1196         .recalc         = &omap2_followparent_recalc,
1197 };
1198
1199 static struct clk gpt7_ick = {
1200         .name           = "gpt7_ick",
1201         .parent         = &l4_ck,
1202         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1203         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* bit9 */
1204         .enable_bit     = 9,
1205         .recalc         = &omap2_followparent_recalc,
1206 };
1207
1208 static struct clk gpt7_fck = {
1209         .name           = "gpt7_fck",
1210         .parent         = &func_32k_ck,
1211         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1212                                 CM_CORE_SEL2,
1213         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1214         .enable_bit     = 9,
1215         .src_offset     = 12,
1216         .recalc         = &omap2_followparent_recalc,
1217 };
1218
1219 static struct clk gpt8_ick = {
1220         .name           = "gpt8_ick",
1221         .parent         = &l4_ck,
1222         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1223         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* bit10 */
1224         .enable_bit     = 10,
1225         .recalc         = &omap2_followparent_recalc,
1226 };
1227
1228 static struct clk gpt8_fck = {
1229         .name           = "gpt8_fck",
1230         .parent         = &func_32k_ck,
1231         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1232                                 CM_CORE_SEL2,
1233         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1234         .enable_bit     = 10,
1235         .src_offset     = 14,
1236         .recalc         = &omap2_followparent_recalc,
1237 };
1238
1239 static struct clk gpt9_ick = {
1240         .name           = "gpt9_ick",
1241         .parent         = &l4_ck,
1242         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1243         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1244         .enable_bit     = 11,
1245         .recalc         = &omap2_followparent_recalc,
1246 };
1247
1248 static struct clk gpt9_fck = {
1249         .name           = "gpt9_fck",
1250         .parent         = &func_32k_ck,
1251         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1252                                         CM_CORE_SEL2,
1253         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1254         .enable_bit     = 11,
1255         .src_offset     = 16,
1256         .recalc         = &omap2_followparent_recalc,
1257 };
1258
1259 static struct clk gpt10_ick = {
1260         .name           = "gpt10_ick",
1261         .parent         = &l4_ck,
1262         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1263         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1264         .enable_bit     = 12,
1265         .recalc         = &omap2_followparent_recalc,
1266 };
1267
1268 static struct clk gpt10_fck = {
1269         .name           = "gpt10_fck",
1270         .parent         = &func_32k_ck,
1271         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1272                                         CM_CORE_SEL2,
1273         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1274         .enable_bit     = 12,
1275         .src_offset     = 18,
1276         .recalc         = &omap2_followparent_recalc,
1277 };
1278
1279 static struct clk gpt11_ick = {
1280         .name           = "gpt11_ick",
1281         .parent         = &l4_ck,
1282         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1283         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1284         .enable_bit     = 13,
1285         .recalc         = &omap2_followparent_recalc,
1286 };
1287
1288 static struct clk gpt11_fck = {
1289         .name           = "gpt11_fck",
1290         .parent         = &func_32k_ck,
1291         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1292                                         CM_CORE_SEL2,
1293         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1294         .enable_bit     = 13,
1295         .src_offset     = 20,
1296         .recalc         = &omap2_followparent_recalc,
1297 };
1298
1299 static struct clk gpt12_ick = {
1300         .name           = "gpt12_ick",
1301         .parent         = &l4_ck,
1302         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1303         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* bit14 */
1304         .enable_bit     = 14,
1305         .recalc         = &omap2_followparent_recalc,
1306 };
1307
1308 static struct clk gpt12_fck = {
1309         .name           = "gpt12_fck",
1310         .parent         = &func_32k_ck,
1311         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1312                                         CM_CORE_SEL2,
1313         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1314         .enable_bit     = 14,
1315         .src_offset     = 22,
1316         .recalc         = &omap2_followparent_recalc,
1317 };
1318
1319 static struct clk mcbsp1_ick = {
1320         .name           = "mcbsp1_ick",
1321         .parent         = &l4_ck,
1322         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1323         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* bit16 */
1324         .enable_bit     = 15,
1325         .recalc         = &omap2_followparent_recalc,
1326 };
1327
1328 static struct clk mcbsp1_fck = {
1329         .name           = "mcbsp1_fck",
1330         .parent         = &func_96m_ck,
1331         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1332         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1333         .enable_bit     = 15,
1334         .recalc         = &omap2_followparent_recalc,
1335 };
1336
1337 static struct clk mcbsp2_ick = {
1338         .name           = "mcbsp2_ick",
1339         .parent         = &l4_ck,
1340         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1341         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1342         .enable_bit     = 16,
1343         .recalc         = &omap2_followparent_recalc,
1344 };
1345
1346 static struct clk mcbsp2_fck = {
1347         .name           = "mcbsp2_fck",
1348         .parent         = &func_96m_ck,
1349         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1350         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1351         .enable_bit     = 16,
1352         .recalc         = &omap2_followparent_recalc,
1353 };
1354
1355 static struct clk mcbsp3_ick = {
1356         .name           = "mcbsp3_ick",
1357         .parent         = &l4_ck,
1358         .flags          = CLOCK_IN_OMAP243X,
1359         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
1360         .enable_bit     = 3,
1361         .recalc         = &omap2_followparent_recalc,
1362 };
1363
1364 static struct clk mcbsp3_fck = {
1365         .name           = "mcbsp3_fck",
1366         .parent         = &func_96m_ck,
1367         .flags          = CLOCK_IN_OMAP243X,
1368         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1369         .enable_bit     = 3,
1370         .recalc         = &omap2_followparent_recalc,
1371 };
1372
1373 static struct clk mcbsp4_ick = {
1374         .name           = "mcbsp4_ick",
1375         .parent         = &l4_ck,
1376         .flags          = CLOCK_IN_OMAP243X,
1377         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
1378         .enable_bit     = 4,
1379         .recalc         = &omap2_followparent_recalc,
1380 };
1381
1382 static struct clk mcbsp4_fck = {
1383         .name           = "mcbsp4_fck",
1384         .parent         = &func_96m_ck,
1385         .flags          = CLOCK_IN_OMAP243X,
1386         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1387         .enable_bit     = 4,
1388         .recalc         = &omap2_followparent_recalc,
1389 };
1390
1391 static struct clk mcbsp5_ick = {
1392         .name           = "mcbsp5_ick",
1393         .parent         = &l4_ck,
1394         .flags          = CLOCK_IN_OMAP243X,
1395         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
1396         .enable_bit     = 5,
1397         .recalc         = &omap2_followparent_recalc,
1398 };
1399
1400 static struct clk mcbsp5_fck = {
1401         .name           = "mcbsp5_fck",
1402         .parent         = &func_96m_ck,
1403         .flags          = CLOCK_IN_OMAP243X,
1404         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1405         .enable_bit     = 5,
1406         .recalc         = &omap2_followparent_recalc,
1407 };
1408
1409 static struct clk mcspi1_ick = {
1410         .name           = "mcspi_ick",
1411         .id             = 1,
1412         .parent         = &l4_ck,
1413         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1414         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1415         .enable_bit     = 17,
1416         .recalc         = &omap2_followparent_recalc,
1417 };
1418
1419 static struct clk mcspi1_fck = {
1420         .name           = "mcspi_fck",
1421         .id             = 1,
1422         .parent         = &func_48m_ck,
1423         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1424         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1425         .enable_bit     = 17,
1426         .recalc         = &omap2_followparent_recalc,
1427 };
1428
1429 static struct clk mcspi2_ick = {
1430         .name           = "mcspi_ick",
1431         .id             = 2,
1432         .parent         = &l4_ck,
1433         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1434         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1435         .enable_bit     = 18,
1436         .recalc         = &omap2_followparent_recalc,
1437 };
1438
1439 static struct clk mcspi2_fck = {
1440         .name           = "mcspi_fck",
1441         .id             = 2,
1442         .parent         = &func_48m_ck,
1443         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1444         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1445         .enable_bit     = 18,
1446         .recalc         = &omap2_followparent_recalc,
1447 };
1448
1449 static struct clk mcspi3_ick = {
1450         .name           = "mcspi_ick",
1451         .id             = 3,
1452         .parent         = &l4_ck,
1453         .flags          = CLOCK_IN_OMAP243X,
1454         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
1455         .enable_bit     = 9,
1456         .recalc         = &omap2_followparent_recalc,
1457 };
1458
1459 static struct clk mcspi3_fck = {
1460         .name           = "mcspi_fck",
1461         .id             = 3,
1462         .parent         = &func_48m_ck,
1463         .flags          = CLOCK_IN_OMAP243X,
1464         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1465         .enable_bit     = 9,
1466         .recalc         = &omap2_followparent_recalc,
1467 };
1468
1469 static struct clk uart1_ick = {
1470         .name           = "uart1_ick",
1471         .parent         = &l4_ck,
1472         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1473         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1474         .enable_bit     = 21,
1475         .recalc         = &omap2_followparent_recalc,
1476 };
1477
1478 static struct clk uart1_fck = {
1479         .name           = "uart1_fck",
1480         .parent         = &func_48m_ck,
1481         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1482         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1483         .enable_bit     = 21,
1484         .recalc         = &omap2_followparent_recalc,
1485 };
1486
1487 static struct clk uart2_ick = {
1488         .name           = "uart2_ick",
1489         .parent         = &l4_ck,
1490         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1491         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1492         .enable_bit     = 22,
1493         .recalc         = &omap2_followparent_recalc,
1494 };
1495
1496 static struct clk uart2_fck = {
1497         .name           = "uart2_fck",
1498         .parent         = &func_48m_ck,
1499         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1500         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1501         .enable_bit     = 22,
1502         .recalc         = &omap2_followparent_recalc,
1503 };
1504
1505 static struct clk uart3_ick = {
1506         .name           = "uart3_ick",
1507         .parent         = &l4_ck,
1508         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1509         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
1510         .enable_bit     = 2,
1511         .recalc         = &omap2_followparent_recalc,
1512 };
1513
1514 static struct clk uart3_fck = {
1515         .name           = "uart3_fck",
1516         .parent         = &func_48m_ck,
1517         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1518         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1519         .enable_bit     = 2,
1520         .recalc         = &omap2_followparent_recalc,
1521 };
1522
1523 static struct clk gpios_ick = {
1524         .name           = "gpios_ick",
1525         .parent         = &l4_ck,
1526         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1527         .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
1528         .enable_bit     = 2,
1529         .recalc         = &omap2_followparent_recalc,
1530 };
1531
1532 static struct clk gpios_fck = {
1533         .name           = "gpios_fck",
1534         .parent         = &func_32k_ck,
1535         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1536         .enable_reg     = (void __iomem *)&CM_FCLKEN_WKUP,
1537         .enable_bit     = 2,
1538         .recalc         = &omap2_followparent_recalc,
1539 };
1540
1541 static struct clk mpu_wdt_ick = {
1542         .name           = "mpu_wdt_ick",
1543         .parent         = &l4_ck,
1544         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1545         .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
1546         .enable_bit     = 3,
1547         .recalc         = &omap2_followparent_recalc,
1548 };
1549
1550 static struct clk mpu_wdt_fck = {
1551         .name           = "mpu_wdt_fck",
1552         .parent         = &func_32k_ck,
1553         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1554         .enable_reg     = (void __iomem *)&CM_FCLKEN_WKUP,
1555         .enable_bit     = 3,
1556         .recalc         = &omap2_followparent_recalc,
1557 };
1558
1559 static struct clk sync_32k_ick = {
1560         .name           = "sync_32k_ick",
1561         .parent         = &l4_ck,
1562         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1563         .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
1564         .enable_bit     = 1,
1565         .recalc         = &omap2_followparent_recalc,
1566 };
1567 static struct clk wdt1_ick = {
1568         .name           = "wdt1_ick",
1569         .parent         = &l4_ck,
1570         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1571         .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
1572         .enable_bit     = 4,
1573         .recalc         = &omap2_followparent_recalc,
1574 };
1575 static struct clk omapctrl_ick = {
1576         .name           = "omapctrl_ick",
1577         .parent         = &l4_ck,
1578         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1579         .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
1580         .enable_bit     = 5,
1581         .recalc         = &omap2_followparent_recalc,
1582 };
1583 static struct clk icr_ick = {
1584         .name           = "icr_ick",
1585         .parent         = &l4_ck,
1586         .flags          = CLOCK_IN_OMAP243X,
1587         .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
1588         .enable_bit     = 6,
1589         .recalc         = &omap2_followparent_recalc,
1590 };
1591
1592 static struct clk cam_ick = {
1593         .name           = "cam_ick",
1594         .parent         = &l4_ck,
1595         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1596         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1597         .enable_bit     = 31,
1598         .recalc         = &omap2_followparent_recalc,
1599 };
1600
1601 static struct clk cam_fck = {
1602         .name           = "cam_fck",
1603         .parent         = &func_96m_ck,
1604         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1605         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1606         .enable_bit     = 31,
1607         .recalc         = &omap2_followparent_recalc,
1608 };
1609
1610 static struct clk mailboxes_ick = {
1611         .name           = "mailboxes_ick",
1612         .parent         = &l4_ck,
1613         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1614         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1615         .enable_bit     = 30,
1616         .recalc         = &omap2_followparent_recalc,
1617 };
1618
1619 static struct clk wdt4_ick = {
1620         .name           = "wdt4_ick",
1621         .parent         = &l4_ck,
1622         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1623         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1624         .enable_bit     = 29,
1625         .recalc         = &omap2_followparent_recalc,
1626 };
1627
1628 static struct clk wdt4_fck = {
1629         .name           = "wdt4_fck",
1630         .parent         = &func_32k_ck,
1631         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1632         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1633         .enable_bit     = 29,
1634         .recalc         = &omap2_followparent_recalc,
1635 };
1636
1637 static struct clk wdt3_ick = {
1638         .name           = "wdt3_ick",
1639         .parent         = &l4_ck,
1640         .flags          = CLOCK_IN_OMAP242X,
1641         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1642         .enable_bit     = 28,
1643         .recalc         = &omap2_followparent_recalc,
1644 };
1645
1646 static struct clk wdt3_fck = {
1647         .name           = "wdt3_fck",
1648         .parent         = &func_32k_ck,
1649         .flags          = CLOCK_IN_OMAP242X,
1650         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1651         .enable_bit     = 28,
1652         .recalc         = &omap2_followparent_recalc,
1653 };
1654
1655 static struct clk mspro_ick = {
1656         .name           = "mspro_ick",
1657         .parent         = &l4_ck,
1658         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1659         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1660         .enable_bit     = 27,
1661         .recalc         = &omap2_followparent_recalc,
1662 };
1663
1664 static struct clk mspro_fck = {
1665         .name           = "mspro_fck",
1666         .parent         = &func_96m_ck,
1667         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1668         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1669         .enable_bit     = 27,
1670         .recalc         = &omap2_followparent_recalc,
1671 };
1672
1673 static struct clk mmc_ick = {
1674         .name           = "mmc_ick",
1675         .parent         = &l4_ck,
1676         .flags          = CLOCK_IN_OMAP242X,
1677         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1678         .enable_bit     = 26,
1679         .recalc         = &omap2_followparent_recalc,
1680 };
1681
1682 static struct clk mmc_fck = {
1683         .name           = "mmc_fck",
1684         .parent         = &func_96m_ck,
1685         .flags          = CLOCK_IN_OMAP242X,
1686         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1687         .enable_bit     = 26,
1688         .recalc         = &omap2_followparent_recalc,
1689 };
1690
1691 static struct clk fac_ick = {
1692         .name           = "fac_ick",
1693         .parent         = &l4_ck,
1694         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1695         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1696         .enable_bit     = 25,
1697         .recalc         = &omap2_followparent_recalc,
1698 };
1699
1700 static struct clk fac_fck = {
1701         .name           = "fac_fck",
1702         .parent         = &func_12m_ck,
1703         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1704         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1705         .enable_bit     = 25,
1706         .recalc         = &omap2_followparent_recalc,
1707 };
1708
1709 static struct clk eac_ick = {
1710         .name           = "eac_ick",
1711         .parent         = &l4_ck,
1712         .flags          = CLOCK_IN_OMAP242X,
1713         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1714         .enable_bit     = 24,
1715         .recalc         = &omap2_followparent_recalc,
1716 };
1717
1718 static struct clk eac_fck = {
1719         .name           = "eac_fck",
1720         .parent         = &func_96m_ck,
1721         .flags          = CLOCK_IN_OMAP242X,
1722         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1723         .enable_bit     = 24,
1724         .recalc         = &omap2_followparent_recalc,
1725 };
1726
1727 static struct clk hdq_ick = {
1728         .name           = "hdq_ick",
1729         .parent         = &l4_ck,
1730         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1731         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1732         .enable_bit     = 23,
1733         .recalc         = &omap2_followparent_recalc,
1734 };
1735
1736 static struct clk hdq_fck = {
1737         .name           = "hdq_fck",
1738         .parent         = &func_12m_ck,
1739         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1740         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1741         .enable_bit     = 23,
1742         .recalc         = &omap2_followparent_recalc,
1743 };
1744
1745 static struct clk i2c2_ick = {
1746         .name           = "i2c_ick",
1747         .id             = 2,
1748         .parent         = &l4_ck,
1749         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1750         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1751         .enable_bit     = 20,
1752         .recalc         = &omap2_followparent_recalc,
1753 };
1754
1755 static struct clk i2c2_fck = {
1756         .name           = "i2c_fck",
1757         .id             = 2,
1758         .parent         = &func_12m_ck,
1759         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1760         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1761         .enable_bit     = 20,
1762         .recalc         = &omap2_followparent_recalc,
1763 };
1764
1765 static struct clk i2chs2_fck = {
1766         .name           = "i2chs_fck",
1767         .id             = 2,
1768         .parent         = &func_96m_ck,
1769         .flags          = CLOCK_IN_OMAP243X,
1770         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1771         .enable_bit     = 20,
1772         .recalc         = &omap2_followparent_recalc,
1773 };
1774
1775 static struct clk i2c1_ick = {
1776         .name           = "i2c_ick",
1777         .id             = 1,
1778         .parent         = &l4_ck,
1779         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1780         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1781         .enable_bit     = 19,
1782         .recalc         = &omap2_followparent_recalc,
1783 };
1784
1785 static struct clk i2c1_fck = {
1786         .name           = "i2c_fck",
1787         .id             = 1,
1788         .parent         = &func_12m_ck,
1789         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1790         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1791         .enable_bit     = 19,
1792         .recalc         = &omap2_followparent_recalc,
1793 };
1794
1795 static struct clk i2chs1_fck = {
1796         .name           = "i2chs_fck",
1797         .id             = 1,
1798         .parent         = &func_96m_ck,
1799         .flags          = CLOCK_IN_OMAP243X,
1800         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1801         .enable_bit     = 19,
1802         .recalc         = &omap2_followparent_recalc,
1803 };
1804
1805 static struct clk vlynq_ick = {
1806         .name           = "vlynq_ick",
1807         .parent         = &core_l3_ck,
1808         .flags          = CLOCK_IN_OMAP242X,
1809         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1810         .enable_bit     = 3,
1811         .recalc         = &omap2_followparent_recalc,
1812 };
1813
1814 static struct clk vlynq_fck = {
1815         .name           = "vlynq_fck",
1816         .parent         = &func_96m_ck,
1817         .flags          = CLOCK_IN_OMAP242X  | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
1818         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1819         .enable_bit     = 3,
1820         .src_offset     = 15,
1821         .recalc         = &omap2_followparent_recalc,
1822 };
1823
1824 static struct clk sdrc_ick = {
1825         .name           = "sdrc_ick",
1826         .parent         = &l4_ck,
1827         .flags          = CLOCK_IN_OMAP243X,
1828         .enable_reg     = (void __iomem *)&CM_ICLKEN3_CORE,
1829         .enable_bit     = 2,
1830         .recalc         = &omap2_followparent_recalc,
1831 };
1832
1833 static struct clk des_ick = {
1834         .name           = "des_ick",
1835         .parent         = &l4_ck,
1836         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1837         .enable_reg     = (void __iomem *)&CM_ICLKEN4_CORE,
1838         .enable_bit     = 0,
1839         .recalc         = &omap2_followparent_recalc,
1840 };
1841
1842 static struct clk sha_ick = {
1843         .name           = "sha_ick",
1844         .parent         = &l4_ck,
1845         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1846         .enable_reg     = (void __iomem *)&CM_ICLKEN4_CORE,
1847         .enable_bit     = 1,
1848         .recalc         = &omap2_followparent_recalc,
1849 };
1850
1851 static struct clk rng_ick = {
1852         .name           = "rng_ick",
1853         .parent         = &l4_ck,
1854         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1855         .enable_reg     = (void __iomem *)&CM_ICLKEN4_CORE,
1856         .enable_bit     = 2,
1857         .recalc         = &omap2_followparent_recalc,
1858 };
1859
1860 static struct clk aes_ick = {
1861         .name           = "aes_ick",
1862         .parent         = &l4_ck,
1863         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1864         .enable_reg     = (void __iomem *)&CM_ICLKEN4_CORE,
1865         .enable_bit     = 3,
1866         .recalc         = &omap2_followparent_recalc,
1867 };
1868
1869 static struct clk pka_ick = {
1870         .name           = "pka_ick",
1871         .parent         = &l4_ck,
1872         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1873         .enable_reg     = (void __iomem *)&CM_ICLKEN4_CORE,
1874         .enable_bit     = 4,
1875         .recalc         = &omap2_followparent_recalc,
1876 };
1877
1878 static struct clk usb_fck = {
1879         .name           = "usb_fck",
1880         .parent         = &func_48m_ck,
1881         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1882         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1883         .enable_bit     = 0,
1884         .recalc         = &omap2_followparent_recalc,
1885 };
1886
1887 static struct clk usbhs_ick = {
1888         .name           = "usbhs_ick",
1889         .parent         = &core_l3_ck,
1890         .flags          = CLOCK_IN_OMAP243X,
1891         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
1892         .enable_bit     = 6,
1893         .recalc         = &omap2_followparent_recalc,
1894 };
1895
1896 static struct clk mmchs1_ick = {
1897         .name           = "mmchs1_ick",
1898         .parent         = &l4_ck,
1899         .flags          = CLOCK_IN_OMAP243X,
1900         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
1901         .enable_bit     = 7,
1902         .recalc         = &omap2_followparent_recalc,
1903 };
1904
1905 static struct clk mmchs1_fck = {
1906         .name           = "mmchs1_fck",
1907         .parent         = &func_96m_ck,
1908         .flags          = CLOCK_IN_OMAP243X,
1909         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1910         .enable_bit     = 7,
1911         .recalc         = &omap2_followparent_recalc,
1912 };
1913
1914 static struct clk mmchs2_ick = {
1915         .name           = "mmchs2_ick",
1916         .parent         = &l4_ck,
1917         .flags          = CLOCK_IN_OMAP243X,
1918         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
1919         .enable_bit     = 8,
1920         .recalc         = &omap2_followparent_recalc,
1921 };
1922
1923 static struct clk mmchs2_fck = {
1924         .name           = "mmchs2_fck",
1925         .parent         = &func_96m_ck,
1926         .flags          = CLOCK_IN_OMAP243X,
1927         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1928         .enable_bit     = 8,
1929         .recalc         = &omap2_followparent_recalc,
1930 };
1931
1932 static struct clk gpio5_ick = {
1933         .name           = "gpio5_ick",
1934         .parent         = &l4_ck,
1935         .flags          = CLOCK_IN_OMAP243X,
1936         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
1937         .enable_bit     = 10,
1938         .recalc         = &omap2_followparent_recalc,
1939 };
1940
1941 static struct clk gpio5_fck = {
1942         .name           = "gpio5_fck",
1943         .parent         = &func_32k_ck,
1944         .flags          = CLOCK_IN_OMAP243X,
1945         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1946         .enable_bit     = 10,
1947         .recalc         = &omap2_followparent_recalc,
1948 };
1949
1950 static struct clk mdm_intc_ick = {
1951         .name           = "mdm_intc_ick",
1952         .parent         = &l4_ck,
1953         .flags          = CLOCK_IN_OMAP243X,
1954         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
1955         .enable_bit     = 11,
1956         .recalc         = &omap2_followparent_recalc,
1957 };
1958
1959 static struct clk mmchsdb1_fck = {
1960         .name           = "mmchsdb1_fck",
1961         .parent         = &func_32k_ck,
1962         .flags          = CLOCK_IN_OMAP243X,
1963         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1964         .enable_bit     = 16,
1965         .recalc         = &omap2_followparent_recalc,
1966 };
1967
1968 static struct clk mmchsdb2_fck = {
1969         .name           = "mmchsdb2_fck",
1970         .parent         = &func_32k_ck,
1971         .flags          = CLOCK_IN_OMAP243X,
1972         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1973         .enable_bit     = 17,
1974         .recalc         = &omap2_followparent_recalc,
1975 };
1976
1977 /*
1978  * This clock is a composite clock which does entire set changes then
1979  * forces a rebalance. It keys on the MPU speed, but it really could
1980  * be any key speed part of a set in the rate table.
1981  *
1982  * to really change a set, you need memory table sets which get changed
1983  * in sram, pre-notifiers & post notifiers, changing the top set, without
1984  * having low level display recalc's won't work... this is why dpm notifiers
1985  * work, isr's off, walk a list of clocks already _off_ and not messing with
1986  * the bus.
1987  *
1988  * This clock should have no parent. It embodies the entire upper level
1989  * active set. A parent will mess up some of the init also.
1990  */
1991 static struct clk virt_prcm_set = {
1992         .name           = "virt_prcm_set",
1993         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1994                                 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
1995         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
1996         .recalc         = &omap2_mpu_recalc,    /* sets are keyed on mpu rate */
1997         .set_rate       = &omap2_select_table_rate,
1998         .round_rate     = &omap2_round_to_table_rate,
1999 };
2000
2001 static struct clk *onchip_clks[] = {
2002         /* external root sources */
2003         &func_32k_ck,
2004         &osc_ck,
2005         &sys_ck,
2006         &alt_ck,
2007         /* internal analog sources */
2008         &dpll_ck,
2009         &apll96_ck,
2010         &apll54_ck,
2011         /* internal prcm root sources */
2012         &func_54m_ck,
2013         &core_ck,
2014         &sleep_ck,
2015         &func_96m_ck,
2016         &func_48m_ck,
2017         &func_12m_ck,
2018         &wdt1_osc_ck,
2019         &sys_clkout,
2020         &sys_clkout2,
2021         &emul_ck,
2022         /* mpu domain clocks */
2023         &mpu_ck,
2024         /* dsp domain clocks */
2025         &iva2_1_fck,            /* 2430 */
2026         &iva2_1_ick,
2027         &dsp_ick,               /* 2420 */
2028         &dsp_fck,
2029         &iva1_ifck,
2030         &iva1_mpu_int_ifck,
2031         /* GFX domain clocks */
2032         &gfx_3d_fck,
2033         &gfx_2d_fck,
2034         &gfx_ick,
2035         /* Modem domain clocks */
2036         &mdm_ick,
2037         &mdm_osc_ck,
2038         /* DSS domain clocks */
2039         &dss_ick,
2040         &dss1_fck,
2041         &dss2_fck,
2042         &dss_54m_fck,
2043         /* L3 domain clocks */
2044         &core_l3_ck,
2045         &ssi_ssr_sst_fck,
2046         &usb_l4_ick,
2047         /* L4 domain clocks */
2048         &l4_ck,                 /* used as both core_l4 and wu_l4 */
2049         &ssi_l4_ick,
2050         /* virtual meta-group clock */
2051         &virt_prcm_set,
2052         /* general l4 interface ck, multi-parent functional clk */
2053         &gpt1_ick,
2054         &gpt1_fck,
2055         &gpt2_ick,
2056         &gpt2_fck,
2057         &gpt3_ick,
2058         &gpt3_fck,
2059         &gpt4_ick,
2060         &gpt4_fck,
2061         &gpt5_ick,
2062         &gpt5_fck,
2063         &gpt6_ick,
2064         &gpt6_fck,
2065         &gpt7_ick,
2066         &gpt7_fck,
2067         &gpt8_ick,
2068         &gpt8_fck,
2069         &gpt9_ick,
2070         &gpt9_fck,
2071         &gpt10_ick,
2072         &gpt10_fck,
2073         &gpt11_ick,
2074         &gpt11_fck,
2075         &gpt12_ick,
2076         &gpt12_fck,
2077         &mcbsp1_ick,
2078         &mcbsp1_fck,
2079         &mcbsp2_ick,
2080         &mcbsp2_fck,
2081         &mcbsp3_ick,
2082         &mcbsp3_fck,
2083         &mcbsp4_ick,
2084         &mcbsp4_fck,
2085         &mcbsp5_ick,
2086         &mcbsp5_fck,
2087         &mcspi1_ick,
2088         &mcspi1_fck,
2089         &mcspi2_ick,
2090         &mcspi2_fck,
2091         &mcspi3_ick,
2092         &mcspi3_fck,
2093         &uart1_ick,
2094         &uart1_fck,
2095         &uart2_ick,
2096         &uart2_fck,
2097         &uart3_ick,
2098         &uart3_fck,
2099         &gpios_ick,
2100         &gpios_fck,
2101         &mpu_wdt_ick,
2102         &mpu_wdt_fck,
2103         &sync_32k_ick,
2104         &wdt1_ick,
2105         &omapctrl_ick,
2106         &icr_ick,
2107         &cam_fck,
2108         &cam_ick,
2109         &mailboxes_ick,
2110         &wdt4_ick,
2111         &wdt4_fck,
2112         &wdt3_ick,
2113         &wdt3_fck,
2114         &mspro_ick,
2115         &mspro_fck,
2116         &mmc_ick,
2117         &mmc_fck,
2118         &fac_ick,
2119         &fac_fck,
2120         &eac_ick,
2121         &eac_fck,
2122         &hdq_ick,
2123         &hdq_fck,
2124         &i2c1_ick,
2125         &i2c1_fck,
2126         &i2chs1_fck,
2127         &i2c2_ick,
2128         &i2c2_fck,
2129         &i2chs2_fck,
2130         &vlynq_ick,
2131         &vlynq_fck,
2132         &sdrc_ick,
2133         &des_ick,
2134         &sha_ick,
2135         &rng_ick,
2136         &aes_ick,
2137         &pka_ick,
2138         &usb_fck,
2139         &usbhs_ick,
2140         &mmchs1_ick,
2141         &mmchs1_fck,
2142         &mmchs2_ick,
2143         &mmchs2_fck,
2144         &gpio5_ick,
2145         &gpio5_fck,
2146         &mdm_intc_ick,
2147         &mmchsdb1_fck,
2148         &mmchsdb2_fck,
2149 };
2150
2151 #endif