arch/arm/mach-omap2/clock.c

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock.c
   3  *
   4  *  Copyright (C) 2005 Texas Instruments Inc.
   5  *  Richard Woodruff <r-woodruff2@ti.com>
   6  *  Created for OMAP2.
   7  *
   8  *  Cleaned up and modified to use omap shared clock framework by
   9  *  Tony Lindgren <tony@atomide.com>
  10  *
  11  *  Based on omap1 clock.c, Copyright (C) 2004 - 2005 Nokia corporation
  12  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/device.h>
  21 #include <linux/list.h>
  22 #include <linux/errno.h>
  23 #include <linux/delay.h>
  24 #include <linux/clk.h>
  25
  26 #include <asm/io.h>
  27
  28 #include <asm/arch/clock.h>
  29 #include <asm/arch/sram.h>
  30 #include <asm/div64.h>
  31
  32 #include "memory.h"
  33 #include "clock.h"
  34 #include "prm.h"
  35 #include "prm_regbits_24xx.h"
  36 #include "cm.h"
  37 #include "cm_regbits_24xx.h"
  38 #include "sdrc.h"
  39
  40 #undef DEBUG
  41
  42 /* SET_PERFORMANCE_LEVEL PARAMETERS */
  43 #define PRCM_HALF_SPEED         1
  44 #define PRCM_FULL_SPEED         2
  45
  46 //#define DOWN_VARIABLE_DPLL 1                  /* Experimental */
  47
  48 static struct prcm_config *curr_prcm_set;
  49 static u32 curr_perf_level = PRCM_FULL_SPEED;
  50 static struct clk *vclk;
  51 static struct clk *sclk;
  52 static u8 cpu_mask;
  53
  54 /*-------------------------------------------------------------------------
  55  * Omap2 specific clock functions
  56  *-------------------------------------------------------------------------*/
  57
  58 /* Recalculate SYST_CLK */
  59 static void omap2_sys_clk_recalc(struct clk * clk)
  60 {
  61         u32 div;
  62
  63         if (!cpu_is_omap34xx()) {
  64                 div = prm_read_reg(OMAP24XX_PRCM_CLKSRC_CTRL);
  65                 /* Test if ext clk divided by 1 or 2 */
  66                 div &= (0x3 << OMAP_SYSCLKDIV_SHIFT);
  67                 div >>= clk->rate_offset;
  68                 clk->rate = (clk->parent->rate / div);
  69         }
  70         propagate_rate(clk);
  71 }
  72
  73 static u32 omap2_get_dpll_rate(struct clk * tclk)
  74 {
  75         long long dpll_clk;
  76         int dpll_mult, dpll_div, amult;
  77         u32 dpll;
  78
  79         dpll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
  80
  81         dpll_mult = dpll & OMAP24XX_DPLL_MULT_MASK;
  82         dpll_mult >>= OMAP24XX_DPLL_MULT_SHIFT;         /* 10 bits */
  83         dpll_div = dpll & OMAP24XX_DPLL_DIV_MASK;
  84         dpll_div >>= OMAP24XX_DPLL_DIV_SHIFT;           /* 4 bits */
  85         dpll_clk = (long long)tclk->parent->rate * dpll_mult;
  86         do_div(dpll_clk, dpll_div + 1);
  87         amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
  88         amult &= OMAP24XX_CORE_CLK_SRC_MASK;
  89         dpll_clk *= amult;
  90
  91         return dpll_clk;
  92 }
  93
  94 static void omap2_followparent_recalc(struct clk *clk)
  95 {
  96         followparent_recalc(clk);
  97 }
  98
  99 static void omap2_propagate_rate(struct clk * clk)
 100 {
 101         if (!(clk->flags & RATE_FIXED))
 102                 clk->rate = clk->parent->rate;
 103
 104         propagate_rate(clk);
 105 }
 106
 107 static void omap2_set_osc_ck(int enable)
 108 {
 109         u32 pcc;
 110
 111         pcc = prm_read_reg(OMAP24XX_PRCM_CLKSRC_CTRL);
 112
 113         if (enable)
 114                 prm_write_reg(pcc & ~OMAP_AUTOEXTCLKMODE_MASK,
 115                               OMAP24XX_PRCM_CLKSRC_CTRL);
 116         else
 117                 prm_write_reg(pcc | OMAP_AUTOEXTCLKMODE_MASK,
 118                               OMAP24XX_PRCM_CLKSRC_CTRL);
 119 }
 120
 121 /* Enable an APLL if off */
 122 static void omap2_clk_fixed_enable(struct clk *clk)
 123 {
 124         u32 cval, i=0;
 125
 126         if (clk->enable_bit == PARENT_CONTROLS_CLOCK)   /* Parent will do it */
 127                 return;
 128
 129         cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 130
 131         if ((cval & (0x3 << clk->enable_bit)) == (0x3 << clk->enable_bit))
 132                 return;
 133
 134         cval &= ~(0x3 << clk->enable_bit);
 135         cval |= (0x3 << clk->enable_bit);
 136         cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 137
 138         if (clk == &apll96_ck)
 139                 cval = OMAP24XX_ST_96M_APLL;
 140         else if (clk == &apll54_ck)
 141                 cval = OMAP24XX_ST_54M_CLK;
 142
 143         /* Wait for lock */
 144         while (!(cm_read_mod_reg(PLL_MOD, CM_IDLEST) & cval)) {
 145                 ++i;
 146                 udelay(1);
 147                 if (i == 100000) {
 148                         printk(KERN_ERR "Clock %s didn't lock\n", clk->name);
 149                         break;
 150                 }
 151         }
 152 }
 153
 154 static void omap2_clk_wait_ready(struct clk *clk)
 155 {
 156         unsigned long reg, other_reg, st_reg;
 157         u32 bit;
 158         int i;
 159
 160         reg = (unsigned long) clk->enable_reg;
 161         if (reg == (unsigned long)OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1) ||
 162             reg == (unsigned long)OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2))
 163                 other_reg = (reg & ~0xf0) | 0x10; /* CM_ICLKEN* */
 164         else if (reg == (unsigned long)OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1) ||
 165                  reg == (unsigned long)OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2))
 166                 other_reg = (reg & ~0xf0) | 0x00; /* CM_FCLKEN* */
 167         else
 168                 return;
 169
 170         /* No check for DSS or cam clocks */
 171         if ((reg & 0x0f) == 0) {
 172                 if (clk->enable_bit <= 1 || clk->enable_bit == 31)
 173                         return;
 174         }
 175
 176         /* Check if both functional and interface clocks
 177          * are running. */
 178         bit = 1 << clk->enable_bit;
 179         if (!(cm_read_reg((void __iomem *)other_reg) & bit))
 180                 return;
 181         st_reg = (other_reg & ~0xf0) | 0x20; /* CM_IDLEST* */
 182         i = 0;
 183         while (!(cm_read_reg((void __iomem *)st_reg) & bit)) {
 184                 i++;
 185                 if (i == 100000) {
 186                         printk(KERN_ERR "Timeout enabling clock %s\n", clk->name);
 187                         break;
 188                 }
 189         }
 190         if (i)
 191                 pr_debug("Clock %s stable after %d loops\n", clk->name, i);
 192 }
 193
 194 /* Enables clock without considering parent dependencies or use count
 195  * REVISIT: Maybe change this to use clk->enable like on omap1?
 196  */
 197 static int _omap2_clk_enable(struct clk * clk)
 198 {
 199         u32 regval32;
 200
 201         if (clk->flags & ALWAYS_ENABLED)
 202                 return 0;
 203
 204         if (unlikely(clk == &osc_ck)) {
 205                 omap2_set_osc_ck(1);
 206                 return 0;
 207         }
 208
 209         if (unlikely(clk->enable_reg == 0)) {
 210                 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
 211                        clk->name);
 212                 return 0;
 213         }
 214
 215         if (clk->enable_reg == (void __iomem *)OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN)) {
 216                 omap2_clk_fixed_enable(clk);
 217                 return 0;
 218         }
 219
 220         regval32 = cm_read_reg(clk->enable_reg);
 221         regval32 |= (1 << clk->enable_bit);
 222         cm_write_reg(regval32, clk->enable_reg);
 223         wmb();
 224
 225         omap2_clk_wait_ready(clk);
 226
 227         return 0;
 228 }
 229
 230 /* Stop APLL */
 231 static void omap2_clk_fixed_disable(struct clk *clk)
 232 {
 233         u32 cval;
 234
 235         if (clk->enable_bit == PARENT_CONTROLS_CLOCK)
 236                 return;         /* let parent off do it */
 237
 238         cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 239         cval &= ~(0x3 << clk->enable_bit);
 240         cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 241 }
 242
 243 /* Disables clock without considering parent dependencies or use count */
 244 static void _omap2_clk_disable(struct clk *clk)
 245 {
 246         u32 regval32;
 247
 248         if (unlikely(clk == &osc_ck)) {
 249                 omap2_set_osc_ck(0);
 250                 return;
 251         }
 252
 253         if (clk->enable_reg == 0)
 254                 return;
 255
 256         if (clk->enable_reg == (void __iomem *)OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN)) {
 257                 omap2_clk_fixed_disable(clk);
 258                 return;
 259         }
 260
 261         regval32 = cm_read_reg(clk->enable_reg);
 262         regval32 &= ~(1 << clk->enable_bit);
 263         cm_write_reg(regval32, clk->enable_reg);
 264         wmb();
 265 }
 266
 267 static int omap2_clk_enable(struct clk *clk)
 268 {
 269         int ret = 0;
 270
 271         if (clk->usecount++ == 0) {
 272                 if (likely((u32)clk->parent))
 273                         ret = omap2_clk_enable(clk->parent);
 274
 275                 if (unlikely(ret != 0)) {
 276                         clk->usecount--;
 277                         return ret;
 278                 }
 279
 280                 ret = _omap2_clk_enable(clk);
 281
 282                 if (unlikely(ret != 0) && clk->parent) {
 283                         omap2_clk_disable(clk->parent);
 284                         clk->usecount--;
 285                 }
 286         }
 287
 288         return ret;
 289 }
 290
 291 static void omap2_clk_disable(struct clk *clk)
 292 {
 293         if (clk->usecount > 0 && !(--clk->usecount)) {
 294                 _omap2_clk_disable(clk);
 295                 if (likely((u32)clk->parent))
 296                         omap2_clk_disable(clk->parent);
 297         }
 298 }
 299
 300 /*
 301  * Uses the current prcm set to tell if a rate is valid.
 302  * You can go slower, but not faster within a given rate set.
 303  */
 304 static u32 omap2_dpll_round_rate(unsigned long target_rate)
 305 {
 306         u32 high, low, core_clk_src;
 307
 308         core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 309         core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
 310
 311         if (core_clk_src == 1) {        /* DPLL clockout */
 312                 high = curr_prcm_set->dpll_speed * 2;
 313                 low = curr_prcm_set->dpll_speed;
 314         } else {                                /* DPLL clockout x 2 */
 315                 high = curr_prcm_set->dpll_speed;
 316                 low = curr_prcm_set->dpll_speed / 2;
 317         }
 318
 319 #ifdef DOWN_VARIABLE_DPLL
 320         if (target_rate > high)
 321                 return high;
 322         else
 323                 return target_rate;
 324 #else
 325         if (target_rate > low)
 326                 return high;
 327         else
 328                 return low;
 329 #endif
 330
 331 }
 332
 333 /*
 334  * Used for clocks that are part of CLKSEL_xyz governed clocks.
 335  * REVISIT: Maybe change to use clk->enable() functions like on omap1?
 336  */
 337 static void omap2_clksel_recalc(struct clk * clk)
 338 {
 339         u32 fixed = 0, div = 0;
 340         u32 clksel1_core;
 341
 342         if (clk == &dpll_ck) {
 343                 clk->rate = omap2_get_dpll_rate(clk);
 344                 fixed = 1;
 345                 div = 0;
 346         }
 347
 348         if (clk == &iva1_mpu_int_ifck) {
 349                 div = 2;
 350                 fixed = 1;
 351         }
 352
 353         clksel1_core = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1);
 354
 355         if ((clk == &dss1_fck) &&
 356             (clksel1_core & OMAP24XX_CLKSEL_DSS1_MASK) == 0) {
 357                 clk->rate = sys_ck.rate;
 358                 return;
 359         }
 360
 361         if (!fixed) {
 362                 div = omap2_clksel_get_divisor(clk);
 363                 if (div == 0)
 364                         return;
 365         }
 366
 367         if (div != 0) {
 368                 if (unlikely(clk->rate == clk->parent->rate / div))
 369                         return;
 370                 clk->rate = clk->parent->rate / div;
 371         }
 372
 373         if (unlikely(clk->flags & RATE_PROPAGATES))
 374                 propagate_rate(clk);
 375 }
 376
 377 /*
 378  * Finds best divider value in an array based on the source and target
 379  * rates. The divider array must be sorted with smallest divider first.
 380  */
 381 static inline u32 omap2_divider_from_table(u32 size, u32 *div_array,
 382                                            u32 src_rate, u32 tgt_rate)
 383 {
 384         int i, test_rate;
 385
 386         if (div_array == NULL)
 387                 return ~1;
 388
 389         for (i=0; i < size; i++) {
 390                 test_rate = src_rate / *div_array;
 391                 if (test_rate <= tgt_rate)
 392                         return *div_array;
 393                 ++div_array;
 394         }
 395
 396         return ~0;      /* No acceptable divider */
 397 }
 398
 399 /*
 400  * Find divisor for the given clock and target rate.
 401  *
 402  * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
 403  * they are only settable as part of virtual_prcm set.
 404  */
 405 static u32 omap2_clksel_round_rate(struct clk *tclk, u32 target_rate,
 406         u32 *new_div)
 407 {
 408         u32 gfx_div[] = {2, 3, 4};
 409         u32 sysclkout_div[] = {1, 2, 4, 8, 16};
 410         u32 dss1_div[] = {1, 2, 3, 4, 5, 6, 8, 9, 12, 16};
 411         u32 vylnq_div[] = {1, 2, 3, 4, 6, 8, 9, 12, 16, 18};
 412         u32 best_div = ~0, asize = 0;
 413         u32 *div_array = NULL;
 414
 415         switch (tclk->flags & SRC_RATE_SEL_MASK) {
 416         case CM_GFX_SEL1:
 417                 asize = 3;
 418                 div_array = gfx_div;
 419                 break;
 420         case CM_PLL_SEL1:
 421                 return omap2_dpll_round_rate(target_rate);
 422         case CM_SYSCLKOUT_SEL1:
 423                 asize = 5;
 424                 div_array = sysclkout_div;
 425                 break;
 426         case CM_CORE_SEL1:
 427                 if(tclk == &dss1_fck){
 428                         if(tclk->parent == &core_ck){
 429                                 asize = 10;
 430                                 div_array = dss1_div;
 431                         } else {
 432                                 *new_div = 0; /* fixed clk */
 433                                 return(tclk->parent->rate);
 434                         }
 435                 } else if((tclk == &vlynq_fck) && cpu_is_omap2420()){
 436                         if(tclk->parent == &core_ck){
 437                                 asize = 10;
 438                                 div_array = vylnq_div;
 439                         } else {
 440                                 *new_div = 0; /* fixed clk */
 441                                 return(tclk->parent->rate);
 442                         }
 443                 }
 444                 break;
 445         }
 446
 447         best_div = omap2_divider_from_table(asize, div_array,
 448          tclk->parent->rate, target_rate);
 449         if (best_div == ~0){
 450                 *new_div = 1;
 451                 return best_div; /* signal error */
 452         }
 453
 454         *new_div = best_div;
 455         return (tclk->parent->rate / best_div);
 456 }
 457
 458 /* Given a clock and a rate apply a clock specific rounding function */
 459 static long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
 460 {
 461         u32 new_div = 0;
 462         int valid_rate;
 463
 464         if (clk->flags & RATE_FIXED)
 465                 return clk->rate;
 466
 467         if (clk->flags & RATE_CKCTL) {
 468                 valid_rate = omap2_clksel_round_rate(clk, rate, &new_div);
 469                 return valid_rate;
 470         }
 471
 472         if (clk->round_rate != 0)
 473                 return clk->round_rate(clk, rate);
 474
 475         return clk->rate;
 476 }
 477
 478 /*
 479  * Check the DLL lock state, and return tue if running in unlock mode.
 480  * This is needed to compensate for the shifted DLL value in unlock mode.
 481  */
 482 static u32 omap2_dll_force_needed(void)
 483 {
 484         /* dlla and dllb are a set */
 485         u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
 486
 487         if ((dll_state & (1 << 2)) == (1 << 2))
 488                 return 1;
 489         else
 490                 return 0;
 491 }
 492
 493 static u32 omap2_reprogram_sdrc(u32 level, u32 force)
 494 {
 495         u32 slow_dll_ctrl, fast_dll_ctrl, m_type;
 496         u32 prev = curr_perf_level, flags;
 497
 498         if ((curr_perf_level == level) && !force)
 499                 return prev;
 500
 501         m_type = omap2_memory_get_type();
 502         slow_dll_ctrl = omap2_memory_get_slow_dll_ctrl();
 503         fast_dll_ctrl = omap2_memory_get_fast_dll_ctrl();
 504
 505         if (level == PRCM_HALF_SPEED) {
 506                 local_irq_save(flags);
 507                 prm_write_reg(0xffff, OMAP24XX_PRCM_VOLTSETUP);
 508                 omap2_sram_reprogram_sdrc(PRCM_HALF_SPEED,
 509                                           slow_dll_ctrl, m_type);
 510                 curr_perf_level = PRCM_HALF_SPEED;
 511                 local_irq_restore(flags);
 512         }
 513         if (level == PRCM_FULL_SPEED) {
 514                 local_irq_save(flags);
 515                 prm_write_reg(0xffff, OMAP24XX_PRCM_VOLTSETUP);
 516                 omap2_sram_reprogram_sdrc(PRCM_FULL_SPEED,
 517                                           fast_dll_ctrl, m_type);
 518                 curr_perf_level = PRCM_FULL_SPEED;
 519                 local_irq_restore(flags);
 520         }
 521
 522         return prev;
 523 }
 524
 525 static int omap2_reprogram_dpll(struct clk * clk, unsigned long rate)
 526 {
 527         u32 flags, cur_rate, low, mult, div, valid_rate, done_rate;
 528         u32 bypass = 0;
 529         struct prcm_config tmpset;
 530         int ret = -EINVAL;
 531
 532         local_irq_save(flags);
 533         cur_rate = omap2_get_dpll_rate(&dpll_ck);
 534         mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 535         mult &= OMAP24XX_CORE_CLK_SRC_MASK;
 536
 537         if ((rate == (cur_rate / 2)) && (mult == 2)) {
 538                 omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1);
 539         } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
 540                 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
 541         } else if (rate != cur_rate) {
 542                 valid_rate = omap2_dpll_round_rate(rate);
 543                 if (valid_rate != rate)
 544                         goto dpll_exit;
 545
 546                 if (mult == 1)
 547                         low = curr_prcm_set->dpll_speed;
 548                 else
 549                         low = curr_prcm_set->dpll_speed / 2;
 550
 551                 /* REVISIT: This sets several reserved bits? */
 552                 tmpset.cm_clksel1_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
 553                 tmpset.cm_clksel1_pll &= ~(0x3FFF << 8);
 554                 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
 555                 tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 556                 tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
 557                 if (rate > low) {
 558                         tmpset.cm_clksel2_pll |= 0x2;
 559                         mult = ((rate / 2) / 1000000);
 560                         done_rate = PRCM_FULL_SPEED;
 561                 } else {
 562                         tmpset.cm_clksel2_pll |= 0x1;
 563                         mult = (rate / 1000000);
 564                         done_rate = PRCM_HALF_SPEED;
 565                 }
 566                 tmpset.cm_clksel1_pll |= (div << OMAP24XX_DPLL_DIV_SHIFT);
 567                 tmpset.cm_clksel1_pll |= (mult << OMAP24XX_DPLL_MULT_SHIFT);
 568
 569                 /* Worst case */
 570                 tmpset.base_sdrc_rfr = V24XX_SDRC_RFR_CTRL_BYPASS;
 571
 572                 if (rate == curr_prcm_set->xtal_speed)  /* If asking for 1-1 */
 573                         bypass = 1;
 574
 575                 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1); /* For init_mem */
 576
 577                 /* Force dll lock mode */
 578                 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
 579                                bypass);
 580
 581                 /* Errata: ret dll entry state */
 582                 omap2_init_memory_params(omap2_dll_force_needed());
 583                 omap2_reprogram_sdrc(done_rate, 0);
 584         }
 585         omap2_clksel_recalc(&dpll_ck);
 586         ret = 0;
 587
 588 dpll_exit:
 589         local_irq_restore(flags);
 590         return(ret);
 591 }
 592
 593 /* Just return the MPU speed */
 594 static void omap2_mpu_recalc(struct clk * clk)
 595 {
 596         clk->rate = curr_prcm_set->mpu_speed;
 597 }
 598
 599 /*
 600  * Look for a rate equal or less than the target rate given a configuration set.
 601  *
 602  * What's not entirely clear is "which" field represents the key field.
 603  * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
 604  * just uses the ARM rates.
 605  */
 606 static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate)
 607 {
 608         struct prcm_config * ptr;
 609         long highest_rate;
 610
 611         if (clk != &virt_prcm_set)
 612                 return -EINVAL;
 613
 614         highest_rate = -EINVAL;
 615
 616         for (ptr = rate_table; ptr->mpu_speed; ptr++) {
 617                 if (!(ptr->flags & cpu_mask))
 618                         continue;
 619                 if (ptr->xtal_speed != sys_ck.rate)
 620                         continue;
 621
 622                 highest_rate = ptr->mpu_speed;
 623
 624                 /* Can check only after xtal frequency check */
 625                 if (ptr->mpu_speed <= rate)
 626                         break;
 627         }
 628         return highest_rate;
 629 }
 630
 631 /*
 632  * omap2_convert_field_to_div() - turn field value into integer divider
 633  */
 634 static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val)
 635 {
 636         u32 i;
 637         u32 clkout_array[] = {1, 2, 4, 8, 16};
 638
 639         if ((div_sel & SRC_RATE_SEL_MASK) == CM_SYSCLKOUT_SEL1) {
 640                 for (i = 0; i < 5; i++) {
 641                         if (field_val == i)
 642                                 return clkout_array[i];
 643                 }
 644                 return ~0;
 645         } else
 646                 return field_val;
 647 }
 648
 649 /*
 650  * Returns the CLKSEL divider register value
 651  * REVISIT: This should be cleaned up to work nicely with void __iomem *
 652  */
 653 static u32 omap2_get_clksel(u32 *div_sel, u32 *field_mask,
 654                             struct clk *clk)
 655 {
 656         int ret = ~0;
 657         u32 reg_val, div_off;
 658         void __iomem *div_addr = 0;
 659         u32 mask = ~0;
 660
 661         div_off = clk->rate_offset;
 662
 663         switch ((*div_sel & SRC_RATE_SEL_MASK)) {
 664         case CM_MPU_SEL1:
 665                 div_addr = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL);
 666                 mask = OMAP24XX_CLKSEL_MPU_MASK;
 667                 break;
 668         case CM_DSP_SEL1:
 669                 div_addr = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL);
 670                 if (cpu_is_omap2420()) {
 671                         if (div_off == OMAP24XX_CLKSEL_DSP_SHIFT)
 672                                 mask = OMAP24XX_CLKSEL_DSP_MASK;
 673                         else if (div_off == OMAP2420_CLKSEL_IVA_SHIFT)
 674                                 mask = OMAP2420_CLKSEL_IVA_MASK;
 675                         else if (div_off == OMAP24XX_CLKSEL_DSP_IF_SHIFT)
 676                                 mask = OMAP24XX_CLKSEL_DSP_IF_MASK;
 677                 } else if (cpu_is_omap2430()) {
 678                         if (div_off == OMAP24XX_CLKSEL_DSP_SHIFT)
 679                                 mask = OMAP24XX_CLKSEL_DSP_MASK;
 680                         else if (div_off == OMAP24XX_CLKSEL_DSP_IF_SHIFT)
 681                                 mask = OMAP24XX_CLKSEL_DSP_IF_MASK;
 682                 }
 683         case CM_GFX_SEL1:
 684                 div_addr = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL);
 685                 if (div_off == OMAP_CLKSEL_GFX_SHIFT)
 686                         mask = OMAP_CLKSEL_GFX_MASK;
 687                 break;
 688         case CM_MODEM_SEL1:
 689                 div_addr = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL);
 690                 if (div_off == OMAP2430_CLKSEL_MDM_SHIFT)
 691                         mask = OMAP2430_CLKSEL_MDM_MASK;
 692                 break;
 693         case CM_SYSCLKOUT_SEL1:
 694                 div_addr = OMAP24XX_PRCM_CLKOUT_CTRL;
 695                 if (div_off == OMAP24XX_CLKOUT_DIV_SHIFT)
 696                         mask = OMAP24XX_CLKOUT_DIV_MASK;
 697                 else if (div_off == OMAP2420_CLKOUT2_DIV_SHIFT)
 698                         mask = OMAP2420_CLKOUT2_DIV_MASK;
 699                 break;
 700         case CM_CORE_SEL1:
 701                 div_addr = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1);
 702                 switch (div_off) {
 703                 case OMAP24XX_CLKSEL_L3_SHIFT:
 704                         mask = OMAP24XX_CLKSEL_L3_MASK;
 705                         break;
 706                 case OMAP24XX_CLKSEL_L4_SHIFT:
 707                         mask = OMAP24XX_CLKSEL_L4_MASK;
 708                         break;
 709                 case OMAP24XX_CLKSEL_DSS1_SHIFT:
 710                         mask = OMAP24XX_CLKSEL_DSS1_MASK;
 711                         break;
 712                 case OMAP24XX_CLKSEL_DSS2_SHIFT:
 713                         mask = OMAP24XX_CLKSEL_DSS2_MASK;
 714                         break;
 715                 case OMAP2420_CLKSEL_VLYNQ_SHIFT:
 716                         mask = OMAP2420_CLKSEL_VLYNQ_MASK;
 717                         break;
 718                 case OMAP24XX_CLKSEL_SSI_SHIFT:
 719                         mask = OMAP24XX_CLKSEL_SSI_MASK;
 720                         break;
 721                 case OMAP24XX_CLKSEL_USB_SHIFT:
 722                         mask = OMAP24XX_CLKSEL_USB_MASK;
 723                         break;
 724                 }
 725         }
 726
 727         *field_mask = (mask >> div_off);
 728
 729         if (unlikely(mask == ~0))
 730                 div_addr = 0;
 731
 732         *div_sel = (u32)div_addr;
 733
 734         if (unlikely(div_addr == 0))
 735                 return ret;
 736
 737         /* Isolate field */
 738         reg_val = cm_read_reg(div_addr) & mask;
 739
 740         /* Normalize back to divider value */
 741         reg_val >>= div_off;
 742
 743         return reg_val;
 744 }
 745
 746 /*
 747  * Return divider to be applied to parent clock.
 748  * Return 0 on error.
 749  */
 750 static u32 omap2_clksel_get_divisor(struct clk *clk)
 751 {
 752         int ret = 0;
 753         u32 div, div_sel, div_off, field_mask, field_val;
 754
 755         /* isolate control register */
 756         div_sel = (SRC_RATE_SEL_MASK & clk->flags);
 757
 758         div_off = clk->rate_offset;
 759         field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
 760         if (div_sel == 0)
 761                 return ret;
 762
 763         div_sel = (SRC_RATE_SEL_MASK & clk->flags);
 764         div = omap2_clksel_to_divisor(div_sel, field_val);
 765
 766         return div;
 767 }
 768
 769 /* Set the clock rate for a clock source */
 770 static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
 771
 772 {
 773         int ret = -EINVAL;
 774         void __iomem * reg;
 775         u32 div_sel, div_off, field_mask, field_val, reg_val, validrate;
 776         u32 new_div = 0;
 777
 778         if (!(clk->flags & CONFIG_PARTICIPANT) && (clk->flags & RATE_CKCTL)) {
 779                 if (clk == &dpll_ck)
 780                         return omap2_reprogram_dpll(clk, rate);
 781
 782                 /* Isolate control register */
 783                 div_sel = (SRC_RATE_SEL_MASK & clk->flags);
 784                 div_off = clk->rate_offset;
 785
 786                 validrate = omap2_clksel_round_rate(clk, rate, &new_div);
 787                 if (validrate != rate)
 788                         return(ret);
 789
 790                 field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
 791                 if (div_sel == 0)
 792                         return ret;
 793
 794                 if (clk->flags & CM_SYSCLKOUT_SEL1) {
 795                         switch (new_div) {
 796                         case 16:
 797                                 field_val = 4;
 798                                 break;
 799                         case 8:
 800                                 field_val = 3;
 801                                 break;
 802                         case 4:
 803                                 field_val = 2;
 804                                 break;
 805                         case 2:
 806                                 field_val = 1;
 807                                 break;
 808                         case 1:
 809                                 field_val = 0;
 810                                 break;
 811                         }
 812                 } else
 813                         field_val = new_div;
 814
 815                 reg = (void __iomem *)div_sel;
 816
 817                 reg_val = cm_read_reg(reg);
 818                 reg_val &= ~(field_mask << div_off);
 819                 reg_val |= (field_val << div_off);
 820                 cm_write_reg(reg_val, reg);
 821                 wmb();
 822                 clk->rate = clk->parent->rate / new_div;
 823
 824                 if (clk->flags & DELAYED_APP) {
 825                         prm_write_reg(OMAP24XX_VALID_CONFIG,
 826                                       OMAP24XX_PRCM_CLKCFG_CTRL);
 827                         wmb();
 828                 }
 829                 ret = 0;
 830         } else if (clk->set_rate != 0)
 831                 ret = clk->set_rate(clk, rate);
 832
 833         if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
 834                 propagate_rate(clk);
 835
 836         return ret;
 837 }
 838
 839 /* Converts encoded control register address into a full address */
 840 static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset,
 841                                struct clk *src_clk, u32 *field_mask)
 842 {
 843         u32 val = ~0, mask = 0;
 844         void __iomem *src_reg_addr = 0;
 845
 846         /* Find target control register.*/
 847         switch ((*type_to_addr & SRC_RATE_SEL_MASK)) {
 848         case CM_CORE_SEL1:
 849                 src_reg_addr = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1);
 850                 if (reg_offset == OMAP24XX_CLKSEL_DSS2_SHIFT) {
 851                         mask = OMAP24XX_CLKSEL_DSS2_MASK;
 852                         mask >>= OMAP24XX_CLKSEL_DSS2_SHIFT;
 853                         if (src_clk == &sys_ck)
 854                                 val = 0;
 855                         if (src_clk == &func_48m_ck)
 856                                 val = 1;
 857                 } else if (reg_offset == OMAP24XX_CLKSEL_DSS1_SHIFT) {
 858                         mask = OMAP24XX_CLKSEL_DSS1_MASK;
 859                         mask >>= OMAP24XX_CLKSEL_DSS1_SHIFT;
 860                         if (src_clk == &sys_ck)
 861                                 val = 0;
 862                         else if (src_clk == &core_ck)   /* divided clock */
 863                                 val = 0x10;             /* rate needs fixing */
 864                 } else if ((reg_offset == OMAP2420_CLKSEL_VLYNQ_SHIFT) &&
 865                            cpu_is_omap2420()){
 866                         mask = OMAP2420_CLKSEL_VLYNQ_MASK;
 867                         mask >>= OMAP2420_CLKSEL_VLYNQ_SHIFT;
 868                         if(src_clk == &func_96m_ck)
 869                                 val = 0;
 870                         else if (src_clk == &core_ck)
 871                                 val = 0x10;
 872                 }
 873                 break;
 874         case CM_CORE_SEL2:
 875                 src_reg_addr = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2);
 876                 mask = 0x3;
 877                 if (src_clk == &func_32k_ck)
 878                         val = 0x0;
 879                 if (src_clk == &sys_ck)
 880                         val = 0x1;
 881                 if (src_clk == &alt_ck)
 882                         val = 0x2;
 883                 break;
 884         case CM_WKUP_SEL1:
 885                 src_reg_addr = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL);
 886                 mask = 0x3;
 887                 if (src_clk == &func_32k_ck)
 888                         val = 0x0;
 889                 if (src_clk == &sys_ck)
 890                         val = 0x1;
 891                 if (src_clk == &alt_ck)
 892                         val = 0x2;
 893                 break;
 894         case CM_PLL_SEL1:
 895                 src_reg_addr = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1);
 896                 mask = 0x1;
 897                 if (reg_offset == 0x3) {
 898                         if (src_clk == &apll96_ck)
 899                                 val = 0;
 900                         if (src_clk == &alt_ck)
 901                                 val = 1;
 902                 }
 903                 else if (reg_offset == 0x5) {
 904                         if (src_clk == &apll54_ck)
 905                                 val = 0;
 906                         if (src_clk == &alt_ck)
 907                                 val = 1;
 908                 }
 909                 break;
 910         case CM_PLL_SEL2:
 911                 src_reg_addr = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2);
 912                 mask = 0x3;
 913                 if (src_clk == &func_32k_ck)
 914                         val = 0x0;
 915                 if (src_clk == &dpll_ck)
 916                         val = 0x2;
 917                 break;
 918         case CM_SYSCLKOUT_SEL1:
 919                 src_reg_addr = OMAP24XX_PRCM_CLKOUT_CTRL;
 920                 mask = 0x3;
 921                 if (src_clk == &dpll_ck)
 922                         val = 0;
 923                 if (src_clk == &sys_ck)
 924                         val = 1;
 925                 if (src_clk == &func_96m_ck)
 926                         val = 2;
 927                 if (src_clk == &func_54m_ck)
 928                         val = 3;
 929                 break;
 930         }
 931
 932         if (val == ~0)                  /* Catch errors in offset */
 933                 *type_to_addr = 0;
 934         else
 935                 *type_to_addr = (u32)src_reg_addr;
 936         *field_mask = mask;
 937
 938         return val;
 939 }
 940
 941 static int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
 942 {
 943         void __iomem * reg;
 944         u32 src_sel, src_off, field_val, field_mask, reg_val, rate;
 945         int ret = -EINVAL;
 946
 947         if (unlikely(clk->flags & CONFIG_PARTICIPANT))
 948                 return ret;
 949
 950         if (clk->flags & SRC_SEL_MASK) {        /* On-chip SEL collection */
 951                 src_sel = (SRC_RATE_SEL_MASK & clk->flags);
 952                 src_off = clk->src_offset;
 953
 954                 if (src_sel == 0)
 955                         goto set_parent_error;
 956
 957                 field_val = omap2_get_src_field(&src_sel, src_off, new_parent,
 958                                                 &field_mask);
 959
 960                 reg = (void __iomem *)src_sel;
 961
 962                 if (clk->usecount > 0)
 963                         _omap2_clk_disable(clk);
 964
 965                 /* Set new source value (previous dividers if any in effect) */
 966                 reg_val = __raw_readl(reg) & ~(field_mask << src_off);
 967                 reg_val |= (field_val << src_off);
 968                 __raw_writel(reg_val, reg);
 969                 wmb();
 970
 971                 if (clk->flags & DELAYED_APP) {
 972                         prm_write_reg(OMAP24XX_VALID_CONFIG,
 973                                       OMAP24XX_PRCM_CLKCFG_CTRL);
 974                         wmb();
 975                 }
 976                 if (clk->usecount > 0)
 977                         _omap2_clk_enable(clk);
 978
 979                 clk->parent = new_parent;
 980
 981                 /* SRC_RATE_SEL_MASK clocks follow their parents rates.*/
 982                 if ((new_parent == &core_ck) && (clk == &dss1_fck))
 983                         clk->rate = new_parent->rate / 0x10;
 984                 else
 985                         clk->rate = new_parent->rate;
 986
 987                 if (unlikely(clk->flags & RATE_PROPAGATES))
 988                         propagate_rate(clk);
 989
 990                 return 0;
 991         } else {
 992                 clk->parent = new_parent;
 993                 rate = new_parent->rate;
 994                 omap2_clk_set_rate(clk, rate);
 995                 ret = 0;
 996         }
 997
 998  set_parent_error:
 999         return ret;
1000 }
1001
1002 /* Sets basic clocks based on the specified rate */
1003 static int omap2_select_table_rate(struct clk * clk, unsigned long rate)
1004 {
1005         u32 flags, cur_rate, done_rate, bypass = 0, tmp;
1006         struct prcm_config *prcm;
1007         unsigned long found_speed = 0;
1008
1009         if (clk != &virt_prcm_set)
1010                 return -EINVAL;
1011
1012         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
1013                 if (!(prcm->flags & cpu_mask))
1014                         continue;
1015
1016                 if (prcm->xtal_speed != sys_ck.rate)
1017                         continue;
1018
1019                 if (prcm->mpu_speed <= rate) {
1020                         found_speed = prcm->mpu_speed;
1021                         break;
1022                 }
1023         }
1024
1025         if (!found_speed) {
1026                 printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
1027          rate / 1000000);
1028                 return -EINVAL;
1029         }
1030
1031         curr_prcm_set = prcm;
1032         cur_rate = omap2_get_dpll_rate(&dpll_ck);
1033
1034         if (prcm->dpll_speed == cur_rate / 2) {
1035                 omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1);
1036         } else if (prcm->dpll_speed == cur_rate * 2) {
1037                 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
1038         } else if (prcm->dpll_speed != cur_rate) {
1039                 local_irq_save(flags);
1040
1041                 if (prcm->dpll_speed == prcm->xtal_speed)
1042                         bypass = 1;
1043
1044                 if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) == 2)
1045                         done_rate = PRCM_FULL_SPEED;
1046                 else
1047                         done_rate = PRCM_HALF_SPEED;
1048
1049                 /* MPU divider */
1050                 cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
1051
1052                 /* dsp + iva1 div(2420), iva2.1(2430) */
1053                 cm_write_mod_reg(prcm->cm_clksel_dsp,
1054                                  OMAP24XX_DSP_MOD, CM_CLKSEL);
1055
1056                 cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
1057
1058                 /* Major subsystem dividers */
1059                 tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & 0x2000;
1060                 cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1);
1061                 if (cpu_is_omap2430())
1062                         cm_write_mod_reg(prcm->cm_clksel_mdm,
1063                                          OMAP2430_MDM_MOD, CM_CLKSEL);
1064
1065                 /* x2 to enter init_mem */
1066                 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
1067
1068                 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
1069                                bypass);
1070
1071                 omap2_init_memory_params(omap2_dll_force_needed());
1072                 omap2_reprogram_sdrc(done_rate, 0);
1073
1074                 local_irq_restore(flags);
1075         }
1076         omap2_clksel_recalc(&dpll_ck);
1077
1078         return 0;
1079 }
1080
1081 /*-------------------------------------------------------------------------
1082  * Omap2 clock reset and init functions
1083  *-------------------------------------------------------------------------*/
1084
1085 #ifdef CONFIG_OMAP_RESET_CLOCKS
1086 static void __init omap2_clk_disable_unused(struct clk *clk)
1087 {
1088         u32 regval32;
1089
1090         regval32 = cm_read_reg(clk->enable_reg);
1091         if ((regval32 & (1 << clk->enable_bit)) == 0)
1092                 return;
1093
1094         printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
1095         _omap2_clk_disable(clk);
1096 }
1097 #else
1098 #define omap2_clk_disable_unused        NULL
1099 #endif
1100
1101 static struct clk_functions omap2_clk_functions = {
1102         .clk_enable             = omap2_clk_enable,
1103         .clk_disable            = omap2_clk_disable,
1104         .clk_round_rate         = omap2_clk_round_rate,
1105         .clk_set_rate           = omap2_clk_set_rate,
1106         .clk_set_parent         = omap2_clk_set_parent,
1107         .clk_disable_unused     = omap2_clk_disable_unused,
1108 };
1109
1110 static void __init omap2_get_crystal_rate(struct clk *osc, struct clk *sys)
1111 {
1112         u32 div, aplls, sclk = 13000000;
1113
1114         aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
1115         aplls &= OMAP24XX_APLLS_CLKIN_MASK;
1116         aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;   /* Isolate field, 0,2,3 */
1117
1118         if (aplls == 0)
1119                 sclk = 19200000;
1120         else if (aplls == 2)
1121                 sclk = 13000000;
1122         else if (aplls == 3)
1123                 sclk = 12000000;
1124
1125         div = prm_read_reg(OMAP24XX_PRCM_CLKSRC_CTRL);
1126         div &= OMAP_SYSCLKDIV_MASK;
1127         div >>= sys->rate_offset;
1128
1129         osc->rate = sclk;
1130         sys->rate = osc->rate / div;
1131 }
1132
1133 /*
1134  * Set clocks for bypass mode for reboot to work.
1135  */
1136 void omap2_clk_prepare_for_reboot(void)
1137 {
1138         u32 rate;
1139
1140         if (vclk == NULL || sclk == NULL)
1141                 return;
1142
1143         rate = clk_get_rate(sclk);
1144         clk_set_rate(vclk, rate);
1145 }
1146
1147 /*
1148  * Switch the MPU rate if specified on cmdline.
1149  * We cannot do this early until cmdline is parsed.
1150  */
1151 static int __init omap2_clk_arch_init(void)
1152 {
1153         if (!mpurate)
1154                 return -EINVAL;
1155
1156         if (omap2_select_table_rate(&virt_prcm_set, mpurate))
1157                 printk(KERN_ERR "Could not find matching MPU rate\n");
1158
1159         propagate_rate(&osc_ck);                /* update main root fast */
1160         propagate_rate(&func_32k_ck);           /* update main root slow */
1161
1162         printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
1163                "%ld.%01ld/%ld/%ld MHz\n",
1164                (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
1165                (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
1166
1167         return 0;
1168 }
1169 arch_initcall(omap2_clk_arch_init);
1170
1171 int __init omap2_clk_init(void)
1172 {
1173         struct prcm_config *prcm;
1174         struct clk ** clkp;
1175         u32 clkrate;
1176
1177         clk_init(&omap2_clk_functions);
1178         omap2_get_crystal_rate(&osc_ck, &sys_ck);
1179
1180         for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
1181              clkp++) {
1182
1183                 if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
1184                         clk_register(*clkp);
1185                         continue;
1186                 }
1187
1188                 if ((*clkp)->flags & CLOCK_IN_OMAP243X && (cpu_is_omap2430() || cpu_is_omap34xx())) {
1189                         clk_register(*clkp);
1190                         continue;
1191                 }
1192         }
1193
1194         if (cpu_is_omap242x())
1195                 cpu_mask = RATE_IN_242X;
1196         else if (cpu_is_omap2430())
1197                 cpu_mask = RATE_IN_243X;
1198
1199         /* Check the MPU rate set by bootloader */
1200         clkrate = omap2_get_dpll_rate(&dpll_ck);
1201         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
1202                 if (!(prcm->flags & cpu_mask))
1203                         continue;
1204                 if (prcm->xtal_speed != sys_ck.rate)
1205                         continue;
1206                 if (prcm->dpll_speed <= clkrate)
1207                          break;
1208         }
1209         curr_prcm_set = prcm;
1210
1211         propagate_rate(&osc_ck);                /* update main root fast */
1212         propagate_rate(&func_32k_ck);           /* update main root slow */
1213
1214         printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
1215                "%ld.%01ld/%ld/%ld MHz\n",
1216                (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
1217                (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
1218
1219         /*
1220          * Only enable those clocks we will need, let the drivers
1221          * enable other clocks as necessary
1222          */
1223         clk_enable(&sync_32k_ick);
1224         clk_enable(&omapctrl_ick);
1225
1226         /* Force the APLLs always active. The clocks are idled
1227          * automatically by hardware. */
1228         clk_enable(&apll96_ck);
1229         clk_enable(&apll54_ck);
1230
1231         if (cpu_is_omap2430())
1232                 clk_enable(&sdrc_ick);
1233
1234         /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
1235         vclk = clk_get(NULL, "virt_prcm_set");
1236         sclk = clk_get(NULL, "sys_ck");
1237
1238         return 0;
1239 }