arch/arm/mach-omap2/clock.c

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock.c
   3  *
   4  *  Copyright (C) 2005 Texas Instruments Inc.
   5  *  Richard Woodruff <r-woodruff2@ti.com>
   6  *  Created for OMAP2.
   7  *
   8  *  Cleaned up and modified to use omap shared clock framework by
   9  *  Tony Lindgren <tony@atomide.com>
  10  *
  11  *  Based on omap1 clock.c, Copyright (C) 2004 - 2005 Nokia corporation
  12  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/device.h>
  21 #include <linux/list.h>
  22 #include <linux/errno.h>
  23 #include <linux/delay.h>
  24 #include <linux/clk.h>
  25
  26 #include <asm/io.h>
  27
  28 #include <asm/arch/clock.h>
  29 #include <asm/arch/sram.h>
  30 #include <asm/div64.h>
  31
  32 #include "memory.h"
  33 #include "clock.h"
  34 #include "prm.h"
  35 #include "prm_regbits_24xx.h"
  36 #include "cm.h"
  37 #include "cm_regbits_24xx.h"
  38
  39 #undef DEBUG
  40
  41 /* CM_CLKSEL1_CORE.CLKSEL_VLYNQ options (2420) */
  42 #define CLKSEL_VLYNQ_96MHZ              0
  43 #define CLKSEL_VLYNQ_CORECLK_16         0x10
  44
  45 //#define DOWN_VARIABLE_DPLL 1                  /* Experimental */
  46
  47 static struct prcm_config *curr_prcm_set;
  48 static u32 curr_perf_level = PRCM_FULL_SPEED;
  49 static struct clk *vclk;
  50 static struct clk *sclk;
  51 static u8 cpu_mask;
  52
  53 /*-------------------------------------------------------------------------
  54  * Omap2 specific clock functions
  55  *-------------------------------------------------------------------------*/
  56
  57 /* Recalculate SYST_CLK */
  58 static void omap2_sys_clk_recalc(struct clk * clk)
  59 {
  60         u32 div;
  61
  62         if (!cpu_is_omap34xx()) {
  63                 div = prm_read_reg(OMAP24XX_PRCM_CLKSRC_CTRL);
  64                 /* Test if ext clk divided by 1 or 2 */
  65                 div &= (0x3 << OMAP_SYSCLKDIV_SHIFT);
  66                 div >>= clk->rate_offset;
  67                 clk->rate = (clk->parent->rate / div);
  68         }
  69         propagate_rate(clk);
  70 }
  71
  72 static u32 omap2_get_dpll_rate(struct clk * tclk)
  73 {
  74         long long dpll_clk;
  75         int dpll_mult, dpll_div, amult;
  76         u32 dpll;
  77
  78         dpll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
  79
  80         dpll_mult = dpll & OMAP24XX_DPLL_MULT_MASK;
  81         dpll_mult >>= OMAP24XX_DPLL_MULT_SHIFT;         /* 10 bits */
  82         dpll_div = dpll & OMAP24XX_DPLL_DIV_MASK;
  83         dpll_div >>= OMAP24XX_DPLL_DIV_SHIFT;           /* 4 bits */
  84         dpll_clk = (long long)tclk->parent->rate * dpll_mult;
  85         do_div(dpll_clk, dpll_div + 1);
  86         amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
  87         amult &= OMAP24XX_CORE_CLK_SRC_MASK;
  88         dpll_clk *= amult;
  89
  90         return dpll_clk;
  91 }
  92
  93 static void omap2_followparent_recalc(struct clk *clk)
  94 {
  95         followparent_recalc(clk);
  96 }
  97
  98 static void omap2_propagate_rate(struct clk * clk)
  99 {
 100         if (!(clk->flags & RATE_FIXED))
 101                 clk->rate = clk->parent->rate;
 102
 103         propagate_rate(clk);
 104 }
 105
 106 static void omap2_set_osc_ck(int enable)
 107 {
 108         u32 pcc;
 109
 110         pcc = prm_read_reg(OMAP24XX_PRCM_CLKSRC_CTRL);
 111
 112         if (enable)
 113                 prm_write_reg(pcc & ~OMAP_AUTOEXTCLKMODE_MASK,
 114                               OMAP24XX_PRCM_CLKSRC_CTRL);
 115         else
 116                 prm_write_reg(pcc | OMAP_AUTOEXTCLKMODE_MASK,
 117                               OMAP24XX_PRCM_CLKSRC_CTRL);
 118 }
 119
 120 /* Enable an APLL if off */
 121 static void omap2_clk_fixed_enable(struct clk *clk)
 122 {
 123         u32 cval, i=0;
 124
 125         cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 126
 127         if ((cval & (0x3 << clk->enable_bit)) == (0x3 << clk->enable_bit))
 128                 return;
 129
 130         cval &= ~(0x3 << clk->enable_bit);
 131         cval |= (0x3 << clk->enable_bit);
 132         cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 133
 134         if (clk == &apll96_ck)
 135                 cval = OMAP24XX_ST_96M_APLL;
 136         else if (clk == &apll54_ck)
 137                 cval = OMAP24XX_ST_54M_CLK;
 138
 139         /* Wait for lock */
 140         while (!(cm_read_mod_reg(PLL_MOD, CM_IDLEST) & cval)) {
 141                 ++i;
 142                 udelay(1);
 143                 if (i == 100000) {
 144                         printk(KERN_ERR "Clock %s didn't lock\n", clk->name);
 145                         break;
 146                 }
 147         }
 148 }
 149
 150 static void omap2_clk_wait_ready(struct clk *clk)
 151 {
 152         unsigned long reg, other_reg, st_reg;
 153         u32 bit;
 154         int i;
 155
 156         reg = (unsigned long) clk->enable_reg;
 157         if (reg == (unsigned long)OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1) ||
 158             reg == (unsigned long)OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2))
 159                 other_reg = (reg & ~0xf0) | 0x10; /* CM_ICLKEN* */
 160         else if (reg == (unsigned long)OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1) ||
 161                  reg == (unsigned long)OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2))
 162                 other_reg = (reg & ~0xf0) | 0x00; /* CM_FCLKEN* */
 163         else
 164                 return;
 165
 166         /* No check for DSS or cam clocks */
 167         if ((reg & 0x0f) == 0) {
 168                 if (clk->enable_bit <= 1 || clk->enable_bit == 31)
 169                         return;
 170         }
 171
 172         /* Check if both functional and interface clocks
 173          * are running. */
 174         bit = 1 << clk->enable_bit;
 175         if (!(cm_read_reg((void __iomem *)other_reg) & bit))
 176                 return;
 177         st_reg = (other_reg & ~0xf0) | 0x20; /* CM_IDLEST* */
 178         i = 0;
 179         while (!(cm_read_reg((void __iomem *)st_reg) & bit)) {
 180                 i++;
 181                 if (i == 100000) {
 182                         printk(KERN_ERR "Timeout enabling clock %s\n", clk->name);
 183                         break;
 184                 }
 185         }
 186         if (i)
 187                 pr_debug("Clock %s stable after %d loops\n", clk->name, i);
 188 }
 189
 190 /* Enables clock without considering parent dependencies or use count
 191  * REVISIT: Maybe change this to use clk->enable like on omap1?
 192  */
 193 static int _omap2_clk_enable(struct clk * clk)
 194 {
 195         u32 regval32;
 196
 197         if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
 198                 return 0;
 199
 200         if (unlikely(clk == &osc_ck)) {
 201                 omap2_set_osc_ck(1);
 202                 return 0;
 203         }
 204
 205         if (unlikely(clk->enable_reg == 0)) {
 206                 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
 207                        clk->name);
 208                 return 0;
 209         }
 210
 211         if (clk->enable_reg == OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN)) {
 212                 omap2_clk_fixed_enable(clk);
 213                 return 0;
 214         }
 215
 216         regval32 = cm_read_reg(clk->enable_reg);
 217         regval32 |= (1 << clk->enable_bit);
 218         cm_write_reg(regval32, clk->enable_reg);
 219         wmb();
 220
 221         omap2_clk_wait_ready(clk);
 222
 223         return 0;
 224 }
 225
 226 /* Stop APLL */
 227 static void omap2_clk_fixed_disable(struct clk *clk)
 228 {
 229         u32 cval;
 230
 231         cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 232         cval &= ~(0x3 << clk->enable_bit);
 233         cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 234 }
 235
 236 /* Disables clock without considering parent dependencies or use count */
 237 static void _omap2_clk_disable(struct clk *clk)
 238 {
 239         u32 regval32;
 240
 241         if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
 242                 return;
 243
 244         if (unlikely(clk == &osc_ck)) {
 245                 omap2_set_osc_ck(0);
 246                 return;
 247         }
 248
 249         if (clk->enable_reg == 0)
 250                 return;
 251
 252         if (clk->enable_reg == OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN)) {
 253                 omap2_clk_fixed_disable(clk);
 254                 return;
 255         }
 256
 257         regval32 = cm_read_reg(clk->enable_reg);
 258         regval32 &= ~(1 << clk->enable_bit);
 259         cm_write_reg(regval32, clk->enable_reg);
 260         wmb();
 261 }
 262
 263 static int omap2_clk_enable(struct clk *clk)
 264 {
 265         int ret = 0;
 266
 267         if (clk->usecount++ == 0) {
 268                 if (likely((u32)clk->parent))
 269                         ret = omap2_clk_enable(clk->parent);
 270
 271                 if (unlikely(ret != 0)) {
 272                         clk->usecount--;
 273                         return ret;
 274                 }
 275
 276                 ret = _omap2_clk_enable(clk);
 277
 278                 if (unlikely(ret != 0) && clk->parent) {
 279                         omap2_clk_disable(clk->parent);
 280                         clk->usecount--;
 281                 }
 282         }
 283
 284         return ret;
 285 }
 286
 287 static void omap2_clk_disable(struct clk *clk)
 288 {
 289         if (clk->usecount > 0 && !(--clk->usecount)) {
 290                 _omap2_clk_disable(clk);
 291                 if (likely((u32)clk->parent))
 292                         omap2_clk_disable(clk->parent);
 293         }
 294 }
 295
 296 /*
 297  * Uses the current prcm set to tell if a rate is valid.
 298  * You can go slower, but not faster within a given rate set.
 299  */
 300 static u32 omap2_dpll_round_rate(unsigned long target_rate)
 301 {
 302         u32 high, low, core_clk_src;
 303
 304         core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 305         core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
 306
 307         if (core_clk_src == 1) {        /* DPLL clockout */
 308                 high = curr_prcm_set->dpll_speed * 2;
 309                 low = curr_prcm_set->dpll_speed;
 310         } else {                                /* DPLL clockout x 2 */
 311                 high = curr_prcm_set->dpll_speed;
 312                 low = curr_prcm_set->dpll_speed / 2;
 313         }
 314
 315 #ifdef DOWN_VARIABLE_DPLL
 316         if (target_rate > high)
 317                 return high;
 318         else
 319                 return target_rate;
 320 #else
 321         if (target_rate > low)
 322                 return high;
 323         else
 324                 return low;
 325 #endif
 326
 327 }
 328
 329 /*
 330  * Used for clocks that are part of CLKSEL_xyz governed clocks.
 331  * REVISIT: Maybe change to use clk->enable() functions like on omap1?
 332  */
 333 static void omap2_clksel_recalc(struct clk * clk)
 334 {
 335         u32 fixed = 0, div = 0;
 336         u32 clksel1_core;
 337
 338         if (clk == &dpll_ck) {
 339                 clk->rate = omap2_get_dpll_rate(clk);
 340                 fixed = 1;
 341                 div = 0;
 342         }
 343
 344         if (clk == &iva1_mpu_int_ifck) {
 345                 div = 2;
 346                 fixed = 1;
 347         }
 348
 349         clksel1_core = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1);
 350
 351         if ((clk == &dss1_fck) &&
 352             (clksel1_core & OMAP24XX_CLKSEL_DSS1_MASK) == 0) {
 353                 clk->rate = sys_ck.rate;
 354                 return;
 355         }
 356
 357         if ((clk == &vlynq_fck) && cpu_is_omap2420() &&
 358             (clksel1_core & OMAP2420_CLKSEL_VLYNQ_MASK) == CLKSEL_VLYNQ_96MHZ) {
 359                 clk->rate = func_96m_ck.rate;
 360                 return;
 361         }
 362
 363         if (!fixed) {
 364                 div = omap2_clksel_get_divisor(clk);
 365                 if (div == 0)
 366                         return;
 367         }
 368
 369         if (div != 0) {
 370                 if (unlikely(clk->rate == clk->parent->rate / div))
 371                         return;
 372                 clk->rate = clk->parent->rate / div;
 373         }
 374
 375         if (unlikely(clk->flags & RATE_PROPAGATES))
 376                 propagate_rate(clk);
 377 }
 378
 379 /*
 380  * Finds best divider value in an array based on the source and target
 381  * rates. The divider array must be sorted with smallest divider first.
 382  */
 383 static inline u32 omap2_divider_from_table(u32 size, u32 *div_array,
 384                                            u32 src_rate, u32 tgt_rate)
 385 {
 386         int i, test_rate;
 387
 388         if (div_array == NULL)
 389                 return ~1;
 390
 391         for (i = 0; i < size; i++) {
 392                 test_rate = src_rate / *div_array;
 393                 if (test_rate <= tgt_rate)
 394                         return *div_array;
 395                 ++div_array;
 396         }
 397
 398         return ~0;      /* No acceptable divider */
 399 }
 400
 401 /*
 402  * Find divisor for the given clock and target rate.
 403  *
 404  * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
 405  * they are only settable as part of virtual_prcm set.
 406  */
 407 static u32 omap2_clksel_round_rate(struct clk *tclk, u32 target_rate,
 408         u32 *new_div)
 409 {
 410         u32 gfx_div[] = {2, 3, 4};
 411         u32 sysclkout_div[] = {1, 2, 4, 8, 16};
 412         u32 dss1_div[] = {1, 2, 3, 4, 5, 6, 8, 9, 12, 16};
 413         u32 vlynq_div[] = {1, 2, 3, 4, 6, 8, 9, 12, 16, 18};
 414         u32 best_div = ~0, asize = 0;
 415         u32 *div_array = NULL;
 416
 417         switch (tclk->flags & SRC_RATE_SEL_MASK) {
 418         case CM_GFX_SEL1:
 419                 asize = ARRAY_SIZE(gfx_div);
 420                 div_array = gfx_div;
 421                 break;
 422         case CM_PLL_SEL1:
 423                 return omap2_dpll_round_rate(target_rate);
 424         case CM_SYSCLKOUT_SEL1:
 425                 asize = ARRAY_SIZE(sysclkout_div);
 426                 div_array = sysclkout_div;
 427                 break;
 428         case CM_CORE_SEL1:
 429                 if (tclk == &dss1_fck) {
 430                         if (tclk->parent == &core_ck) {
 431                                 asize = ARRAY_SIZE(dss1_div);
 432                                 div_array = dss1_div;
 433                         } else {
 434                                 *new_div = 0; /* fixed clk */
 435                                 return(tclk->parent->rate);
 436                         }
 437                 } else if ((tclk == &vlynq_fck) && cpu_is_omap2420()) {
 438                         if (tclk->parent == &core_ck) {
 439                                 asize = ARRAY_SIZE(vlynq_div);
 440                                 div_array = vlynq_div;
 441                         } else {
 442                                 *new_div = 0; /* fixed clk */
 443                                 return (tclk->parent->rate);
 444                         }
 445                 }
 446                 break;
 447         }
 448
 449         best_div = omap2_divider_from_table(asize, div_array,
 450                                             tclk->parent->rate, target_rate);
 451         if (best_div == ~0) {
 452                 *new_div = 1;
 453                 return best_div; /* signal error */
 454         }
 455
 456         *new_div = best_div;
 457         return (tclk->parent->rate / best_div);
 458 }
 459
 460 /* Given a clock and a rate apply a clock specific rounding function */
 461 static long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
 462 {
 463         u32 new_div = 0;
 464
 465         if (clk->flags & RATE_FIXED)
 466                 return clk->rate;
 467
 468         if (clk->flags & RATE_CKCTL)
 469                 return omap2_clksel_round_rate(clk, rate, &new_div);
 470
 471         if (clk->round_rate != 0)
 472                 return clk->round_rate(clk, rate);
 473
 474         return clk->rate;
 475 }
 476
 477 static int omap2_reprogram_dpll(struct clk * clk, unsigned long rate)
 478 {
 479         u32 flags, cur_rate, low, mult, div, valid_rate, done_rate;
 480         u32 bypass = 0;
 481         struct prcm_config tmpset;
 482         int ret = -EINVAL;
 483
 484         local_irq_save(flags);
 485         cur_rate = omap2_get_dpll_rate(&dpll_ck);
 486         mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 487         mult &= OMAP24XX_CORE_CLK_SRC_MASK;
 488
 489         if ((rate == (cur_rate / 2)) && (mult == 2)) {
 490                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
 491         } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
 492                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
 493         } else if (rate != cur_rate) {
 494                 valid_rate = omap2_dpll_round_rate(rate);
 495                 if (valid_rate != rate)
 496                         goto dpll_exit;
 497
 498                 if (mult == 1)
 499                         low = curr_prcm_set->dpll_speed;
 500                 else
 501                         low = curr_prcm_set->dpll_speed / 2;
 502
 503                 /* REVISIT: This sets several reserved bits? */
 504                 tmpset.cm_clksel1_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
 505                 tmpset.cm_clksel1_pll &= ~(0x3FFF << 8);
 506                 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
 507                 tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 508                 tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
 509                 if (rate > low) {
 510                         tmpset.cm_clksel2_pll |= 0x2;
 511                         mult = ((rate / 2) / 1000000);
 512                         done_rate = CORE_CLK_SRC_DPLL_X2;
 513                 } else {
 514                         tmpset.cm_clksel2_pll |= 0x1;
 515                         mult = (rate / 1000000);
 516                         done_rate = CORE_CLK_SRC_DPLL;
 517                 }
 518                 tmpset.cm_clksel1_pll |= (div << OMAP24XX_DPLL_DIV_SHIFT);
 519                 tmpset.cm_clksel1_pll |= (mult << OMAP24XX_DPLL_MULT_SHIFT);
 520
 521                 /* Worst case */
 522                 tmpset.base_sdrc_rfr = V24XX_SDRC_RFR_CTRL_BYPASS;
 523
 524                 if (rate == curr_prcm_set->xtal_speed)  /* If asking for 1-1 */
 525                         bypass = 1;
 526
 527                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */
 528
 529                 /* Force dll lock mode */
 530                 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
 531                                bypass);
 532
 533                 /* Errata: ret dll entry state */
 534                 omap2_init_memory_params(omap2_dll_force_needed());
 535                 omap2_reprogram_sdrc(done_rate, 0);
 536         }
 537         omap2_clksel_recalc(&dpll_ck);
 538         ret = 0;
 539
 540 dpll_exit:
 541         local_irq_restore(flags);
 542         return(ret);
 543 }
 544
 545 /* Just return the MPU speed */
 546 static void omap2_mpu_recalc(struct clk * clk)
 547 {
 548         clk->rate = curr_prcm_set->mpu_speed;
 549 }
 550
 551 /*
 552  * Look for a rate equal or less than the target rate given a configuration set.
 553  *
 554  * What's not entirely clear is "which" field represents the key field.
 555  * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
 556  * just uses the ARM rates.
 557  */
 558 static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate)
 559 {
 560         struct prcm_config * ptr;
 561         long highest_rate;
 562
 563         if (clk != &virt_prcm_set)
 564                 return -EINVAL;
 565
 566         highest_rate = -EINVAL;
 567
 568         for (ptr = rate_table; ptr->mpu_speed; ptr++) {
 569                 if (!(ptr->flags & cpu_mask))
 570                         continue;
 571                 if (ptr->xtal_speed != sys_ck.rate)
 572                         continue;
 573
 574                 highest_rate = ptr->mpu_speed;
 575
 576                 /* Can check only after xtal frequency check */
 577                 if (ptr->mpu_speed <= rate)
 578                         break;
 579         }
 580         return highest_rate;
 581 }
 582
 583 /*
 584  * omap2_convert_field_to_div() - turn field value into integer divider
 585  */
 586 static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val)
 587 {
 588         u32 i;
 589         u32 clkout_array[] = {1, 2, 4, 8, 16};
 590
 591         if ((div_sel & SRC_RATE_SEL_MASK) == CM_SYSCLKOUT_SEL1) {
 592                 for (i = 0; i < 5; i++) {
 593                         if (field_val == i)
 594                                 return clkout_array[i];
 595                 }
 596                 return ~0;
 597         } else
 598                 return field_val;
 599 }
 600
 601 /*
 602  * Returns the CLKSEL divider register value
 603  * REVISIT: This should be cleaned up to work nicely with void __iomem *
 604  */
 605 static u32 omap2_get_clksel(u32 *div_sel, u32 *field_mask,
 606                             struct clk *clk)
 607 {
 608         int ret = ~0;
 609         u32 reg_val, div_off;
 610         void __iomem *div_addr = 0;
 611         u32 mask = ~0;
 612
 613         div_off = clk->rate_offset;
 614
 615         switch ((*div_sel & SRC_RATE_SEL_MASK)) {
 616         case CM_MPU_SEL1:
 617                 div_addr = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL);
 618                 mask = OMAP24XX_CLKSEL_MPU_MASK;
 619                 break;
 620         case CM_DSP_SEL1:
 621                 div_addr = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL);
 622                 if (cpu_is_omap2420()) {
 623                         if (div_off == OMAP24XX_CLKSEL_DSP_SHIFT)
 624                                 mask = OMAP24XX_CLKSEL_DSP_MASK;
 625                         else if (div_off == OMAP2420_CLKSEL_IVA_SHIFT)
 626                                 mask = OMAP2420_CLKSEL_IVA_MASK;
 627                         else if (div_off == OMAP24XX_CLKSEL_DSP_IF_SHIFT)
 628                                 mask = OMAP24XX_CLKSEL_DSP_IF_MASK;
 629                 } else if (cpu_is_omap2430()) {
 630                         if (div_off == OMAP24XX_CLKSEL_DSP_SHIFT)
 631                                 mask = OMAP24XX_CLKSEL_DSP_MASK;
 632                         else if (div_off == OMAP24XX_CLKSEL_DSP_IF_SHIFT)
 633                                 mask = OMAP24XX_CLKSEL_DSP_IF_MASK;
 634                 }
 635         case CM_GFX_SEL1:
 636                 div_addr = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL);
 637                 if (div_off == OMAP_CLKSEL_GFX_SHIFT)
 638                         mask = OMAP_CLKSEL_GFX_MASK;
 639                 break;
 640         case CM_MODEM_SEL1:
 641                 div_addr = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL);
 642                 if (div_off == OMAP2430_CLKSEL_MDM_SHIFT)
 643                         mask = OMAP2430_CLKSEL_MDM_MASK;
 644                 break;
 645         case CM_SYSCLKOUT_SEL1:
 646                 div_addr = OMAP24XX_PRCM_CLKOUT_CTRL;
 647                 if (div_off == OMAP24XX_CLKOUT_DIV_SHIFT)
 648                         mask = OMAP24XX_CLKOUT_DIV_MASK;
 649                 else if (div_off == OMAP2420_CLKOUT2_DIV_SHIFT)
 650                         mask = OMAP2420_CLKOUT2_DIV_MASK;
 651                 break;
 652         case CM_CORE_SEL1:
 653                 div_addr = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1);
 654                 switch (div_off) {
 655                 case OMAP24XX_CLKSEL_L3_SHIFT:
 656                         mask = OMAP24XX_CLKSEL_L3_MASK;
 657                         break;
 658                 case OMAP24XX_CLKSEL_L4_SHIFT:
 659                         mask = OMAP24XX_CLKSEL_L4_MASK;
 660                         break;
 661                 case OMAP24XX_CLKSEL_DSS1_SHIFT:
 662                         mask = OMAP24XX_CLKSEL_DSS1_MASK;
 663                         break;
 664                 case OMAP24XX_CLKSEL_DSS2_SHIFT:
 665                         mask = OMAP24XX_CLKSEL_DSS2_MASK;
 666                         break;
 667                 case OMAP2420_CLKSEL_VLYNQ_SHIFT:
 668                         mask = OMAP2420_CLKSEL_VLYNQ_MASK;
 669                         break;
 670                 case OMAP24XX_CLKSEL_SSI_SHIFT:
 671                         mask = OMAP24XX_CLKSEL_SSI_MASK;
 672                         break;
 673                 case OMAP24XX_CLKSEL_USB_SHIFT:
 674                         mask = OMAP24XX_CLKSEL_USB_MASK;
 675                         break;
 676                 }
 677         }
 678
 679         *field_mask = (mask >> div_off);
 680
 681         if (unlikely(mask == ~0))
 682                 div_addr = 0;
 683
 684         *div_sel = (u32)div_addr;
 685
 686         if (unlikely(div_addr == 0))
 687                 return ret;
 688
 689         /* Isolate field */
 690         reg_val = cm_read_reg(div_addr) & mask;
 691
 692         /* Normalize back to divider value */
 693         reg_val >>= div_off;
 694
 695         return reg_val;
 696 }
 697
 698 /*
 699  * Return divider to be applied to parent clock.
 700  * Return 0 on error.
 701  */
 702 static u32 omap2_clksel_get_divisor(struct clk *clk)
 703 {
 704         int ret = 0;
 705         u32 div, div_sel, div_off, field_mask, field_val;
 706
 707         /* isolate control register */
 708         div_sel = (SRC_RATE_SEL_MASK & clk->flags);
 709
 710         div_off = clk->rate_offset;
 711         field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
 712         if (div_sel == 0)
 713                 return ret;
 714
 715         div_sel = (SRC_RATE_SEL_MASK & clk->flags);
 716         div = omap2_clksel_to_divisor(div_sel, field_val);
 717
 718         return div;
 719 }
 720
 721 /* Set the clock rate for a clock source */
 722 static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
 723 {
 724         int ret = -EINVAL;
 725         void __iomem * reg;
 726         u32 div_sel, div_off, field_mask, field_val, reg_val, validrate;
 727         u32 new_div = 0;
 728
 729         if (!(clk->flags & CONFIG_PARTICIPANT) && (clk->flags & RATE_CKCTL)) {
 730                 if (clk == &dpll_ck)
 731                         return omap2_reprogram_dpll(clk, rate);
 732
 733                 /* Isolate control register */
 734                 div_sel = (SRC_RATE_SEL_MASK & clk->flags);
 735                 div_off = clk->rate_offset;
 736
 737                 validrate = omap2_clksel_round_rate(clk, rate, &new_div);
 738                 if (validrate != rate)
 739                         return ret;
 740
 741                 field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
 742                 if (div_sel == 0)
 743                         return ret;
 744
 745                 if (clk->flags & CM_SYSCLKOUT_SEL1) {
 746                         switch (new_div) {
 747                         case 16:
 748                                 field_val = 4;
 749                                 break;
 750                         case 8:
 751                                 field_val = 3;
 752                                 break;
 753                         case 4:
 754                                 field_val = 2;
 755                                 break;
 756                         case 2:
 757                                 field_val = 1;
 758                                 break;
 759                         case 1:
 760                                 field_val = 0;
 761                                 break;
 762                         }
 763                 } else
 764                         field_val = new_div;
 765
 766                 reg = (void __iomem *)div_sel;
 767
 768                 reg_val = cm_read_reg(reg);
 769                 reg_val &= ~(field_mask << div_off);
 770                 reg_val |= (field_val << div_off);
 771                 cm_write_reg(reg_val, reg);
 772                 wmb();
 773                 clk->rate = clk->parent->rate / new_div;
 774
 775                 if (clk->flags & DELAYED_APP) {
 776                         prm_write_reg(OMAP24XX_VALID_CONFIG,
 777                                       OMAP24XX_PRCM_CLKCFG_CTRL);
 778                         wmb();
 779                 }
 780                 ret = 0;
 781         } else if (clk->set_rate != 0) {
 782                 ret = clk->set_rate(clk, rate);
 783         }
 784
 785         if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
 786                 propagate_rate(clk);
 787
 788         return ret;
 789 }
 790
 791 /* Converts encoded control register address into a full address */
 792 static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset,
 793                                struct clk *src_clk, u32 *field_mask)
 794 {
 795         u32 val = ~0, mask = 0;
 796         void __iomem *src_reg_addr = 0;
 797
 798         /* Find target control register.*/
 799         switch ((*type_to_addr & SRC_RATE_SEL_MASK)) {
 800         case CM_CORE_SEL1:
 801                 src_reg_addr = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1);
 802                 if (reg_offset == OMAP24XX_CLKSEL_DSS2_SHIFT) {
 803                         mask = OMAP24XX_CLKSEL_DSS2_MASK;
 804                         mask >>= OMAP24XX_CLKSEL_DSS2_SHIFT;
 805                         if (src_clk == &sys_ck)
 806                                 val = 0;
 807                         if (src_clk == &func_48m_ck)
 808                                 val = 1;
 809                 } else if (reg_offset == OMAP24XX_CLKSEL_DSS1_SHIFT) {
 810                         mask = OMAP24XX_CLKSEL_DSS1_MASK;
 811                         mask >>= OMAP24XX_CLKSEL_DSS1_SHIFT;
 812                         if (src_clk == &sys_ck)
 813                                 val = 0;
 814                         else if (src_clk == &core_ck)   /* divided clock */
 815                                 val = 0x10;             /* rate needs fixing */
 816                 } else if ((reg_offset == OMAP2420_CLKSEL_VLYNQ_SHIFT) &&
 817                            cpu_is_omap2420()) {
 818                         mask = OMAP2420_CLKSEL_VLYNQ_MASK;
 819                         mask >>= OMAP2420_CLKSEL_VLYNQ_SHIFT;
 820                         if (src_clk == &func_96m_ck)
 821                                 val = 0;
 822                         else if (src_clk == &core_ck)
 823                                 val = 0x10;             /* rate needs fixing */
 824                 }
 825                 break;
 826         case CM_CORE_SEL2:
 827                 src_reg_addr = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2);
 828                 mask = 0x3;
 829                 if (src_clk == &func_32k_ck)
 830                         val = 0x0;
 831                 if (src_clk == &sys_ck)
 832                         val = 0x1;
 833                 if (src_clk == &alt_ck)
 834                         val = 0x2;
 835                 break;
 836         case CM_WKUP_SEL1:
 837                 src_reg_addr = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL);
 838                 mask = 0x3;
 839                 if (src_clk == &func_32k_ck)
 840                         val = 0x0;
 841                 if (src_clk == &sys_ck)
 842                         val = 0x1;
 843                 if (src_clk == &alt_ck)
 844                         val = 0x2;
 845                 break;
 846         case CM_PLL_SEL1:
 847                 src_reg_addr = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1);
 848                 mask = 0x1;
 849                 if (reg_offset == 0x3) {
 850                         if (src_clk == &apll96_ck)
 851                                 val = 0;
 852                         if (src_clk == &alt_ck)
 853                                 val = 1;
 854                 }
 855                 else if (reg_offset == 0x5) {
 856                         if (src_clk == &apll54_ck)
 857                                 val = 0;
 858                         if (src_clk == &alt_ck)
 859                                 val = 1;
 860                 }
 861                 break;
 862         case CM_PLL_SEL2:
 863                 src_reg_addr = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2);
 864                 mask = 0x3;
 865                 if (src_clk == &func_32k_ck)
 866                         val = 0x0;
 867                 if (src_clk == &dpll_ck)
 868                         val = 0x2;
 869                 break;
 870         case CM_SYSCLKOUT_SEL1:
 871                 src_reg_addr = OMAP24XX_PRCM_CLKOUT_CTRL;
 872                 mask = 0x3;
 873                 if (src_clk == &dpll_ck)
 874                         val = 0;
 875                 if (src_clk == &sys_ck)
 876                         val = 1;
 877                 if (src_clk == &func_96m_ck)
 878                         val = 2;
 879                 if (src_clk == &func_54m_ck)
 880                         val = 3;
 881                 break;
 882         }
 883
 884         if (val == ~0)                  /* Catch errors in offset */
 885                 *type_to_addr = 0;
 886         else
 887                 *type_to_addr = (u32)src_reg_addr;
 888         *field_mask = mask;
 889
 890         return val;
 891 }
 892
 893 static int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
 894 {
 895         void __iomem * reg;
 896         u32 src_sel, src_off, field_val, field_mask, reg_val, rate;
 897         int ret = -EINVAL;
 898
 899         if (unlikely(clk->flags & CONFIG_PARTICIPANT))
 900                 return ret;
 901
 902         if (clk->flags & SRC_SEL_MASK) {        /* On-chip SEL collection */
 903                 src_sel = (SRC_RATE_SEL_MASK & clk->flags);
 904                 src_off = clk->src_offset;
 905
 906                 if (src_sel == 0)
 907                         goto set_parent_error;
 908
 909                 field_val = omap2_get_src_field(&src_sel, src_off, new_parent,
 910                                                 &field_mask);
 911
 912                 reg = (void __iomem *)src_sel;
 913
 914                 if (clk->usecount > 0)
 915                         _omap2_clk_disable(clk);
 916
 917                 /* Set new source value (previous dividers if any in effect) */
 918                 reg_val = __raw_readl(reg) & ~(field_mask << src_off);
 919                 reg_val |= (field_val << src_off);
 920                 __raw_writel(reg_val, reg);
 921                 wmb();
 922
 923                 if (clk->flags & DELAYED_APP) {
 924                         prm_write_reg(OMAP24XX_VALID_CONFIG,
 925                                       OMAP24XX_PRCM_CLKCFG_CTRL);
 926                         wmb();
 927                 }
 928                 if (clk->usecount > 0)
 929                         _omap2_clk_enable(clk);
 930
 931                 clk->parent = new_parent;
 932
 933                 /* SRC_RATE_SEL_MASK clocks follow their parents rates.*/
 934                 if ((new_parent == &core_ck) &&
 935                     (clk == &dss1_fck || clk == &vlynq_fck))
 936                         clk->rate = new_parent->rate / 0x10;
 937                 else
 938                         clk->rate = new_parent->rate;
 939
 940                 if (unlikely(clk->flags & RATE_PROPAGATES))
 941                         propagate_rate(clk);
 942
 943                 return 0;
 944         } else {
 945                 clk->parent = new_parent;
 946                 rate = new_parent->rate;
 947                 omap2_clk_set_rate(clk, rate);
 948                 ret = 0;
 949         }
 950
 951  set_parent_error:
 952         return ret;
 953 }
 954
 955 /* Sets basic clocks based on the specified rate */
 956 static int omap2_select_table_rate(struct clk * clk, unsigned long rate)
 957 {
 958         u32 flags, cur_rate, done_rate, bypass = 0, tmp;
 959         struct prcm_config *prcm;
 960         unsigned long found_speed = 0;
 961
 962         if (clk != &virt_prcm_set)
 963                 return -EINVAL;
 964
 965         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
 966                 if (!(prcm->flags & cpu_mask))
 967                         continue;
 968
 969                 if (prcm->xtal_speed != sys_ck.rate)
 970                         continue;
 971
 972                 if (prcm->mpu_speed <= rate) {
 973                         found_speed = prcm->mpu_speed;
 974                         break;
 975                 }
 976         }
 977
 978         if (!found_speed) {
 979                 printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
 980                        rate / 1000000);
 981                 return -EINVAL;
 982         }
 983
 984         curr_prcm_set = prcm;
 985         cur_rate = omap2_get_dpll_rate(&dpll_ck);
 986
 987         if (prcm->dpll_speed == cur_rate / 2) {
 988                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
 989         } else if (prcm->dpll_speed == cur_rate * 2) {
 990                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
 991         } else if (prcm->dpll_speed != cur_rate) {
 992                 local_irq_save(flags);
 993
 994                 if (prcm->dpll_speed == prcm->xtal_speed)
 995                         bypass = 1;
 996
 997                 if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) == 2)
 998                         done_rate = CORE_CLK_SRC_DPLL_X2;
 999                 else
1000                         done_rate = CORE_CLK_SRC_DPLL;
1001
1002                 /* MPU divider */
1003                 cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
1004
1005                 /* dsp + iva1 div(2420), iva2.1(2430) */
1006                 cm_write_mod_reg(prcm->cm_clksel_dsp,
1007                                  OMAP24XX_DSP_MOD, CM_CLKSEL);
1008
1009                 cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
1010
1011                 /* Major subsystem dividers */
1012                 tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & 0x2000;
1013                 cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1);
1014                 if (cpu_is_omap2430())
1015                         cm_write_mod_reg(prcm->cm_clksel_mdm,
1016                                          OMAP2430_MDM_MOD, CM_CLKSEL);
1017
1018                 /* x2 to enter init_mem */
1019                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
1020
1021                 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
1022                                bypass);
1023
1024                 omap2_init_memory_params(omap2_dll_force_needed());
1025                 omap2_reprogram_sdrc(done_rate, 0);
1026
1027                 local_irq_restore(flags);
1028         }
1029         omap2_clksel_recalc(&dpll_ck);
1030
1031         return 0;
1032 }
1033
1034 /*-------------------------------------------------------------------------
1035  * Omap2 clock reset and init functions
1036  *-------------------------------------------------------------------------*/
1037
1038 #ifdef CONFIG_OMAP_RESET_CLOCKS
1039 static void __init omap2_clk_disable_unused(struct clk *clk)
1040 {
1041         u32 regval32;
1042
1043         regval32 = cm_read_reg(clk->enable_reg);
1044         if ((regval32 & (1 << clk->enable_bit)) == 0)
1045                 return;
1046
1047         printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
1048         _omap2_clk_disable(clk);
1049 }
1050 #else
1051 #define omap2_clk_disable_unused        NULL
1052 #endif
1053
1054 static struct clk_functions omap2_clk_functions = {
1055         .clk_enable             = omap2_clk_enable,
1056         .clk_disable            = omap2_clk_disable,
1057         .clk_round_rate         = omap2_clk_round_rate,
1058         .clk_set_rate           = omap2_clk_set_rate,
1059         .clk_set_parent         = omap2_clk_set_parent,
1060         .clk_disable_unused     = omap2_clk_disable_unused,
1061 };
1062
1063 static void __init omap2_get_crystal_rate(struct clk *osc, struct clk *sys)
1064 {
1065         u32 div, aplls, sclk = 13000000;
1066
1067         aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
1068         aplls &= OMAP24XX_APLLS_CLKIN_MASK;
1069         aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;   /* Isolate field, 0,2,3 */
1070
1071         if (aplls == 0)
1072                 sclk = 19200000;
1073         else if (aplls == 2)
1074                 sclk = 13000000;
1075         else if (aplls == 3)
1076                 sclk = 12000000;
1077
1078         div = prm_read_reg(OMAP24XX_PRCM_CLKSRC_CTRL);
1079         div &= OMAP_SYSCLKDIV_MASK;
1080         div >>= sys->rate_offset;
1081
1082         osc->rate = sclk;
1083         sys->rate = osc->rate / div;
1084 }
1085
1086 /*
1087  * Set clocks for bypass mode for reboot to work.
1088  */
1089 void omap2_clk_prepare_for_reboot(void)
1090 {
1091         u32 rate;
1092
1093         if (vclk == NULL || sclk == NULL)
1094                 return;
1095
1096         rate = clk_get_rate(sclk);
1097         clk_set_rate(vclk, rate);
1098 }
1099
1100 /*
1101  * Switch the MPU rate if specified on cmdline.
1102  * We cannot do this early until cmdline is parsed.
1103  */
1104 static int __init omap2_clk_arch_init(void)
1105 {
1106         if (!mpurate)
1107                 return -EINVAL;
1108
1109         if (omap2_select_table_rate(&virt_prcm_set, mpurate))
1110                 printk(KERN_ERR "Could not find matching MPU rate\n");
1111
1112         propagate_rate(&osc_ck);                /* update main root fast */
1113         propagate_rate(&func_32k_ck);           /* update main root slow */
1114
1115         printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
1116                "%ld.%01ld/%ld/%ld MHz\n",
1117                (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
1118                (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
1119
1120         return 0;
1121 }
1122 arch_initcall(omap2_clk_arch_init);
1123
1124 int __init omap2_clk_init(void)
1125 {
1126         struct prcm_config *prcm;
1127         struct clk ** clkp;
1128         u32 clkrate;
1129
1130         clk_init(&omap2_clk_functions);
1131         omap2_get_crystal_rate(&osc_ck, &sys_ck);
1132
1133         for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
1134              clkp++) {
1135
1136                 if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
1137                         clk_register(*clkp);
1138                         continue;
1139                 }
1140
1141                 if ((*clkp)->flags & CLOCK_IN_OMAP243X && (cpu_is_omap2430() || cpu_is_omap34xx())) {
1142                         clk_register(*clkp);
1143                         continue;
1144                 }
1145         }
1146
1147         if (cpu_is_omap242x())
1148                 cpu_mask = RATE_IN_242X;
1149         else if (cpu_is_omap2430())
1150                 cpu_mask = RATE_IN_243X;
1151
1152         /* Check the MPU rate set by bootloader */
1153         clkrate = omap2_get_dpll_rate(&dpll_ck);
1154         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
1155                 if (!(prcm->flags & cpu_mask))
1156                         continue;
1157                 if (prcm->xtal_speed != sys_ck.rate)
1158                         continue;
1159                 if (prcm->dpll_speed <= clkrate)
1160                          break;
1161         }
1162         curr_prcm_set = prcm;
1163
1164         propagate_rate(&osc_ck);                /* update main root fast */
1165         propagate_rate(&func_32k_ck);           /* update main root slow */
1166
1167         printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
1168                "%ld.%01ld/%ld/%ld MHz\n",
1169                (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
1170                (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
1171
1172         /*
1173          * Only enable those clocks we will need, let the drivers
1174          * enable other clocks as necessary
1175          */
1176         clk_enable(&sync_32k_ick);
1177         clk_enable(&omapctrl_ick);
1178
1179         /* Force the APLLs always active. The clocks are idled
1180          * automatically by hardware. */
1181         clk_enable(&apll96_ck);
1182         clk_enable(&apll54_ck);
1183
1184         if (cpu_is_omap2430())
1185                 clk_enable(&sdrc_ick);
1186
1187         /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
1188         vclk = clk_get(NULL, "virt_prcm_set");
1189         sclk = clk_get(NULL, "sys_ck");
1190
1191         return 0;
1192 }