arch/arm/mach-omap2/clock.c

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock.c
   3  *
   4  *  Copyright (C) 2005 Texas Instruments Inc.
   5  *  Richard Woodruff <r-woodruff2@ti.com>
   6  *  Created for OMAP2.
   7  *
   8  *  Cleaned up and modified to use omap shared clock framework by
   9  *  Tony Lindgren <tony@atomide.com>
  10  *
  11  *  Based on omap1 clock.c, Copyright (C) 2004 - 2005 Nokia corporation
  12  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/device.h>
  21 #include <linux/list.h>
  22 #include <linux/errno.h>
  23 #include <linux/delay.h>
  24 #include <linux/clk.h>
  25
  26 #include <asm/io.h>
  27
  28 #include <asm/arch/clock.h>
  29 #include <asm/arch/sram.h>
  30
  31 #include "prcm-regs.h"
  32 #include "memory.h"
  33 #include "clock.h"
  34
  35 //#define DOWN_VARIABLE_DPLL 1                  /* Experimental */
  36
  37 static struct prcm_config *curr_prcm_set;
  38 static u32 curr_perf_level = PRCM_FULL_SPEED;
  39 static struct clk *vclk;
  40 static struct clk *sclk;
  41
  42 /*-------------------------------------------------------------------------
  43  * Omap2 specific clock functions
  44  *-------------------------------------------------------------------------*/
  45
  46 /* Recalculate SYST_CLK */
  47 static void omap2_sys_clk_recalc(struct clk * clk)
  48 {
  49         u32 div = PRCM_CLKSRC_CTRL;
  50         div &= (1 << 7) | (1 << 6);     /* Test if ext clk divided by 1 or 2 */
  51         div >>= clk->rate_offset;
  52         clk->rate = (clk->parent->rate / div);
  53         propagate_rate(clk);
  54 }
  55
  56 static u32 omap2_get_dpll_rate(struct clk * tclk)
  57 {
  58         long long dpll_clk;
  59         int dpll_mult, dpll_div, amult;
  60
  61         dpll_mult = (CM_CLKSEL1_PLL >> 12) & 0x03ff;    /* 10 bits */
  62         dpll_div = (CM_CLKSEL1_PLL >> 8) & 0x0f;        /* 4 bits */
  63         dpll_clk = (long long)tclk->parent->rate * dpll_mult;
  64         do_div(dpll_clk, dpll_div + 1);
  65         amult = CM_CLKSEL2_PLL & 0x3;
  66         dpll_clk *= amult;
  67
  68         return dpll_clk;
  69 }
  70
  71 static void omap2_followparent_recalc(struct clk *clk)
  72 {
  73         followparent_recalc(clk);
  74 }
  75
  76 static void omap2_propagate_rate(struct clk * clk)
  77 {
  78         if (!(clk->flags & RATE_FIXED))
  79                 clk->rate = clk->parent->rate;
  80
  81         propagate_rate(clk);
  82 }
  83
  84 static void omap2_set_osc_ck(int enable)
  85 {
  86         if (enable)
  87                 PRCM_CLKSRC_CTRL &= ~(0x3 << 3);
  88         else
  89                 PRCM_CLKSRC_CTRL |= 0x3 << 3;
  90 }
  91
  92 /* Enable an APLL if off */
  93 static void omap2_clk_fixed_enable(struct clk *clk)
  94 {
  95         u32 cval, i=0;
  96
  97         if (clk->enable_bit == 0xff)                    /* Parent will do it */
  98                 return;
  99
 100         cval = CM_CLKEN_PLL;
 101
 102         if ((cval & (0x3 << clk->enable_bit)) == (0x3 << clk->enable_bit))
 103                 return;
 104
 105         cval &= ~(0x3 << clk->enable_bit);
 106         cval |= (0x3 << clk->enable_bit);
 107         CM_CLKEN_PLL = cval;
 108
 109         if (clk == &apll96_ck)
 110                 cval = (1 << 8);
 111         else if (clk == &apll54_ck)
 112                 cval = (1 << 6);
 113
 114         while (!(CM_IDLEST_CKGEN & cval)) {             /* Wait for lock */
 115                 ++i;
 116                 udelay(1);
 117                 if (i == 100000)
 118                         break;
 119         }
 120 }
 121
 122 /* Enables clock without considering parent dependencies or use count
 123  * REVISIT: Maybe change this to use clk->enable like on omap1?
 124  */
 125 static int _omap2_clk_enable(struct clk * clk)
 126 {
 127         u32 regval32;
 128
 129         if (clk->flags & ALWAYS_ENABLED)
 130                 return 0;
 131
 132         if (unlikely(clk == &osc_ck)) {
 133                 omap2_set_osc_ck(1);
 134                 return 0;
 135         }
 136
 137         if (unlikely(clk->enable_reg == 0)) {
 138                 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
 139                        clk->name);
 140                 return 0;
 141         }
 142
 143         if (clk->enable_reg == (void __iomem *)&CM_CLKEN_PLL) {
 144                 omap2_clk_fixed_enable(clk);
 145                 return 0;
 146         }
 147
 148         regval32 = __raw_readl(clk->enable_reg);
 149         regval32 |= (1 << clk->enable_bit);
 150         __raw_writel(regval32, clk->enable_reg);
 151         wmb();
 152
 153         return 0;
 154 }
 155
 156 /* Stop APLL */
 157 static void omap2_clk_fixed_disable(struct clk *clk)
 158 {
 159         u32 cval;
 160
 161         if(clk->enable_bit == 0xff)             /* let parent off do it */
 162                 return;
 163
 164         cval = CM_CLKEN_PLL;
 165         cval &= ~(0x3 << clk->enable_bit);
 166         CM_CLKEN_PLL = cval;
 167 }
 168
 169 /* Disables clock without considering parent dependencies or use count */
 170 static void _omap2_clk_disable(struct clk *clk)
 171 {
 172         u32 regval32;
 173
 174         if (unlikely(clk == &osc_ck)) {
 175                 omap2_set_osc_ck(0);
 176                 return;
 177         }
 178
 179         if (clk->enable_reg == 0)
 180                 return;
 181
 182         if (clk->enable_reg == (void __iomem *)&CM_CLKEN_PLL) {
 183                 omap2_clk_fixed_disable(clk);
 184                 return;
 185         }
 186
 187         regval32 = __raw_readl(clk->enable_reg);
 188         regval32 &= ~(1 << clk->enable_bit);
 189         __raw_writel(regval32, clk->enable_reg);
 190         wmb();
 191 }
 192
 193 static int omap2_clk_enable(struct clk *clk)
 194 {
 195         int ret = 0;
 196
 197         if (clk->usecount++ == 0) {
 198                 if (likely((u32)clk->parent))
 199                         ret = omap2_clk_enable(clk->parent);
 200
 201                 if (unlikely(ret != 0)) {
 202                         clk->usecount--;
 203                         return ret;
 204                 }
 205
 206                 ret = _omap2_clk_enable(clk);
 207
 208                 if (unlikely(ret != 0) && clk->parent) {
 209                         omap2_clk_disable(clk->parent);
 210                         clk->usecount--;
 211                 }
 212         }
 213
 214         return ret;
 215 }
 216
 217 static void omap2_clk_disable(struct clk *clk)
 218 {
 219         if (clk->usecount > 0 && !(--clk->usecount)) {
 220                 _omap2_clk_disable(clk);
 221                 if (likely((u32)clk->parent))
 222                         omap2_clk_disable(clk->parent);
 223         }
 224 }
 225
 226 /*
 227  * Uses the current prcm set to tell if a rate is valid.
 228  * You can go slower, but not faster within a given rate set.
 229  */
 230 static u32 omap2_dpll_round_rate(unsigned long target_rate)
 231 {
 232         u32 high, low;
 233
 234         if ((CM_CLKSEL2_PLL & 0x3) == 1) {      /* DPLL clockout */
 235                 high = curr_prcm_set->dpll_speed * 2;
 236                 low = curr_prcm_set->dpll_speed;
 237         } else {                                /* DPLL clockout x 2 */
 238                 high = curr_prcm_set->dpll_speed;
 239                 low = curr_prcm_set->dpll_speed / 2;
 240         }
 241
 242 #ifdef DOWN_VARIABLE_DPLL
 243         if (target_rate > high)
 244                 return high;
 245         else
 246                 return target_rate;
 247 #else
 248         if (target_rate > low)
 249                 return high;
 250         else
 251                 return low;
 252 #endif
 253
 254 }
 255
 256 /*
 257  * Used for clocks that are part of CLKSEL_xyz governed clocks.
 258  * REVISIT: Maybe change to use clk->enable() functions like on omap1?
 259  */
 260 static void omap2_clksel_recalc(struct clk * clk)
 261 {
 262         u32 fixed = 0, div = 0;
 263
 264         if (clk == &dpll_ck) {
 265                 clk->rate = omap2_get_dpll_rate(clk);
 266                 fixed = 1;
 267                 div = 0;
 268         }
 269
 270         if (clk == &iva1_mpu_int_ifck) {
 271                 div = 2;
 272                 fixed = 1;
 273         }
 274
 275         if ((clk == &dss1_fck) && ((CM_CLKSEL1_CORE & (0x1f << 8)) == 0)) {
 276                 clk->rate = sys_ck.rate;
 277                 return;
 278         }
 279
 280         if (!fixed) {
 281                 div = omap2_clksel_get_divisor(clk);
 282                 if (div == 0)
 283                         return;
 284         }
 285
 286         if (div != 0) {
 287                 if (unlikely(clk->rate == clk->parent->rate / div))
 288                         return;
 289                 clk->rate = clk->parent->rate / div;
 290         }
 291
 292         if (unlikely(clk->flags & RATE_PROPAGATES))
 293                 propagate_rate(clk);
 294 }
 295
 296 /*
 297  * Finds best divider value in an array based on the source and target
 298  * rates. The divider array must be sorted with smallest divider first.
 299  */
 300 static inline u32 omap2_divider_from_table(u32 size, u32 *div_array,
 301                                            u32 src_rate, u32 tgt_rate)
 302 {
 303         int i, test_rate;
 304
 305         if (div_array == NULL)
 306                 return ~1;
 307
 308         for (i=0; i < size; i++) {
 309                 test_rate = src_rate / *div_array;
 310                 if (test_rate <= tgt_rate)
 311                         return *div_array;
 312                 ++div_array;
 313         }
 314
 315         return ~0;      /* No acceptable divider */
 316 }
 317
 318 /*
 319  * Find divisor for the given clock and target rate.
 320  *
 321  * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
 322  * they are only settable as part of virtual_prcm set.
 323  */
 324 static u32 omap2_clksel_round_rate(struct clk *tclk, u32 target_rate,
 325         u32 *new_div)
 326 {
 327         u32 gfx_div[] = {2, 3, 4};
 328         u32 sysclkout_div[] = {1, 2, 4, 8, 16};
 329         u32 dss1_div[] = {1, 2, 3, 4, 5, 6, 8, 9, 12, 16};
 330         u32 vylnq_div[] = {1, 2, 3, 4, 6, 8, 9, 12, 16, 18};
 331         u32 best_div = ~0, asize = 0;
 332         u32 *div_array = NULL;
 333
 334         switch (tclk->flags & SRC_RATE_SEL_MASK) {
 335         case CM_GFX_SEL1:
 336                 asize = 3;
 337                 div_array = gfx_div;
 338                 break;
 339         case CM_PLL_SEL1:
 340                 return omap2_dpll_round_rate(target_rate);
 341         case CM_SYSCLKOUT_SEL1:
 342                 asize = 5;
 343                 div_array = sysclkout_div;
 344                 break;
 345         case CM_CORE_SEL1:
 346                 if(tclk == &dss1_fck){
 347                         if(tclk->parent == &core_ck){
 348                                 asize = 10;
 349                                 div_array = dss1_div;
 350                         } else {
 351                                 *new_div = 0; /* fixed clk */
 352                                 return(tclk->parent->rate);
 353                         }
 354                 } else if((tclk == &vlynq_fck) && cpu_is_omap2420()){
 355                         if(tclk->parent == &core_ck){
 356                                 asize = 10;
 357                                 div_array = vylnq_div;
 358                         } else {
 359                                 *new_div = 0; /* fixed clk */
 360                                 return(tclk->parent->rate);
 361                         }
 362                 }
 363                 break;
 364         }
 365
 366         best_div = omap2_divider_from_table(asize, div_array,
 367          tclk->parent->rate, target_rate);
 368         if (best_div == ~0){
 369                 *new_div = 1;
 370                 return best_div; /* signal error */
 371         }
 372
 373         *new_div = best_div;
 374         return (tclk->parent->rate / best_div);
 375 }
 376
 377 /* Given a clock and a rate apply a clock specific rounding function */
 378 static long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
 379 {
 380         u32 new_div = 0;
 381         int valid_rate;
 382
 383         if (clk->flags & RATE_FIXED)
 384                 return clk->rate;
 385
 386         if (clk->flags & RATE_CKCTL) {
 387                 valid_rate = omap2_clksel_round_rate(clk, rate, &new_div);
 388                 return valid_rate;
 389         }
 390
 391         if (clk->round_rate != 0)
 392                 return clk->round_rate(clk, rate);
 393
 394         return clk->rate;
 395 }
 396
 397 /*
 398  * Check the DLL lock state, and return tue if running in unlock mode.
 399  * This is needed to compenste for the shifted DLL value in unlock mode.
 400  */
 401 static u32 omap2_dll_force_needed(void)
 402 {
 403         u32 dll_state = SDRC_DLLA_CTRL;         /* dlla and dllb are a set */
 404
 405         if ((dll_state & (1 << 2)) == (1 << 2))
 406                 return 1;
 407         else
 408                 return 0;
 409 }
 410
 411 static u32 omap2_reprogram_sdrc(u32 level, u32 force)
 412 {
 413         u32 slow_dll_ctrl, fast_dll_ctrl, m_type;
 414         u32 prev = curr_perf_level, flags;
 415
 416         if ((curr_perf_level == level) && !force)
 417                 return prev;
 418
 419         m_type = omap2_memory_get_type();
 420         slow_dll_ctrl = omap2_memory_get_slow_dll_ctrl();
 421         fast_dll_ctrl = omap2_memory_get_fast_dll_ctrl();
 422
 423         if (level == PRCM_HALF_SPEED) {
 424                 local_irq_save(flags);
 425                 PRCM_VOLTSETUP = 0xffff;
 426                 omap2_sram_reprogram_sdrc(PRCM_HALF_SPEED,
 427                                           slow_dll_ctrl, m_type);
 428                 curr_perf_level = PRCM_HALF_SPEED;
 429                 local_irq_restore(flags);
 430         }
 431         if (level == PRCM_FULL_SPEED) {
 432                 local_irq_save(flags);
 433                 PRCM_VOLTSETUP = 0xffff;
 434                 omap2_sram_reprogram_sdrc(PRCM_FULL_SPEED,
 435                                           fast_dll_ctrl, m_type);
 436                 curr_perf_level = PRCM_FULL_SPEED;
 437                 local_irq_restore(flags);
 438         }
 439
 440         return prev;
 441 }
 442
 443 static int omap2_reprogram_dpll(struct clk * clk, unsigned long rate)
 444 {
 445         u32 flags, cur_rate, low, mult, div, valid_rate, done_rate;
 446         u32 bypass = 0;
 447         struct prcm_config tmpset;
 448         int ret = -EINVAL;
 449
 450         local_irq_save(flags);
 451         cur_rate = omap2_get_dpll_rate(&dpll_ck);
 452         mult = CM_CLKSEL2_PLL & 0x3;
 453
 454         if ((rate == (cur_rate / 2)) && (mult == 2)) {
 455                 omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1);
 456         } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
 457                 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
 458         } else if (rate != cur_rate) {
 459                 valid_rate = omap2_dpll_round_rate(rate);
 460                 if (valid_rate != rate)
 461                         goto dpll_exit;
 462
 463                 if ((CM_CLKSEL2_PLL & 0x3) == 1)
 464                         low = curr_prcm_set->dpll_speed;
 465                 else
 466                         low = curr_prcm_set->dpll_speed / 2;
 467
 468                 tmpset.cm_clksel1_pll = CM_CLKSEL1_PLL;
 469                 tmpset.cm_clksel1_pll &= ~(0x3FFF << 8);
 470                 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
 471                 tmpset.cm_clksel2_pll = CM_CLKSEL2_PLL;
 472                 tmpset.cm_clksel2_pll &= ~0x3;
 473                 if (rate > low) {
 474                         tmpset.cm_clksel2_pll |= 0x2;
 475                         mult = ((rate / 2) / 1000000);
 476                         done_rate = PRCM_FULL_SPEED;
 477                 } else {
 478                         tmpset.cm_clksel2_pll |= 0x1;
 479                         mult = (rate / 1000000);
 480                         done_rate = PRCM_HALF_SPEED;
 481                 }
 482                 tmpset.cm_clksel1_pll |= ((div << 8) | (mult << 12));
 483
 484                 /* Worst case */
 485                 tmpset.base_sdrc_rfr = V24XX_SDRC_RFR_CTRL_BYPASS;
 486
 487                 if (rate == curr_prcm_set->xtal_speed)  /* If asking for 1-1 */
 488                         bypass = 1;
 489
 490                 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1); /* For init_mem */
 491
 492                 /* Force dll lock mode */
 493                 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
 494                                bypass);
 495
 496                 /* Errata: ret dll entry state */
 497                 omap2_init_memory_params(omap2_dll_force_needed());
 498                 omap2_reprogram_sdrc(done_rate, 0);
 499         }
 500         omap2_clksel_recalc(&dpll_ck);
 501         ret = 0;
 502
 503 dpll_exit:
 504         local_irq_restore(flags);
 505         return(ret);
 506 }
 507
 508 /* Just return the MPU speed */
 509 static void omap2_mpu_recalc(struct clk * clk)
 510 {
 511         clk->rate = curr_prcm_set->mpu_speed;
 512 }
 513
 514 /*
 515  * Look for a rate equal or less than the target rate given a configuration set.
 516  *
 517  * What's not entirely clear is "which" field represents the key field.
 518  * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
 519  * just uses the ARM rates.
 520  */
 521 static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate)
 522 {
 523         struct prcm_config * ptr;
 524         long highest_rate;
 525
 526         if (clk != &virt_prcm_set)
 527                 return -EINVAL;
 528
 529         highest_rate = -EINVAL;
 530
 531         for (ptr = rate_table; ptr->mpu_speed; ptr++) {
 532                 if (ptr->xtal_speed != sys_ck.rate)
 533                         continue;
 534
 535                 highest_rate = ptr->mpu_speed;
 536
 537                 /* Can check only after xtal frequency check */
 538                 if (ptr->mpu_speed <= rate)
 539                         break;
 540         }
 541         return highest_rate;
 542 }
 543
 544 /*
 545  * omap2_convert_field_to_div() - turn field value into integer divider
 546  */
 547 static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val)
 548 {
 549         u32 i;
 550         u32 clkout_array[] = {1, 2, 4, 8, 16};
 551
 552         if ((div_sel & SRC_RATE_SEL_MASK) == CM_SYSCLKOUT_SEL1) {
 553                 for (i = 0; i < 5; i++) {
 554                         if (field_val == i)
 555                                 return clkout_array[i];
 556                 }
 557                 return ~0;
 558         } else
 559                 return field_val;
 560 }
 561
 562 /*
 563  * Returns the CLKSEL divider register value
 564  * REVISIT: This should be cleaned up to work nicely with void __iomem *
 565  */
 566 static u32 omap2_get_clksel(u32 *div_sel, u32 *field_mask,
 567                             struct clk *clk)
 568 {
 569         int ret = ~0;
 570         u32 reg_val, div_off;
 571         u32 div_addr = 0;
 572         u32 mask = ~0;
 573
 574         div_off = clk->rate_offset;
 575
 576         switch ((*div_sel & SRC_RATE_SEL_MASK)) {
 577         case CM_MPU_SEL1:
 578                 div_addr = (u32)&CM_CLKSEL_MPU;
 579                 mask = 0x1f;
 580                 break;
 581         case CM_DSP_SEL1:
 582                 div_addr = (u32)&CM_CLKSEL_DSP;
 583                 if (cpu_is_omap2420()) {
 584                         if ((div_off == 0) || (div_off == 8))
 585                                 mask = 0x1f;
 586                         else if (div_off == 5)
 587                                 mask = 0x3;
 588                 } else if (cpu_is_omap2430()) {
 589                         if (div_off == 0)
 590                                 mask = 0x1f;
 591                         else if (div_off == 5)
 592                                 mask = 0x3;
 593                 }
 594                 break;
 595         case CM_GFX_SEL1:
 596                 div_addr = (u32)&CM_CLKSEL_GFX;
 597                 if (div_off == 0)
 598                         mask = 0x7;
 599                 break;
 600         case CM_MODEM_SEL1:
 601                 div_addr = (u32)&CM_CLKSEL_MDM;
 602                 if (div_off == 0)
 603                         mask = 0xf;
 604                 break;
 605         case CM_SYSCLKOUT_SEL1:
 606                 div_addr = (u32)&PRCM_CLKOUT_CTRL;
 607                 if ((div_off == 3) || (div_off = 11))
 608                         mask= 0x3;
 609                 break;
 610         case CM_CORE_SEL1:
 611                 div_addr = (u32)&CM_CLKSEL1_CORE;
 612                 switch (div_off) {
 613                 case 0:                                 /* l3 */
 614                 case 8:                                 /* dss1 */
 615                 case 15:                                /* vylnc-2420 */
 616                 case 20:                                /* ssi */
 617                         mask = 0x1f; break;
 618                 case 5:                                 /* l4 */
 619                         mask = 0x3; break;
 620                 case 13:                                /* dss2 */
 621                         mask = 0x1; break;
 622                 case 25:                                /* usb */
 623                         mask = 0x7; break;
 624                 }
 625         }
 626
 627         *field_mask = mask;
 628
 629         if (unlikely(mask == ~0))
 630                 div_addr = 0;
 631
 632         *div_sel = div_addr;
 633
 634         if (unlikely(div_addr == 0))
 635                 return ret;
 636
 637         /* Isolate field */
 638         reg_val = __raw_readl((void __iomem *)div_addr) & (mask << div_off);
 639
 640         /* Normalize back to divider value */
 641         reg_val >>= div_off;
 642
 643         return reg_val;
 644 }
 645
 646 /*
 647  * Return divider to be applied to parent clock.
 648  * Return 0 on error.
 649  */
 650 static u32 omap2_clksel_get_divisor(struct clk *clk)
 651 {
 652         int ret = 0;
 653         u32 div, div_sel, div_off, field_mask, field_val;
 654
 655         /* isolate control register */
 656         div_sel = (SRC_RATE_SEL_MASK & clk->flags);
 657
 658         div_off = clk->rate_offset;
 659         field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
 660         if (div_sel == 0)
 661                 return ret;
 662
 663         div_sel = (SRC_RATE_SEL_MASK & clk->flags);
 664         div = omap2_clksel_to_divisor(div_sel, field_val);
 665
 666         return div;
 667 }
 668
 669 /* Set the clock rate for a clock source */
 670 static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
 671
 672 {
 673         int ret = -EINVAL;
 674         void __iomem * reg;
 675         u32 div_sel, div_off, field_mask, field_val, reg_val, validrate;
 676         u32 new_div = 0;
 677
 678         if (!(clk->flags & CONFIG_PARTICIPANT) && (clk->flags & RATE_CKCTL)) {
 679                 if (clk == &dpll_ck)
 680                         return omap2_reprogram_dpll(clk, rate);
 681
 682                 /* Isolate control register */
 683                 div_sel = (SRC_RATE_SEL_MASK & clk->flags);
 684                 div_off = clk->rate_offset;
 685
 686                 validrate = omap2_clksel_round_rate(clk, rate, &new_div);
 687                 if (validrate != rate)
 688                         return(ret);
 689
 690                 field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
 691                 if (div_sel == 0)
 692                         return ret;
 693
 694                 if (clk->flags & CM_SYSCLKOUT_SEL1) {
 695                         switch (new_div) {
 696                         case 16:
 697                                 field_val = 4;
 698                                 break;
 699                         case 8:
 700                                 field_val = 3;
 701                                 break;
 702                         case 4:
 703                                 field_val = 2;
 704                                 break;
 705                         case 2:
 706                                 field_val = 1;
 707                                 break;
 708                         case 1:
 709                                 field_val = 0;
 710                                 break;
 711                         }
 712                 } else
 713                         field_val = new_div;
 714
 715                 reg = (void __iomem *)div_sel;
 716
 717                 reg_val = __raw_readl(reg);
 718                 reg_val &= ~(field_mask << div_off);
 719                 reg_val |= (field_val << div_off);
 720                 __raw_writel(reg_val, reg);
 721                 wmb();
 722                 clk->rate = clk->parent->rate / field_val;
 723
 724                 if (clk->flags & DELAYED_APP) {
 725                         __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL);
 726                         wmb();
 727                 }
 728                 ret = 0;
 729         } else if (clk->set_rate != 0)
 730                 ret = clk->set_rate(clk, rate);
 731
 732         if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
 733                 propagate_rate(clk);
 734
 735         return ret;
 736 }
 737
 738 /* Converts encoded control register address into a full address */
 739 static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset,
 740                                struct clk *src_clk, u32 *field_mask)
 741 {
 742         u32 val = ~0, src_reg_addr = 0, mask = 0;
 743
 744         /* Find target control register.*/
 745         switch ((*type_to_addr & SRC_RATE_SEL_MASK)) {
 746         case CM_CORE_SEL1:
 747                 src_reg_addr = (u32)&CM_CLKSEL1_CORE;
 748                 if (reg_offset == 13) {                 /* DSS2_fclk */
 749                         mask = 0x1;
 750                         if (src_clk == &sys_ck)
 751                                 val = 0;
 752                         if (src_clk == &func_48m_ck)
 753                                 val = 1;
 754                 } else if (reg_offset == 8) {           /* DSS1_fclk */
 755                         mask = 0x1f;
 756                         if (src_clk == &sys_ck)
 757                                 val = 0;
 758                         else if (src_clk == &core_ck)   /* divided clock */
 759                                 val = 0x10;             /* rate needs fixing */
 760                 } else if ((reg_offset == 15) && cpu_is_omap2420()){ /*vlnyq*/
 761                         mask = 0x1F;
 762                         if(src_clk == &func_96m_ck)
 763                                 val = 0;
 764                         else if (src_clk == &core_ck)
 765                                 val = 0x10;
 766                 }
 767                 break;
 768         case CM_CORE_SEL2:
 769                 src_reg_addr = (u32)&CM_CLKSEL2_CORE;
 770                 mask = 0x3;
 771                 if (src_clk == &func_32k_ck)
 772                         val = 0x0;
 773                 if (src_clk == &sys_ck)
 774                         val = 0x1;
 775                 if (src_clk == &alt_ck)
 776                         val = 0x2;
 777                 break;
 778         case CM_WKUP_SEL1:
 779                 src_reg_addr = (u32)&CM_CLKSEL_WKUP;
 780                 mask = 0x3;
 781                 if (src_clk == &func_32k_ck)
 782                         val = 0x0;
 783                 if (src_clk == &sys_ck)
 784                         val = 0x1;
 785                 if (src_clk == &alt_ck)
 786                         val = 0x2;
 787                 break;
 788         case CM_PLL_SEL1:
 789                 src_reg_addr = (u32)&CM_CLKSEL1_PLL;
 790                 mask = 0x1;
 791                 if (reg_offset == 0x3) {
 792                         if (src_clk == &apll96_ck)
 793                                 val = 0;
 794                         if (src_clk == &alt_ck)
 795                                 val = 1;
 796                 }
 797                 else if (reg_offset == 0x5) {
 798                         if (src_clk == &apll54_ck)
 799                                 val = 0;
 800                         if (src_clk == &alt_ck)
 801                                 val = 1;
 802                 }
 803                 break;
 804         case CM_PLL_SEL2:
 805                 src_reg_addr = (u32)&CM_CLKSEL2_PLL;
 806                 mask = 0x3;
 807                 if (src_clk == &func_32k_ck)
 808                         val = 0x0;
 809                 if (src_clk == &dpll_ck)
 810                         val = 0x2;
 811                 break;
 812         case CM_SYSCLKOUT_SEL1:
 813                 src_reg_addr = (u32)&PRCM_CLKOUT_CTRL;
 814                 mask = 0x3;
 815                 if (src_clk == &dpll_ck)
 816                         val = 0;
 817                 if (src_clk == &sys_ck)
 818                         val = 1;
 819                 if (src_clk == &func_96m_ck)
 820                         val = 2;
 821                 if (src_clk == &func_54m_ck)
 822                         val = 3;
 823                 break;
 824         }
 825
 826         if (val == ~0)                  /* Catch errors in offset */
 827                 *type_to_addr = 0;
 828         else
 829                 *type_to_addr = src_reg_addr;
 830         *field_mask = mask;
 831
 832         return val;
 833 }
 834
 835 static int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
 836 {
 837         void __iomem * reg;
 838         u32 src_sel, src_off, field_val, field_mask, reg_val, rate;
 839         int ret = -EINVAL;
 840
 841         if (unlikely(clk->flags & CONFIG_PARTICIPANT))
 842                 return ret;
 843
 844         if (clk->flags & SRC_SEL_MASK) {        /* On-chip SEL collection */
 845                 src_sel = (SRC_RATE_SEL_MASK & clk->flags);
 846                 src_off = clk->src_offset;
 847
 848                 if (src_sel == 0)
 849                         goto set_parent_error;
 850
 851                 field_val = omap2_get_src_field(&src_sel, src_off, new_parent,
 852                                                 &field_mask);
 853
 854                 reg = (void __iomem *)src_sel;
 855
 856                 if (clk->usecount > 0)
 857                         _omap2_clk_disable(clk);
 858
 859                 /* Set new source value (previous dividers if any in effect) */
 860                 reg_val = __raw_readl(reg) & ~(field_mask << src_off);
 861                 reg_val |= (field_val << src_off);
 862                 __raw_writel(reg_val, reg);
 863                 wmb();
 864
 865                 if (clk->flags & DELAYED_APP) {
 866                         __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL);
 867                         wmb();
 868                 }
 869                 if (clk->usecount > 0)
 870                         _omap2_clk_enable(clk);
 871
 872                 clk->parent = new_parent;
 873
 874                 /* SRC_RATE_SEL_MASK clocks follow their parents rates.*/
 875                 if ((new_parent == &core_ck) && (clk == &dss1_fck))
 876                         clk->rate = new_parent->rate / 0x10;
 877                 else
 878                         clk->rate = new_parent->rate;
 879
 880                 if (unlikely(clk->flags & RATE_PROPAGATES))
 881                         propagate_rate(clk);
 882
 883                 return 0;
 884         } else {
 885                 clk->parent = new_parent;
 886                 rate = new_parent->rate;
 887                 omap2_clk_set_rate(clk, rate);
 888                 ret = 0;
 889         }
 890
 891  set_parent_error:
 892         return ret;
 893 }
 894
 895 /* Sets basic clocks based on the specified rate */
 896 static int omap2_select_table_rate(struct clk * clk, unsigned long rate)
 897 {
 898         u32 flags, cur_rate, done_rate, bypass = 0;
 899         u8 cpu_mask = 0;
 900         struct prcm_config *prcm;
 901         unsigned long found_speed = 0;
 902
 903         if (clk != &virt_prcm_set)
 904                 return -EINVAL;
 905
 906         /* FIXME: Change cpu_is_omap2420() to cpu_is_omap242x() */
 907         if (cpu_is_omap2420())
 908                 cpu_mask = RATE_IN_242X;
 909         else if (cpu_is_omap2430())
 910                 cpu_mask = RATE_IN_243X;
 911
 912         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
 913                 if (!(prcm->flags & cpu_mask))
 914                         continue;
 915
 916                 if (prcm->xtal_speed != sys_ck.rate)
 917                         continue;
 918
 919                 if (prcm->mpu_speed <= rate) {
 920                         found_speed = prcm->mpu_speed;
 921                         break;
 922                 }
 923         }
 924
 925         if (!found_speed) {
 926                 printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
 927          rate / 1000000);
 928                 return -EINVAL;
 929         }
 930
 931         curr_prcm_set = prcm;
 932         cur_rate = omap2_get_dpll_rate(&dpll_ck);
 933
 934         if (prcm->dpll_speed == cur_rate / 2) {
 935                 omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1);
 936         } else if (prcm->dpll_speed == cur_rate * 2) {
 937                 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
 938         } else if (prcm->dpll_speed != cur_rate) {
 939                 local_irq_save(flags);
 940
 941                 if (prcm->dpll_speed == prcm->xtal_speed)
 942                         bypass = 1;
 943
 944                 if ((prcm->cm_clksel2_pll & 0x3) == 2)
 945                         done_rate = PRCM_FULL_SPEED;
 946                 else
 947                         done_rate = PRCM_HALF_SPEED;
 948
 949                 /* MPU divider */
 950                 CM_CLKSEL_MPU = prcm->cm_clksel_mpu;
 951
 952                 /* dsp + iva1 div(2420), iva2.1(2430) */
 953                 CM_CLKSEL_DSP = prcm->cm_clksel_dsp;
 954
 955                 CM_CLKSEL_GFX = prcm->cm_clksel_gfx;
 956
 957                 /* Major subsystem dividers */
 958                 CM_CLKSEL1_CORE = prcm->cm_clksel1_core;
 959                 if (cpu_is_omap2430())
 960                         CM_CLKSEL_MDM = prcm->cm_clksel_mdm;
 961
 962                 /* x2 to enter init_mem */
 963                 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
 964
 965                 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
 966                                bypass);
 967
 968                 omap2_init_memory_params(omap2_dll_force_needed());
 969                 omap2_reprogram_sdrc(done_rate, 0);
 970
 971                 local_irq_restore(flags);
 972         }
 973         omap2_clksel_recalc(&dpll_ck);
 974
 975         return 0;
 976 }
 977
 978 /*-------------------------------------------------------------------------
 979  * Omap2 clock reset and init functions
 980  *-------------------------------------------------------------------------*/
 981
 982 static struct clk_functions omap2_clk_functions = {
 983         .clk_enable             = omap2_clk_enable,
 984         .clk_disable            = omap2_clk_disable,
 985         .clk_round_rate         = omap2_clk_round_rate,
 986         .clk_set_rate           = omap2_clk_set_rate,
 987         .clk_set_parent         = omap2_clk_set_parent,
 988 };
 989
 990 static void __init omap2_get_crystal_rate(struct clk *osc, struct clk *sys)
 991 {
 992         u32 div, aplls, sclk = 13000000;
 993
 994         aplls = CM_CLKSEL1_PLL;
 995         aplls &= ((1 << 23) | (1 << 24) | (1 << 25));
 996         aplls >>= 23;                   /* Isolate field, 0,2,3 */
 997
 998         if (aplls == 0)
 999                 sclk = 19200000;
1000         else if (aplls == 2)
1001                 sclk = 13000000;
1002         else if (aplls == 3)
1003                 sclk = 12000000;
1004
1005         div = PRCM_CLKSRC_CTRL;
1006         div &= ((1 << 7) | (1 << 6));
1007         div >>= sys->rate_offset;
1008
1009         osc->rate = sclk * div;
1010         sys->rate = sclk;
1011 }
1012
1013 /*
1014  * Set clocks for bypass mode for reboot to work.
1015  */
1016 void omap2_clk_prepare_for_reboot(void)
1017 {
1018         u32 rate;
1019
1020         if (vclk == NULL || sclk == NULL)
1021                 return;
1022
1023         rate = clk_get_rate(sclk);
1024         clk_set_rate(vclk, rate);
1025 }
1026
1027 #ifdef CONFIG_OMAP_RESET_CLOCKS
1028 static void __init omap2_disable_unused_clocks(void)
1029 {
1030         struct clk *ck;
1031         u32 regval32;
1032
1033         list_for_each_entry(ck, &clocks, node) {
1034                 if (ck->usecount > 0 || (ck->flags & ALWAYS_ENABLED) ||
1035                         ck->enable_reg == 0)
1036                         continue;
1037
1038                 regval32 = __raw_readl(ck->enable_reg);
1039                 if ((regval32 & (1 << ck->enable_bit)) == 0)
1040                         continue;
1041
1042                 printk(KERN_INFO "Disabling unused clock \"%s\"\n", ck->name);
1043                 _omap2_clk_disable(ck);
1044         }
1045 }
1046 late_initcall(omap2_disable_unused_clocks);
1047 #endif
1048
1049 /*
1050  * Switch the MPU rate if specified on cmdline.
1051  * We cannot do this early until cmdline is parsed.
1052  */
1053 static int __init omap2_clk_arch_init(void)
1054 {
1055         if (!mpurate)
1056                 return -EINVAL;
1057
1058         if (omap2_select_table_rate(&virt_prcm_set, mpurate))
1059                 printk(KERN_ERR "Could not find matching MPU rate\n");
1060
1061         propagate_rate(&osc_ck);                /* update main root fast */
1062         propagate_rate(&func_32k_ck);           /* update main root slow */
1063
1064         printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
1065                "%ld.%01ld/%ld/%ld MHz\n",
1066                (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
1067                (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
1068
1069         return 0;
1070 }
1071 arch_initcall(omap2_clk_arch_init);
1072
1073 int __init omap2_clk_init(void)
1074 {
1075         struct prcm_config *prcm;
1076         struct clk ** clkp;
1077         u32 clkrate;
1078
1079         clk_init(&omap2_clk_functions);
1080         omap2_get_crystal_rate(&osc_ck, &sys_ck);
1081
1082         for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
1083              clkp++) {
1084
1085                 if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
1086                         clk_register(*clkp);
1087                         continue;
1088                 }
1089
1090                 if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) {
1091                         clk_register(*clkp);
1092                         continue;
1093                 }
1094         }
1095
1096         /* Check the MPU rate set by bootloader */
1097         clkrate = omap2_get_dpll_rate(&dpll_ck);
1098         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
1099                 if (prcm->xtal_speed != sys_ck.rate)
1100                         continue;
1101                 if (prcm->dpll_speed <= clkrate)
1102                          break;
1103         }
1104         curr_prcm_set = prcm;
1105
1106         propagate_rate(&osc_ck);                /* update main root fast */
1107         propagate_rate(&func_32k_ck);           /* update main root slow */
1108
1109         printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
1110                "%ld.%01ld/%ld/%ld MHz\n",
1111                (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
1112                (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
1113
1114         /*
1115          * Only enable those clocks we will need, let the drivers
1116          * enable other clocks as necessary
1117          */
1118         clk_enable(&sync_32k_ick);
1119         clk_enable(&omapctrl_ick);
1120         if (cpu_is_omap2430())
1121                 clk_enable(&sdrc_ick);
1122
1123         /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
1124         vclk = clk_get(NULL, "virt_prcm_set");
1125         sclk = clk_get(NULL, "sys_ck");
1126
1127         return 0;
1128 }