2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/list.h>
21 #include <linux/errno.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
24 #include <linux/bitops.h>
27 #include <mach/clock.h>
28 #include <mach/clockdomain.h>
29 #include <mach/sram.h>
31 #include <mach/prcm.h>
32 #include <mach/control.h>
33 #include <asm/div64.h>
35 #include <mach/sdrc.h>
39 #include "prm-regbits-24xx.h"
41 #include "cm-regbits-24xx.h"
42 #include "cm-regbits-34xx.h"
44 #define MAX_CLOCK_ENABLE_WAIT 100000
46 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
47 #define DPLL_MIN_MULTIPLIER 1
48 #define DPLL_MIN_DIVIDER 1
50 /* Possible error results from _dpll_test_mult */
51 #define DPLL_MULT_UNDERFLOW (1 << 0)
54 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
55 * The higher the scale factor, the greater the risk of arithmetic overflow,
56 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
57 * must be a power of DPLL_SCALE_BASE.
59 #define DPLL_SCALE_FACTOR 64
60 #define DPLL_SCALE_BASE 2
61 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
62 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
64 /* Some OMAP2xxx CM_CLKSEL_PLL.ST_CORE_CLK bits - for omap2_get_dpll_rate() */
65 #define ST_CORE_CLK_REF 0x1
66 #define ST_CORE_CLK_32K 0x3
68 /* Bitmask to isolate the register type of clk.enable_reg */
69 #define PRCM_REGTYPE_MASK 0xf0
70 /* various CM register type options */
71 #define CM_FCLKEN_REGTYPE 0x00
72 #define CM_ICLKEN_REGTYPE 0x10
73 #define CM_IDLEST_REGTYPE 0x20
77 /*-------------------------------------------------------------------------
78 * OMAP2/3 specific clock functions
79 *-------------------------------------------------------------------------*/
82 * _omap2_clk_read_reg - read a clock register
85 * Given a struct clk *, returns the value of the clock's register.
87 static u32 _omap2_clk_read_reg(u16 reg_offset, struct clk *clk)
89 if (clk->prcm_mod & CLK_REG_IN_SCM)
90 return omap_ctrl_readl(reg_offset);
91 else if (clk->prcm_mod & CLK_REG_IN_PRM)
92 return prm_read_mod_reg(clk->prcm_mod & PRCM_MOD_ADDR_MASK,
95 return cm_read_mod_reg(clk->prcm_mod, reg_offset);
99 * _omap2_clk_write_reg - write a clock's register
100 * @v: value to write to the clock's enable_reg
103 * Given a register value @v and struct clk * @clk, writes the value of @v to
104 * the clock's enable register. No return value.
106 static void _omap2_clk_write_reg(u32 v, u16 reg_offset, struct clk *clk)
108 if (clk->prcm_mod & CLK_REG_IN_SCM)
109 omap_ctrl_writel(v, reg_offset);
110 else if (clk->prcm_mod & CLK_REG_IN_PRM)
111 prm_write_mod_reg(v, clk->prcm_mod & PRCM_MOD_ADDR_MASK,
114 cm_write_mod_reg(v, clk->prcm_mod, reg_offset);
119 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
120 * @clk: OMAP clock struct ptr to use
122 * Convert a clockdomain name stored in a struct clk 'clk' into a
123 * clockdomain pointer, and save it into the struct clk. Intended to be
124 * called during clk_register(). No return value.
126 void omap2_init_clk_clkdm(struct clk *clk)
128 struct clockdomain *clkdm;
130 if (!clk->clkdm.name) {
131 pr_err("clock: %s: missing clockdomain", clk->name);
135 clkdm = clkdm_lookup(clk->clkdm.name);
137 pr_debug("clock: associated clk %s to clkdm %s\n",
138 clk->name, clk->clkdm.name);
139 clk->clkdm.ptr = clkdm;
141 pr_err("clock: %s: could not associate to clkdm %s\n",
142 clk->name, clk->clkdm.name);
147 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
148 * @clk: OMAP clock struct ptr to use
150 * Given a pointer to a source-selectable struct clk, read the hardware
151 * register and determine what its parent is currently set to. Update the
152 * clk->parent field with the appropriate clk ptr.
154 void omap2_init_clksel_parent(struct clk *clk)
156 const struct clksel *clks;
157 const struct clksel_rate *clkr;
163 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
164 r >>= __ffs(clk->clksel_mask);
166 for (clks = clk->clksel; clks->parent && !found; clks++) {
167 for (clkr = clks->rates; clkr->div && !found; clkr++) {
168 if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
169 if (clk->parent != clks->parent) {
170 pr_debug("clock: inited %s parent "
172 clk->name, clks->parent->name,
174 clk->parent->name : "NULL"));
175 clk->parent = clks->parent;
183 printk(KERN_ERR "clock: init parent: could not find "
184 "regval %0x for clock %s\n", r, clk->name);
190 * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
191 * @clk: struct clk * of a DPLL
193 * DPLLs can be locked or bypassed - basically, enabled or disabled.
194 * When locked, the DPLL output depends on the M and N values. When
195 * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
196 * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
197 * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
198 * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
199 * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
200 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
201 * if the clock @clk is not a DPLL.
203 u32 omap2_get_dpll_rate(struct clk *clk)
206 u32 dpll_mult, dpll_div, v;
207 struct dpll_data *dd;
213 /* Return bypass rate if DPLL is bypassed */
214 v = __raw_readl(dd->idlest_reg) & dd->idlest_mask;
215 v >>= __ffs(dd->idlest_mask);
216 if (cpu_is_omap24xx()) {
218 if (v == ST_CORE_CLK_REF)
219 return clk->parent->rate; /* sys_clk */
220 else if (v == ST_CORE_CLK_32K)
223 } else if (cpu_is_omap34xx()) {
226 return dd->bypass_clk->rate;
230 v = __raw_readl(dd->mult_div1_reg);
231 dpll_mult = v & dd->mult_mask;
232 dpll_mult >>= __ffs(dd->mult_mask);
233 dpll_div = v & dd->div1_mask;
234 dpll_div >>= __ffs(dd->div1_mask);
236 dpll_clk = (long long)clk->parent->rate * dpll_mult;
237 do_div(dpll_clk, dpll_div + 1);
243 * Used for clocks that have the same value as the parent clock,
244 * divided by some factor
246 void omap2_fixed_divisor_recalc(struct clk *clk)
248 WARN_ON(!clk->fixed_div);
250 clk->rate = clk->parent->rate / clk->fixed_div;
252 if (clk->flags & RATE_PROPAGATES)
257 * omap2_wait_clock_ready - wait for clock to enable
258 * @reg: physical address of clock IDLEST register
259 * @mask: value to mask against to determine if the clock is active
260 * @name: name of the clock (for printk)
262 * Returns 1 if the clock enabled in time, or 0 if it failed to enable
263 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
265 int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
270 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
271 * 34xx reverses this, just to keep us on our toes
273 if (cpu_mask & (RATE_IN_242X | RATE_IN_243X))
275 else if (cpu_mask & RATE_IN_343X)
279 while (((__raw_readl(reg) & mask) != ena) &&
280 (i++ < MAX_CLOCK_ENABLE_WAIT)) {
284 if (i < MAX_CLOCK_ENABLE_WAIT)
285 pr_debug("Clock %s stable after %d loops\n", name, i);
287 printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
288 name, MAX_CLOCK_ENABLE_WAIT);
291 return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
296 * Note: We don't need special code here for INVERT_ENABLE
297 * for the time being since INVERT_ENABLE only applies to clocks enabled by
300 * REVISIT: This code is ugly and does not belong here.
302 static void omap2_clk_wait_ready(struct clk *clk)
304 u32 other_bit, idlest_bit;
305 unsigned long reg, other_reg, idlest_reg, prcm_regid;
307 /* Only CM-controlled clocks affect module IDLEST */
308 if (clk->prcm_mod & ~PRCM_MOD_ADDR_MASK)
311 reg = (unsigned long)clk->enable_reg;
312 prcm_regid = reg & 0xff;
314 other_reg = reg & ~PRCM_REGTYPE_MASK;
316 /* If we are enabling an fclk, also test the iclk; and vice versa */
317 if (prcm_regid >= CM_FCLKEN1 && prcm_regid <= OMAP24XX_CM_FCLKEN2)
318 other_reg |= CM_ICLKEN_REGTYPE;
320 other_reg |= CM_FCLKEN_REGTYPE;
322 /* Covers most of the cases - a few exceptions are below */
323 other_bit = 1 << clk->enable_bit;
324 idlest_bit = other_bit;
326 /* 24xx: DSS and CAM have no idlest bits for their target agents */
327 if (cpu_is_omap24xx() && clk->prcm_mod == CORE_MOD &&
328 (reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
330 if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
331 clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
332 clk->enable_bit == OMAP24XX_EN_CAM_SHIFT)
337 /* REVISIT: What are the appropriate exclusions for 34XX? */
338 if (cpu_is_omap34xx()) {
341 if (clk->prcm_mod == CORE_MOD &&
343 clk->enable_bit == OMAP3430_EN_SSI_SHIFT) {
345 if (system_rev == OMAP3430_REV_ES1_0)
348 idlest_bit = OMAP3430ES2_ST_SSI_IDLE;
352 if (clk->prcm_mod == OMAP3430_DSS_MOD) {
354 /* 3430ES1 DSS has no target idlest bits */
355 if (system_rev == OMAP3430_REV_ES1_0)
359 * For 3430ES2+ DSS, only wait once (dss1_alwon_fclk,
360 * dss_l3_iclk, dss_l4_iclk) are enabled
362 if (clk->enable_bit != OMAP3430_EN_DSS1_SHIFT)
365 idlest_bit = OMAP3430ES2_ST_DSS_IDLE;
369 if (system_rev > OMAP3430_REV_ES1_0 &&
370 clk->prcm_mod == OMAP3430ES2_USBHOST_MOD) {
373 * The 120MHz clock apparently has nothing to do with
374 * USBHOST module accessibility
376 if (clk->enable_bit == OMAP3430ES2_EN_USBHOST2_SHIFT)
379 idlest_bit = OMAP3430ES2_ST_USBHOST_IDLE;
384 /* Check if both functional and interface clocks
386 if (!(__raw_readl((void __iomem *)other_reg) & other_bit))
389 idlest_reg = other_reg & ~PRCM_REGTYPE_MASK;
390 idlest_reg |= CM_IDLEST_REGTYPE;
392 omap2_wait_clock_ready((void __iomem *)idlest_reg, idlest_bit,
396 /* Enables clock without considering parent dependencies or use count
397 * REVISIT: Maybe change this to use clk->enable like on omap1?
399 static int _omap2_clk_enable(struct clk *clk)
403 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
407 return clk->enable(clk);
409 if (unlikely(clk->enable_reg == NULL)) {
410 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
412 return 0; /* REVISIT: -EINVAL */
415 v = __raw_readl(clk->enable_reg);
416 if (clk->flags & INVERT_ENABLE)
417 v &= ~(1 << clk->enable_bit);
419 v |= (1 << clk->enable_bit);
420 __raw_writel(v, clk->enable_reg);
423 omap2_clk_wait_ready(clk);
428 /* Disables clock without considering parent dependencies or use count */
429 static void _omap2_clk_disable(struct clk *clk)
433 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
441 if (clk->enable_reg == NULL) {
443 * 'Independent' here refers to a clock which is not
444 * controlled by its parent.
446 printk(KERN_ERR "clock: clk_disable called on independent "
447 "clock %s which has no enable_reg\n", clk->name);
451 v = __raw_readl(clk->enable_reg);
452 if (clk->flags & INVERT_ENABLE)
453 v |= (1 << clk->enable_bit);
455 v &= ~(1 << clk->enable_bit);
456 __raw_writel(v, clk->enable_reg);
460 void omap2_clk_disable(struct clk *clk)
462 if (clk->usecount > 0 && !(--clk->usecount)) {
463 _omap2_clk_disable(clk);
465 omap2_clk_disable(clk->parent);
467 omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
472 int omap2_clk_enable(struct clk *clk)
476 if (clk->usecount++ == 0) {
478 ret = omap2_clk_enable(clk->parent);
486 omap2_clkdm_clk_enable(clk->clkdm.ptr, clk);
488 ret = _omap2_clk_enable(clk);
492 omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
495 omap2_clk_disable(clk->parent);
505 * Used for clocks that are part of CLKSEL_xyz governed clocks.
506 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
508 void omap2_clksel_recalc(struct clk *clk)
512 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
514 div = omap2_clksel_get_divisor(clk);
518 if (clk->rate == (clk->parent->rate / div))
520 clk->rate = clk->parent->rate / div;
522 pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
524 if (clk->flags & RATE_PROPAGATES)
529 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
530 * @clk: OMAP struct clk ptr to inspect
531 * @src_clk: OMAP struct clk ptr of the parent clk to search for
533 * Scan the struct clksel array associated with the clock to find
534 * the element associated with the supplied parent clock address.
535 * Returns a pointer to the struct clksel on success or NULL on error.
537 static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
540 const struct clksel *clks;
545 for (clks = clk->clksel; clks->parent; clks++) {
546 if (clks->parent == src_clk)
547 break; /* Found the requested parent */
551 printk(KERN_ERR "clock: Could not find parent clock %s in "
552 "clksel array of clock %s\n", src_clk->name,
561 * omap2_clksel_round_rate_div - find divisor for the given clock and rate
562 * @clk: OMAP struct clk to use
563 * @target_rate: desired clock rate
564 * @new_div: ptr to where we should store the divisor
566 * Finds 'best' divider value in an array based on the source and target
567 * rates. The divider array must be sorted with smallest divider first.
568 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
569 * they are only settable as part of virtual_prcm set.
571 * Returns the rounded clock rate or returns 0xffffffff on error.
573 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
576 unsigned long test_rate;
577 const struct clksel *clks;
578 const struct clksel_rate *clkr;
581 printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
582 clk->name, target_rate);
586 clks = omap2_get_clksel_by_parent(clk, clk->parent);
590 for (clkr = clks->rates; clkr->div; clkr++) {
591 if (!(clkr->flags & cpu_mask))
595 if (clkr->div <= last_div)
596 printk(KERN_ERR "clock: clksel_rate table not sorted "
597 "for clock %s", clk->name);
599 last_div = clkr->div;
601 test_rate = clk->parent->rate / clkr->div;
603 if (test_rate <= target_rate)
604 break; /* found it */
608 printk(KERN_ERR "clock: Could not find divisor for target "
609 "rate %ld for clock %s parent %s\n", target_rate,
610 clk->name, clk->parent->name);
614 *new_div = clkr->div;
616 printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
617 (clk->parent->rate / clkr->div));
619 return (clk->parent->rate / clkr->div);
623 * omap2_clksel_round_rate - find rounded rate for the given clock and rate
624 * @clk: OMAP struct clk to use
625 * @target_rate: desired clock rate
627 * Compatibility wrapper for OMAP clock framework
628 * Finds best target rate based on the source clock and possible dividers.
629 * rates. The divider array must be sorted with smallest divider first.
630 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
631 * they are only settable as part of virtual_prcm set.
633 * Returns the rounded clock rate or returns 0xffffffff on error.
635 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
639 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
643 /* Given a clock and a rate apply a clock specific rounding function */
644 long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
646 if (clk->round_rate != NULL)
647 return clk->round_rate(clk, rate);
649 if (clk->flags & RATE_FIXED)
650 printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
651 "on fixed-rate clock %s\n", clk->name);
657 * omap2_clksel_to_divisor() - turn clksel field value into integer divider
658 * @clk: OMAP struct clk to use
659 * @field_val: register field value to find
661 * Given a struct clk of a rate-selectable clksel clock, and a register field
662 * value to search for, find the corresponding clock divisor. The register
663 * field value should be pre-masked and shifted down so the LSB is at bit 0
664 * before calling. Returns 0 on error
666 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
668 const struct clksel *clks;
669 const struct clksel_rate *clkr;
671 clks = omap2_get_clksel_by_parent(clk, clk->parent);
675 for (clkr = clks->rates; clkr->div; clkr++) {
676 if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
681 printk(KERN_ERR "clock: Could not find fieldval %d for "
682 "clock %s parent %s\n", field_val, clk->name,
691 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
692 * @clk: OMAP struct clk to use
693 * @div: integer divisor to search for
695 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
696 * find the corresponding register field value. The return register value is
697 * the value before left-shifting. Returns 0xffffffff on error
699 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
701 const struct clksel *clks;
702 const struct clksel_rate *clkr;
704 /* should never happen */
707 clks = omap2_get_clksel_by_parent(clk, clk->parent);
711 for (clkr = clks->rates; clkr->div; clkr++) {
712 if ((clkr->flags & cpu_mask) && (clkr->div == div))
717 printk(KERN_ERR "clock: Could not find divisor %d for "
718 "clock %s parent %s\n", div, clk->name,
727 * omap2_get_clksel - find clksel register addr & field mask for a clk
728 * @clk: struct clk to use
729 * @field_mask: ptr to u32 to store the register field mask
731 * Returns the address of the clksel register upon success or NULL on error.
733 static void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
735 if (unlikely((clk->clksel_reg == NULL) || (clk->clksel_mask == NULL)))
738 *field_mask = clk->clksel_mask;
740 return clk->clksel_reg;
744 * omap2_clksel_get_divisor - get current divider applied to parent clock.
745 * @clk: OMAP struct clk to use.
747 * Returns the integer divisor upon success or 0 on error.
749 u32 omap2_clksel_get_divisor(struct clk *clk)
752 void __iomem *div_addr;
754 div_addr = omap2_get_clksel(clk, &field_mask);
755 if (div_addr == NULL)
758 v = __raw_readl(div_addr) & field_mask;
759 v >>= __ffs(field_mask);
761 return omap2_clksel_to_divisor(clk, v);
764 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
766 u32 field_mask, field_val, validrate, new_div = 0;
767 void __iomem *div_addr;
770 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
771 if (validrate != rate)
774 div_addr = omap2_get_clksel(clk, &field_mask);
775 if (div_addr == NULL)
778 field_val = omap2_divisor_to_clksel(clk, new_div);
782 v = __raw_readl(div_addr);
784 v |= field_val << __ffs(field_mask);
785 __raw_writel(v, div_addr);
789 clk->rate = clk->parent->rate / new_div;
791 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
792 prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
793 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
801 /* Set the clock rate for a clock source */
802 int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
806 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
808 /* CONFIG_PARTICIPANT clocks are changed only in sets via the
809 rate table mechanism, driven by mpu_speed */
810 if (clk->flags & CONFIG_PARTICIPANT)
813 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
814 if (clk->set_rate != NULL)
815 ret = clk->set_rate(clk, rate);
817 if (ret == 0 && (clk->flags & RATE_PROPAGATES))
824 * Converts encoded control register address into a full address
825 * On error, *src_addr will be returned as 0.
827 static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
828 struct clk *src_clk, u32 *field_mask,
829 struct clk *clk, u32 *parent_div)
831 const struct clksel *clks;
832 const struct clksel_rate *clkr;
837 clks = omap2_get_clksel_by_parent(clk, src_clk);
841 for (clkr = clks->rates; clkr->div; clkr++) {
842 if (clkr->flags & (cpu_mask | DEFAULT_RATE))
843 break; /* Found the default rate for this platform */
847 printk(KERN_ERR "clock: Could not find default rate for "
848 "clock %s parent %s\n", clk->name,
849 src_clk->parent->name);
853 /* Should never happen. Add a clksel mask to the struct clk. */
854 WARN_ON(clk->clksel_mask == 0);
856 *field_mask = clk->clksel_mask;
857 *src_addr = clk->clksel_reg;
858 *parent_div = clkr->div;
863 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
865 void __iomem *src_addr;
866 u32 field_val, field_mask, v, parent_div;
868 if (clk->flags & CONFIG_PARTICIPANT)
874 field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
875 &field_mask, clk, &parent_div);
876 if (src_addr == NULL)
879 if (clk->usecount > 0)
880 _omap2_clk_disable(clk);
882 /* Set new source value (previous dividers if any in effect) */
883 v = __raw_readl(src_addr) & ~field_mask;
884 v |= (field_val << __ffs(field_mask));
885 __raw_writel(v, src_addr);
888 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
889 prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
890 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
894 if (clk->usecount > 0)
895 _omap2_clk_enable(clk);
897 clk->parent = new_parent;
899 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
900 clk->rate = new_parent->rate;
903 clk->rate /= parent_div;
905 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
906 clk->name, clk->parent->name, clk->rate);
908 if (clk->flags & RATE_PROPAGATES)
914 /* DPLL rate rounding code */
917 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
918 * @clk: struct clk * of the DPLL
919 * @tolerance: maximum rate error tolerance
921 * Set the maximum DPLL rate error tolerance for the rate rounding
922 * algorithm. The rate tolerance is an attempt to balance DPLL power
923 * saving (the least divider value "n") vs. rate fidelity (the least
924 * difference between the desired DPLL target rate and the rounded
925 * rate out of the algorithm). So, increasing the tolerance is likely
926 * to decrease DPLL power consumption and increase DPLL rate error.
927 * Returns -EINVAL if provided a null clock ptr or a clk that is not a
928 * DPLL; or 0 upon success.
930 int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
932 if (!clk || !clk->dpll_data)
935 clk->dpll_data->rate_tolerance = tolerance;
940 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
941 unsigned int m, unsigned int n)
943 unsigned long long num;
945 num = (unsigned long long)parent_rate * m;
951 * _dpll_test_mult - test a DPLL multiplier value
952 * @m: pointer to the DPLL m (multiplier) value under test
953 * @n: current DPLL n (divider) value under test
954 * @new_rate: pointer to storage for the resulting rounded rate
955 * @target_rate: the desired DPLL rate
956 * @parent_rate: the DPLL's parent clock rate
958 * This code tests a DPLL multiplier value, ensuring that the
959 * resulting rate will not be higher than the target_rate, and that
960 * the multiplier value itself is valid for the DPLL. Initially, the
961 * integer pointed to by the m argument should be prescaled by
962 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
963 * a non-scaled m upon return. This non-scaled m will result in a
964 * new_rate as close as possible to target_rate (but not greater than
965 * target_rate) given the current (parent_rate, n, prescaled m)
966 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
967 * non-scaled m attempted to underflow, which can allow the calling
968 * function to bail out early; or 0 upon success.
970 static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
971 unsigned long target_rate,
972 unsigned long parent_rate)
974 int flags = 0, carry = 0;
976 /* Unscale m and round if necessary */
977 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
979 *m = (*m / DPLL_SCALE_FACTOR) + carry;
982 * The new rate must be <= the target rate to avoid programming
983 * a rate that is impossible for the hardware to handle
985 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
986 if (*new_rate > target_rate) {
991 /* Guard against m underflow */
992 if (*m < DPLL_MIN_MULTIPLIER) {
993 *m = DPLL_MIN_MULTIPLIER;
995 flags = DPLL_MULT_UNDERFLOW;
999 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
1005 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
1006 * @clk: struct clk * for a DPLL
1007 * @target_rate: desired DPLL clock rate
1009 * Given a DPLL, a desired target rate, and a rate tolerance, round
1010 * the target rate to a possible, programmable rate for this DPLL.
1011 * Rate tolerance is assumed to be set by the caller before this
1012 * function is called. Attempts to select the minimum possible n
1013 * within the tolerance to reduce power consumption. Stores the
1014 * computed (m, n) in the DPLL's dpll_data structure so set_rate()
1015 * will not need to call this (expensive) function again. Returns ~0
1016 * if the target rate cannot be rounded, either because the rate is
1017 * too low or because the rate tolerance is set too tightly; or the
1018 * rounded rate upon success.
1020 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
1022 int m, n, r, e, scaled_max_m;
1023 unsigned long scaled_rt_rp, new_rate;
1024 int min_e = -1, min_e_m = -1, min_e_n = -1;
1026 if (!clk || !clk->dpll_data)
1029 pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
1030 "%ld\n", clk->name, target_rate);
1032 scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR);
1033 scaled_max_m = clk->dpll_data->max_multiplier * DPLL_SCALE_FACTOR;
1035 clk->dpll_data->last_rounded_rate = 0;
1037 for (n = clk->dpll_data->max_divider; n >= DPLL_MIN_DIVIDER; n--) {
1039 /* Compute the scaled DPLL multiplier, based on the divider */
1040 m = scaled_rt_rp * n;
1043 * Since we're counting n down, a m overflow means we can
1044 * can immediately skip to the next n
1046 if (m > scaled_max_m)
1049 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
1052 e = target_rate - new_rate;
1053 pr_debug("clock: n = %d: m = %d: rate error is %d "
1054 "(new_rate = %ld)\n", n, m, e, new_rate);
1057 min_e >= (int)(abs(e) - clk->dpll_data->rate_tolerance)) {
1062 pr_debug("clock: found new least error %d\n", min_e);
1066 * Since we're counting n down, a m underflow means we
1067 * can bail out completely (since as n decreases in
1068 * the next iteration, there's no way that m can
1069 * increase beyond the current m)
1071 if (r & DPLL_MULT_UNDERFLOW)
1076 pr_debug("clock: error: target rate or tolerance too low\n");
1080 clk->dpll_data->last_rounded_m = min_e_m;
1081 clk->dpll_data->last_rounded_n = min_e_n;
1082 clk->dpll_data->last_rounded_rate =
1083 _dpll_compute_new_rate(clk->parent->rate, min_e_m, min_e_n);
1085 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
1086 min_e, min_e_m, min_e_n);
1087 pr_debug("clock: final rate: %ld (target rate: %ld)\n",
1088 clk->dpll_data->last_rounded_rate, target_rate);
1090 return clk->dpll_data->last_rounded_rate;
1093 /*-------------------------------------------------------------------------
1094 * Omap2 clock reset and init functions
1095 *-------------------------------------------------------------------------*/
1097 #ifdef CONFIG_OMAP_RESET_CLOCKS
1098 void omap2_clk_disable_unused(struct clk *clk)
1102 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
1104 regval32 = __raw_readl(clk->enable_reg);
1105 if ((regval32 & (1 << clk->enable_bit)) == v)
1108 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
1109 _omap2_clk_disable(clk);