2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/list.h>
21 #include <linux/errno.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
24 #include <linux/bitops.h>
27 #include <mach/clock.h>
28 #include <mach/clockdomain.h>
29 #include <mach/sram.h>
31 #include <mach/prcm.h>
32 #include <asm/div64.h>
34 #include <mach/sdrc.h>
38 #include "prm-regbits-24xx.h"
40 #include "cm-regbits-24xx.h"
41 #include "cm-regbits-34xx.h"
43 #define MAX_CLOCK_ENABLE_WAIT 100000
45 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
46 #define DPLL_MIN_MULTIPLIER 1
47 #define DPLL_MIN_DIVIDER 1
49 /* Possible error results from _dpll_test_mult */
50 #define DPLL_MULT_UNDERFLOW (1 << 0)
53 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
54 * The higher the scale factor, the greater the risk of arithmetic overflow,
55 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
56 * must be a power of DPLL_SCALE_BASE.
58 #define DPLL_SCALE_FACTOR 64
59 #define DPLL_SCALE_BASE 2
60 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
61 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
63 /* Some OMAP2xxx CM_CLKSEL_PLL.ST_CORE_CLK bits - for omap2_get_dpll_rate() */
64 #define ST_CORE_CLK_REF 0x1
65 #define ST_CORE_CLK_32K 0x3
69 /*-------------------------------------------------------------------------
70 * OMAP2/3 specific clock functions
71 *-------------------------------------------------------------------------*/
74 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
75 * @clk: OMAP clock struct ptr to use
77 * Convert a clockdomain name stored in a struct clk 'clk' into a
78 * clockdomain pointer, and save it into the struct clk. Intended to be
79 * called during clk_register(). No return value.
81 void omap2_init_clk_clkdm(struct clk *clk)
83 struct clockdomain *clkdm;
85 if (!clk->clkdm.name) {
86 pr_err("clock: %s: missing clockdomain", clk->name);
90 clkdm = clkdm_lookup(clk->clkdm.name);
92 pr_debug("clock: associated clk %s to clkdm %s\n",
93 clk->name, clk->clkdm.name);
94 clk->clkdm.ptr = clkdm;
96 pr_err("clock: %s: could not associate to clkdm %s\n",
97 clk->name, clk->clkdm.name);
102 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
103 * @clk: OMAP clock struct ptr to use
105 * Given a pointer to a source-selectable struct clk, read the hardware
106 * register and determine what its parent is currently set to. Update the
107 * clk->parent field with the appropriate clk ptr.
109 void omap2_init_clksel_parent(struct clk *clk)
111 const struct clksel *clks;
112 const struct clksel_rate *clkr;
118 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
119 r >>= __ffs(clk->clksel_mask);
121 for (clks = clk->clksel; clks->parent && !found; clks++) {
122 for (clkr = clks->rates; clkr->div && !found; clkr++) {
123 if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
124 if (clk->parent != clks->parent) {
125 pr_debug("clock: inited %s parent "
127 clk->name, clks->parent->name,
129 clk->parent->name : "NULL"));
130 clk->parent = clks->parent;
138 printk(KERN_ERR "clock: init parent: could not find "
139 "regval %0x for clock %s\n", r, clk->name);
145 * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
146 * @clk: struct clk * of a DPLL
148 * DPLLs can be locked or bypassed - basically, enabled or disabled.
149 * When locked, the DPLL output depends on the M and N values. When
150 * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
151 * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
152 * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
153 * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
154 * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
155 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
156 * if the clock @clk is not a DPLL.
158 u32 omap2_get_dpll_rate(struct clk *clk)
161 u32 dpll_mult, dpll_div, v;
162 struct dpll_data *dd;
168 /* Return bypass rate if DPLL is bypassed */
169 v = __raw_readl(dd->idlest_reg) & dd->idlest_mask;
170 v >>= __ffs(dd->idlest_mask);
171 if (cpu_is_omap24xx()) {
173 if (v == ST_CORE_CLK_REF)
174 return clk->parent->rate; /* sys_clk */
175 else if (v == ST_CORE_CLK_32K)
178 } else if (cpu_is_omap34xx()) {
181 return dd->bypass_clk->rate;
185 v = __raw_readl(dd->mult_div1_reg);
186 dpll_mult = v & dd->mult_mask;
187 dpll_mult >>= __ffs(dd->mult_mask);
188 dpll_div = v & dd->div1_mask;
189 dpll_div >>= __ffs(dd->div1_mask);
191 dpll_clk = (long long)clk->parent->rate * dpll_mult;
192 do_div(dpll_clk, dpll_div + 1);
198 * Used for clocks that have the same value as the parent clock,
199 * divided by some factor
201 void omap2_fixed_divisor_recalc(struct clk *clk)
203 WARN_ON(!clk->fixed_div);
205 clk->rate = clk->parent->rate / clk->fixed_div;
207 if (clk->flags & RATE_PROPAGATES)
212 * omap2_wait_clock_ready - wait for clock to enable
213 * @reg: physical address of clock IDLEST register
214 * @mask: value to mask against to determine if the clock is active
215 * @name: name of the clock (for printk)
217 * Returns 1 if the clock enabled in time, or 0 if it failed to enable
218 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
220 int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
226 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
227 * 34xx reverses this, just to keep us on our toes
229 if (cpu_mask & (RATE_IN_242X | RATE_IN_243X))
231 else if (cpu_mask & RATE_IN_343X)
235 while (((__raw_readl(reg) & mask) != ena) &&
236 (i++ < MAX_CLOCK_ENABLE_WAIT)) {
240 if (i < MAX_CLOCK_ENABLE_WAIT)
241 pr_debug("Clock %s stable after %d loops\n", name, i);
243 printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
244 name, MAX_CLOCK_ENABLE_WAIT);
247 return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
252 * Note: We don't need special code here for INVERT_ENABLE
253 * for the time being since INVERT_ENABLE only applies to clocks enabled by
256 * REVISIT: This code is ugly and does not belong here.
258 static void omap2_clk_wait_ready(struct clk *clk)
260 u32 other_bit, idlest_bit;
261 unsigned long reg, other_reg, idlest_reg, prcm_mod, prcm_regid;
263 reg = (unsigned long)clk->enable_reg;
264 prcm_mod = reg & ~0xff;
265 prcm_regid = reg & 0xff;
267 if (prcm_regid >= CM_FCLKEN1 && prcm_regid <= OMAP24XX_CM_FCLKEN2)
268 other_reg = ((reg & ~0xf0) | 0x10); /* CM_ICLKEN* */
269 else if (prcm_regid >= CM_ICLKEN1 && prcm_regid <= OMAP24XX_CM_ICLKEN4)
270 other_reg = ((reg & ~0xf0) | 0x00); /* CM_FCLKEN* */
274 /* Covers most of the cases - a few exceptions are below */
275 other_bit = 1 << clk->enable_bit;
276 idlest_bit = other_bit;
278 /* 24xx: DSS and CAM have no idlest bits for their target agents */
279 if (cpu_is_omap24xx() &&
280 (prcm_mod == OMAP2420_CM_REGADDR(CORE_MOD, 0) ||
281 prcm_mod == OMAP2430_CM_REGADDR(CORE_MOD, 0)) &&
282 (reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
284 if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
285 clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
286 clk->enable_bit == OMAP24XX_EN_CAM_SHIFT)
291 /* REVISIT: What are the appropriate exclusions for 34XX? */
292 if (cpu_is_omap34xx()) {
295 if (prcm_mod == OMAP34XX_CM_REGADDR(CORE_MOD, 0) &&
297 clk->enable_bit == OMAP3430_EN_SSI_SHIFT) {
299 if (system_rev == OMAP3430_REV_ES1_0)
302 idlest_bit = OMAP3430ES2_ST_SSI_IDLE;
306 if (prcm_mod == OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0)) {
308 /* 3430ES1 DSS has no target idlest bits */
309 if (system_rev == OMAP3430_REV_ES1_0)
313 * For 3430ES2+ DSS, only wait once (dss1_alwon_fclk,
314 * dss_l3_iclk, dss_l4_iclk) are enabled
316 if (clk->enable_bit != OMAP3430_EN_DSS1_SHIFT)
319 idlest_bit = OMAP3430ES2_ST_DSS_IDLE;
323 if (system_rev > OMAP3430_REV_ES1_0 &&
324 prcm_mod == OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, 0)) {
327 * The 120MHz clock apparently has nothing to do with
328 * USBHOST module accessibility
330 if (clk->enable_bit == OMAP3430ES2_EN_USBHOST2_SHIFT)
333 idlest_bit = OMAP3430ES2_ST_USBHOST_IDLE;
338 /* Check if both functional and interface clocks
340 if (!(__raw_readl((void __iomem *)other_reg) & other_bit))
343 idlest_reg = ((other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
345 omap2_wait_clock_ready((void __iomem *)idlest_reg, idlest_bit,
349 /* Enables clock without considering parent dependencies or use count
350 * REVISIT: Maybe change this to use clk->enable like on omap1?
352 static int _omap2_clk_enable(struct clk *clk)
356 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
360 return clk->enable(clk);
362 if (unlikely(clk->enable_reg == NULL)) {
363 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
365 return 0; /* REVISIT: -EINVAL */
368 regval32 = __raw_readl(clk->enable_reg);
369 if (clk->flags & INVERT_ENABLE)
370 regval32 &= ~(1 << clk->enable_bit);
372 regval32 |= (1 << clk->enable_bit);
373 __raw_writel(regval32, clk->enable_reg);
376 omap2_clk_wait_ready(clk);
381 /* Disables clock without considering parent dependencies or use count */
382 static void _omap2_clk_disable(struct clk *clk)
386 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
394 if (clk->enable_reg == NULL) {
396 * 'Independent' here refers to a clock which is not
397 * controlled by its parent.
399 printk(KERN_ERR "clock: clk_disable called on independent "
400 "clock %s which has no enable_reg\n", clk->name);
404 regval32 = __raw_readl(clk->enable_reg);
405 if (clk->flags & INVERT_ENABLE)
406 regval32 |= (1 << clk->enable_bit);
408 regval32 &= ~(1 << clk->enable_bit);
409 __raw_writel(regval32, clk->enable_reg);
413 void omap2_clk_disable(struct clk *clk)
415 if (clk->usecount > 0 && !(--clk->usecount)) {
416 _omap2_clk_disable(clk);
418 omap2_clk_disable(clk->parent);
420 omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
425 int omap2_clk_enable(struct clk *clk)
429 if (clk->usecount++ == 0) {
431 ret = omap2_clk_enable(clk->parent);
439 omap2_clkdm_clk_enable(clk->clkdm.ptr, clk);
441 ret = _omap2_clk_enable(clk);
445 omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
448 omap2_clk_disable(clk->parent);
458 * Used for clocks that are part of CLKSEL_xyz governed clocks.
459 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
461 void omap2_clksel_recalc(struct clk *clk)
465 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
467 div = omap2_clksel_get_divisor(clk);
471 if (clk->rate == (clk->parent->rate / div))
473 clk->rate = clk->parent->rate / div;
475 pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
477 if (clk->flags & RATE_PROPAGATES)
482 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
483 * @clk: OMAP struct clk ptr to inspect
484 * @src_clk: OMAP struct clk ptr of the parent clk to search for
486 * Scan the struct clksel array associated with the clock to find
487 * the element associated with the supplied parent clock address.
488 * Returns a pointer to the struct clksel on success or NULL on error.
490 static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
493 const struct clksel *clks;
498 for (clks = clk->clksel; clks->parent; clks++) {
499 if (clks->parent == src_clk)
500 break; /* Found the requested parent */
504 printk(KERN_ERR "clock: Could not find parent clock %s in "
505 "clksel array of clock %s\n", src_clk->name,
514 * omap2_clksel_round_rate_div - find divisor for the given clock and rate
515 * @clk: OMAP struct clk to use
516 * @target_rate: desired clock rate
517 * @new_div: ptr to where we should store the divisor
519 * Finds 'best' divider value in an array based on the source and target
520 * rates. The divider array must be sorted with smallest divider first.
521 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
522 * they are only settable as part of virtual_prcm set.
524 * Returns the rounded clock rate or returns 0xffffffff on error.
526 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
529 unsigned long test_rate;
530 const struct clksel *clks;
531 const struct clksel_rate *clkr;
534 printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
535 clk->name, target_rate);
539 clks = omap2_get_clksel_by_parent(clk, clk->parent);
543 for (clkr = clks->rates; clkr->div; clkr++) {
544 if (!(clkr->flags & cpu_mask))
548 if (clkr->div <= last_div)
549 printk(KERN_ERR "clock: clksel_rate table not sorted "
550 "for clock %s", clk->name);
552 last_div = clkr->div;
554 test_rate = clk->parent->rate / clkr->div;
556 if (test_rate <= target_rate)
557 break; /* found it */
561 printk(KERN_ERR "clock: Could not find divisor for target "
562 "rate %ld for clock %s parent %s\n", target_rate,
563 clk->name, clk->parent->name);
567 *new_div = clkr->div;
569 printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
570 (clk->parent->rate / clkr->div));
572 return (clk->parent->rate / clkr->div);
576 * omap2_clksel_round_rate - find rounded rate for the given clock and rate
577 * @clk: OMAP struct clk to use
578 * @target_rate: desired clock rate
580 * Compatibility wrapper for OMAP clock framework
581 * Finds best target rate based on the source clock and possible dividers.
582 * rates. The divider array must be sorted with smallest divider first.
583 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
584 * they are only settable as part of virtual_prcm set.
586 * Returns the rounded clock rate or returns 0xffffffff on error.
588 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
592 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
596 /* Given a clock and a rate apply a clock specific rounding function */
597 long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
599 if (clk->round_rate != NULL)
600 return clk->round_rate(clk, rate);
602 if (clk->flags & RATE_FIXED)
603 printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
604 "on fixed-rate clock %s\n", clk->name);
610 * omap2_clksel_to_divisor() - turn clksel field value into integer divider
611 * @clk: OMAP struct clk to use
612 * @field_val: register field value to find
614 * Given a struct clk of a rate-selectable clksel clock, and a register field
615 * value to search for, find the corresponding clock divisor. The register
616 * field value should be pre-masked and shifted down so the LSB is at bit 0
617 * before calling. Returns 0 on error
619 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
621 const struct clksel *clks;
622 const struct clksel_rate *clkr;
624 clks = omap2_get_clksel_by_parent(clk, clk->parent);
628 for (clkr = clks->rates; clkr->div; clkr++) {
629 if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
634 printk(KERN_ERR "clock: Could not find fieldval %d for "
635 "clock %s parent %s\n", field_val, clk->name,
644 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
645 * @clk: OMAP struct clk to use
646 * @div: integer divisor to search for
648 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
649 * find the corresponding register field value. The return register value is
650 * the value before left-shifting. Returns 0xffffffff on error
652 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
654 const struct clksel *clks;
655 const struct clksel_rate *clkr;
657 /* should never happen */
660 clks = omap2_get_clksel_by_parent(clk, clk->parent);
664 for (clkr = clks->rates; clkr->div; clkr++) {
665 if ((clkr->flags & cpu_mask) && (clkr->div == div))
670 printk(KERN_ERR "clock: Could not find divisor %d for "
671 "clock %s parent %s\n", div, clk->name,
680 * omap2_get_clksel - find clksel register addr & field mask for a clk
681 * @clk: struct clk to use
682 * @field_mask: ptr to u32 to store the register field mask
684 * Returns the address of the clksel register upon success or NULL on error.
686 static void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
688 if (unlikely((clk->clksel_reg == NULL) || (clk->clksel_mask == NULL)))
691 *field_mask = clk->clksel_mask;
693 return clk->clksel_reg;
697 * omap2_clksel_get_divisor - get current divider applied to parent clock.
698 * @clk: OMAP struct clk to use.
700 * Returns the integer divisor upon success or 0 on error.
702 u32 omap2_clksel_get_divisor(struct clk *clk)
704 u32 field_mask, field_val;
705 void __iomem *div_addr;
707 div_addr = omap2_get_clksel(clk, &field_mask);
708 if (div_addr == NULL)
711 field_val = __raw_readl(div_addr) & field_mask;
712 field_val >>= __ffs(field_mask);
714 return omap2_clksel_to_divisor(clk, field_val);
717 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
719 u32 field_mask, field_val, validrate, new_div = 0;
720 void __iomem *div_addr;
723 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
724 if (validrate != rate)
727 div_addr = omap2_get_clksel(clk, &field_mask);
728 if (div_addr == NULL)
731 field_val = omap2_divisor_to_clksel(clk, new_div);
735 v = __raw_readl(div_addr);
737 v |= field_val << __ffs(field_mask);
738 __raw_writel(v, div_addr);
742 clk->rate = clk->parent->rate / new_div;
744 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
745 prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
746 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
754 /* Set the clock rate for a clock source */
755 int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
759 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
761 /* CONFIG_PARTICIPANT clocks are changed only in sets via the
762 rate table mechanism, driven by mpu_speed */
763 if (clk->flags & CONFIG_PARTICIPANT)
766 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
767 if (clk->set_rate != NULL)
768 ret = clk->set_rate(clk, rate);
770 if (ret == 0 && (clk->flags & RATE_PROPAGATES))
777 * Converts encoded control register address into a full address
778 * On error, *src_addr will be returned as 0.
780 static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
781 struct clk *src_clk, u32 *field_mask,
782 struct clk *clk, u32 *parent_div)
784 const struct clksel *clks;
785 const struct clksel_rate *clkr;
790 clks = omap2_get_clksel_by_parent(clk, src_clk);
794 for (clkr = clks->rates; clkr->div; clkr++) {
795 if (clkr->flags & (cpu_mask | DEFAULT_RATE))
796 break; /* Found the default rate for this platform */
800 printk(KERN_ERR "clock: Could not find default rate for "
801 "clock %s parent %s\n", clk->name,
802 src_clk->parent->name);
806 /* Should never happen. Add a clksel mask to the struct clk. */
807 WARN_ON(clk->clksel_mask == 0);
809 *field_mask = clk->clksel_mask;
810 *src_addr = clk->clksel_reg;
811 *parent_div = clkr->div;
816 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
818 void __iomem *src_addr;
819 u32 field_val, field_mask, reg_val, parent_div;
821 if (clk->flags & CONFIG_PARTICIPANT)
827 field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
828 &field_mask, clk, &parent_div);
829 if (src_addr == NULL)
832 if (clk->usecount > 0)
833 _omap2_clk_disable(clk);
835 /* Set new source value (previous dividers if any in effect) */
836 reg_val = __raw_readl(src_addr) & ~field_mask;
837 reg_val |= (field_val << __ffs(field_mask));
838 __raw_writel(reg_val, src_addr);
841 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
842 prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
843 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
847 if (clk->usecount > 0)
848 _omap2_clk_enable(clk);
850 clk->parent = new_parent;
852 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
853 clk->rate = new_parent->rate;
856 clk->rate /= parent_div;
858 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
859 clk->name, clk->parent->name, clk->rate);
861 if (clk->flags & RATE_PROPAGATES)
867 /* DPLL rate rounding code */
870 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
871 * @clk: struct clk * of the DPLL
872 * @tolerance: maximum rate error tolerance
874 * Set the maximum DPLL rate error tolerance for the rate rounding
875 * algorithm. The rate tolerance is an attempt to balance DPLL power
876 * saving (the least divider value "n") vs. rate fidelity (the least
877 * difference between the desired DPLL target rate and the rounded
878 * rate out of the algorithm). So, increasing the tolerance is likely
879 * to decrease DPLL power consumption and increase DPLL rate error.
880 * Returns -EINVAL if provided a null clock ptr or a clk that is not a
881 * DPLL; or 0 upon success.
883 int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
885 if (!clk || !clk->dpll_data)
888 clk->dpll_data->rate_tolerance = tolerance;
893 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
894 unsigned int m, unsigned int n)
896 unsigned long long num;
898 num = (unsigned long long)parent_rate * m;
904 * _dpll_test_mult - test a DPLL multiplier value
905 * @m: pointer to the DPLL m (multiplier) value under test
906 * @n: current DPLL n (divider) value under test
907 * @new_rate: pointer to storage for the resulting rounded rate
908 * @target_rate: the desired DPLL rate
909 * @parent_rate: the DPLL's parent clock rate
911 * This code tests a DPLL multiplier value, ensuring that the
912 * resulting rate will not be higher than the target_rate, and that
913 * the multiplier value itself is valid for the DPLL. Initially, the
914 * integer pointed to by the m argument should be prescaled by
915 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
916 * a non-scaled m upon return. This non-scaled m will result in a
917 * new_rate as close as possible to target_rate (but not greater than
918 * target_rate) given the current (parent_rate, n, prescaled m)
919 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
920 * non-scaled m attempted to underflow, which can allow the calling
921 * function to bail out early; or 0 upon success.
923 static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
924 unsigned long target_rate,
925 unsigned long parent_rate)
927 int flags = 0, carry = 0;
929 /* Unscale m and round if necessary */
930 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
932 *m = (*m / DPLL_SCALE_FACTOR) + carry;
935 * The new rate must be <= the target rate to avoid programming
936 * a rate that is impossible for the hardware to handle
938 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
939 if (*new_rate > target_rate) {
944 /* Guard against m underflow */
945 if (*m < DPLL_MIN_MULTIPLIER) {
946 *m = DPLL_MIN_MULTIPLIER;
948 flags = DPLL_MULT_UNDERFLOW;
952 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
958 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
959 * @clk: struct clk * for a DPLL
960 * @target_rate: desired DPLL clock rate
962 * Given a DPLL, a desired target rate, and a rate tolerance, round
963 * the target rate to a possible, programmable rate for this DPLL.
964 * Rate tolerance is assumed to be set by the caller before this
965 * function is called. Attempts to select the minimum possible n
966 * within the tolerance to reduce power consumption. Stores the
967 * computed (m, n) in the DPLL's dpll_data structure so set_rate()
968 * will not need to call this (expensive) function again. Returns ~0
969 * if the target rate cannot be rounded, either because the rate is
970 * too low or because the rate tolerance is set too tightly; or the
971 * rounded rate upon success.
973 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
975 int m, n, r, e, scaled_max_m;
976 unsigned long scaled_rt_rp, new_rate;
977 int min_e = -1, min_e_m = -1, min_e_n = -1;
979 if (!clk || !clk->dpll_data)
982 pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
983 "%ld\n", clk->name, target_rate);
985 scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR);
986 scaled_max_m = clk->dpll_data->max_multiplier * DPLL_SCALE_FACTOR;
988 clk->dpll_data->last_rounded_rate = 0;
990 for (n = clk->dpll_data->max_divider; n >= DPLL_MIN_DIVIDER; n--) {
992 /* Compute the scaled DPLL multiplier, based on the divider */
993 m = scaled_rt_rp * n;
996 * Since we're counting n down, a m overflow means we can
997 * can immediately skip to the next n
999 if (m > scaled_max_m)
1002 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
1005 e = target_rate - new_rate;
1006 pr_debug("clock: n = %d: m = %d: rate error is %d "
1007 "(new_rate = %ld)\n", n, m, e, new_rate);
1010 min_e >= (int)(abs(e) - clk->dpll_data->rate_tolerance)) {
1015 pr_debug("clock: found new least error %d\n", min_e);
1019 * Since we're counting n down, a m underflow means we
1020 * can bail out completely (since as n decreases in
1021 * the next iteration, there's no way that m can
1022 * increase beyond the current m)
1024 if (r & DPLL_MULT_UNDERFLOW)
1029 pr_debug("clock: error: target rate or tolerance too low\n");
1033 clk->dpll_data->last_rounded_m = min_e_m;
1034 clk->dpll_data->last_rounded_n = min_e_n;
1035 clk->dpll_data->last_rounded_rate =
1036 _dpll_compute_new_rate(clk->parent->rate, min_e_m, min_e_n);
1038 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
1039 min_e, min_e_m, min_e_n);
1040 pr_debug("clock: final rate: %ld (target rate: %ld)\n",
1041 clk->dpll_data->last_rounded_rate, target_rate);
1043 return clk->dpll_data->last_rounded_rate;
1046 /*-------------------------------------------------------------------------
1047 * Omap2 clock reset and init functions
1048 *-------------------------------------------------------------------------*/
1050 #ifdef CONFIG_OMAP_RESET_CLOCKS
1051 void omap2_clk_disable_unused(struct clk *clk)
1055 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
1057 regval32 = __raw_readl(clk->enable_reg);
1058 if ((regval32 & (1 << clk->enable_bit)) == v)
1061 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
1062 _omap2_clk_disable(clk);