2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/list.h>
21 #include <linux/errno.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
24 #include <linux/bitops.h>
27 #include <asm/arch/clock.h>
28 #include <asm/arch/clockdomain.h>
29 #include <asm/arch/sram.h>
30 #include <asm/arch/cpu.h>
31 #include <asm/arch/prcm.h>
32 #include <asm/div64.h>
34 #include <asm/arch/sdrc.h>
38 #include "prm-regbits-24xx.h"
40 #include "cm-regbits-24xx.h"
41 #include "cm-regbits-34xx.h"
43 #define MAX_CLOCK_ENABLE_WAIT 100000
45 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
46 #define DPLL_MIN_MULTIPLIER 1
47 #define DPLL_MIN_DIVIDER 1
49 /* Possible error results from _dpll_test_mult */
50 #define DPLL_MULT_UNDERFLOW (1 << 0)
53 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
54 * The higher the scale factor, the greater the risk of arithmetic overflow,
55 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
56 * must be a power of DPLL_SCALE_BASE.
58 #define DPLL_SCALE_FACTOR 64
59 #define DPLL_SCALE_BASE 2
60 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
61 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
65 /*-------------------------------------------------------------------------
66 * OMAP2/3 specific clock functions
67 *-------------------------------------------------------------------------*/
70 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
71 * @clk: OMAP clock struct ptr to use
73 * Convert a clockdomain name stored in a struct clk 'clk' into a
74 * clockdomain pointer, and save it into the struct clk. Intended to be
75 * called during clk_register(). No return value.
77 void omap2_init_clk_clkdm(struct clk *clk)
79 struct clockdomain *clkdm;
84 clkdm = clkdm_lookup(clk->clkdm.name);
86 pr_debug("clock: associated clk %s to clkdm %s\n",
87 clk->name, clk->clkdm.name);
88 clk->clkdm.ptr = clkdm;
90 pr_debug("clock: could not associate clk %s to "
91 "clkdm %s\n", clk->name, clk->clkdm.name);
96 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
97 * @clk: OMAP clock struct ptr to use
99 * Given a pointer to a source-selectable struct clk, read the hardware
100 * register and determine what its parent is currently set to. Update the
101 * clk->parent field with the appropriate clk ptr.
103 void omap2_init_clksel_parent(struct clk *clk)
105 const struct clksel *clks;
106 const struct clksel_rate *clkr;
112 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
113 r >>= __ffs(clk->clksel_mask);
115 for (clks = clk->clksel; clks->parent && !found; clks++) {
116 for (clkr = clks->rates; clkr->div && !found; clkr++) {
117 if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
118 if (clk->parent != clks->parent) {
119 pr_debug("clock: inited %s parent "
121 clk->name, clks->parent->name,
123 clk->parent->name : "NULL"));
124 clk->parent = clks->parent;
132 printk(KERN_ERR "clock: init parent: could not find "
133 "regval %0x for clock %s\n", r, clk->name);
138 /* Returns the DPLL rate */
139 u32 omap2_get_dpll_rate(struct clk *clk)
142 u32 dpll_mult, dpll_div, dpll;
143 struct dpll_data *dd;
146 /* REVISIT: What do we return on error? */
150 dpll = __raw_readl(dd->mult_div1_reg);
151 dpll_mult = dpll & dd->mult_mask;
152 dpll_mult >>= __ffs(dd->mult_mask);
153 dpll_div = dpll & dd->div1_mask;
154 dpll_div >>= __ffs(dd->div1_mask);
156 dpll_clk = (long long)clk->parent->rate * dpll_mult;
157 do_div(dpll_clk, dpll_div + 1);
163 * Used for clocks that have the same value as the parent clock,
164 * divided by some factor
166 void omap2_fixed_divisor_recalc(struct clk *clk)
168 WARN_ON(!clk->fixed_div);
170 clk->rate = clk->parent->rate / clk->fixed_div;
172 if (clk->flags & RATE_PROPAGATES)
177 * omap2_wait_clock_ready - wait for clock to enable
178 * @reg: physical address of clock IDLEST register
179 * @mask: value to mask against to determine if the clock is active
180 * @name: name of the clock (for printk)
182 * Returns 1 if the clock enabled in time, or 0 if it failed to enable
183 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
185 int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
191 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
192 * 34xx reverses this, just to keep us on our toes
194 if (cpu_mask & (RATE_IN_242X | RATE_IN_243X))
196 else if (cpu_mask & RATE_IN_343X)
200 while (((__raw_readl(reg) & mask) != ena) &&
201 (i++ < MAX_CLOCK_ENABLE_WAIT)) {
205 if (i < MAX_CLOCK_ENABLE_WAIT)
206 pr_debug("Clock %s stable after %d loops\n", name, i);
208 printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
209 name, MAX_CLOCK_ENABLE_WAIT);
212 return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
217 * Note: We don't need special code here for INVERT_ENABLE
218 * for the time being since INVERT_ENABLE only applies to clocks enabled by
221 * REVISIT: This code is ugly and does not belong here.
223 static void omap2_clk_wait_ready(struct clk *clk)
225 u32 other_bit, idlest_bit;
226 unsigned long reg, other_reg, idlest_reg, prcm_mod, prcm_regid;
228 reg = (unsigned long)clk->enable_reg;
229 prcm_mod = reg & ~0xff;
230 prcm_regid = reg & 0xff;
232 if (prcm_regid >= CM_FCLKEN1 && prcm_regid <= OMAP24XX_CM_FCLKEN2)
233 other_reg = ((reg & ~0xf0) | 0x10); /* CM_ICLKEN* */
234 else if (prcm_regid >= CM_ICLKEN1 && prcm_regid <= OMAP24XX_CM_ICLKEN4)
235 other_reg = ((reg & ~0xf0) | 0x00); /* CM_FCLKEN* */
239 /* Covers most of the cases - a few exceptions are below */
240 other_bit = 1 << clk->enable_bit;
241 idlest_bit = other_bit;
243 /* 24xx: DSS and CAM have no idlest bits for their target agents */
244 if (cpu_is_omap24xx() &&
245 (prcm_mod == OMAP2420_CM_REGADDR(CORE_MOD, 0) ||
246 prcm_mod == OMAP2430_CM_REGADDR(CORE_MOD, 0)) &&
247 (reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
249 if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
250 clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
251 clk->enable_bit == OMAP24XX_EN_CAM_SHIFT)
256 /* REVISIT: What are the appropriate exclusions for 34XX? */
257 if (cpu_is_omap34xx()) {
260 if (prcm_mod == OMAP34XX_CM_REGADDR(CORE_MOD, 0) &&
262 clk->enable_bit == OMAP3430_EN_SSI_SHIFT) {
264 if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0))
267 idlest_bit = OMAP3430ES2_ST_SSI_IDLE;
271 if (prcm_mod == OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0)) {
273 /* 3430ES1 DSS has no target idlest bits */
274 if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0))
278 * For 3430ES2+ DSS, only wait once (dss1_alwon_fclk,
279 * dss_l3_iclk, dss_l4_iclk) are enabled
281 if (clk->enable_bit != OMAP3430_EN_DSS1_SHIFT)
284 idlest_bit = OMAP3430ES2_ST_DSS_IDLE;
288 if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0) &&
289 prcm_mod == OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, 0)) {
292 * The 120MHz clock apparently has nothing to do with
293 * USBHOST module accessibility
295 if (clk->enable_bit == OMAP3430ES2_EN_USBHOST2_SHIFT)
298 idlest_bit = OMAP3430ES2_ST_USBHOST_IDLE;
303 /* Check if both functional and interface clocks
305 if (!(__raw_readl((void __iomem *)other_reg) & other_bit))
308 idlest_reg = ((other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
310 omap2_wait_clock_ready((void __iomem *)idlest_reg, idlest_bit,
314 /* Enables clock without considering parent dependencies or use count
315 * REVISIT: Maybe change this to use clk->enable like on omap1?
317 static int _omap2_clk_enable(struct clk *clk)
321 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
325 return clk->enable(clk);
327 if (!clk->enable_reg) {
328 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
330 return 0; /* REVISIT: -EINVAL */
333 regval32 = __raw_readl(clk->enable_reg);
334 if (clk->flags & INVERT_ENABLE)
335 regval32 &= ~(1 << clk->enable_bit);
337 regval32 |= (1 << clk->enable_bit);
338 __raw_writel(regval32, clk->enable_reg);
341 omap2_clk_wait_ready(clk);
346 /* Disables clock without considering parent dependencies or use count */
347 static void _omap2_clk_disable(struct clk *clk)
351 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
359 if (!clk->enable_reg) {
361 * 'Independent' here refers to a clock which is not
362 * controlled by its parent.
364 printk(KERN_ERR "clock: clk_disable called on independent "
365 "clock %s which has no enable_reg\n", clk->name);
369 regval32 = __raw_readl(clk->enable_reg);
370 if (clk->flags & INVERT_ENABLE)
371 regval32 |= (1 << clk->enable_bit);
373 regval32 &= ~(1 << clk->enable_bit);
374 __raw_writel(regval32, clk->enable_reg);
378 void omap2_clk_disable(struct clk *clk)
380 if (clk->usecount > 0 && !(--clk->usecount)) {
381 _omap2_clk_disable(clk);
383 omap2_clk_disable(clk->parent);
385 omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
390 int omap2_clk_enable(struct clk *clk)
394 if (clk->usecount++ == 0) {
396 ret = omap2_clk_enable(clk->parent);
404 omap2_clkdm_clk_enable(clk->clkdm.ptr, clk);
406 ret = _omap2_clk_enable(clk);
410 omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
413 omap2_clk_disable(clk->parent);
423 * Used for clocks that are part of CLKSEL_xyz governed clocks.
424 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
426 void omap2_clksel_recalc(struct clk *clk)
430 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
432 div = omap2_clksel_get_divisor(clk);
436 if (clk->rate == (clk->parent->rate / div))
438 clk->rate = clk->parent->rate / div;
440 pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
442 if (clk->flags & RATE_PROPAGATES)
447 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
448 * @clk: OMAP struct clk ptr to inspect
449 * @src_clk: OMAP struct clk ptr of the parent clk to search for
451 * Scan the struct clksel array associated with the clock to find
452 * the element associated with the supplied parent clock address.
453 * Returns a pointer to the struct clksel on success or NULL on error.
455 static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
458 const struct clksel *clks;
463 for (clks = clk->clksel; clks->parent; clks++) {
464 if (clks->parent == src_clk)
465 break; /* Found the requested parent */
469 printk(KERN_ERR "clock: Could not find parent clock %s in "
470 "clksel array of clock %s\n", src_clk->name,
479 * omap2_clksel_round_rate_div - find divisor for the given clock and rate
480 * @clk: OMAP struct clk to use
481 * @target_rate: desired clock rate
482 * @new_div: ptr to where we should store the divisor
484 * Finds 'best' divider value in an array based on the source and target
485 * rates. The divider array must be sorted with smallest divider first.
486 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
487 * they are only settable as part of virtual_prcm set.
489 * Returns the rounded clock rate or returns 0xffffffff on error.
491 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
494 unsigned long test_rate;
495 const struct clksel *clks;
496 const struct clksel_rate *clkr;
499 printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
500 clk->name, target_rate);
504 clks = omap2_get_clksel_by_parent(clk, clk->parent);
508 for (clkr = clks->rates; clkr->div; clkr++) {
509 if (!(clkr->flags & cpu_mask))
513 if (clkr->div <= last_div)
514 printk(KERN_ERR "clock: clksel_rate table not sorted "
515 "for clock %s", clk->name);
517 last_div = clkr->div;
519 test_rate = clk->parent->rate / clkr->div;
521 if (test_rate <= target_rate)
522 break; /* found it */
526 printk(KERN_ERR "clock: Could not find divisor for target "
527 "rate %ld for clock %s parent %s\n", target_rate,
528 clk->name, clk->parent->name);
532 *new_div = clkr->div;
534 printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
535 (clk->parent->rate / clkr->div));
537 return (clk->parent->rate / clkr->div);
541 * omap2_clksel_round_rate - find rounded rate for the given clock and rate
542 * @clk: OMAP struct clk to use
543 * @target_rate: desired clock rate
545 * Compatibility wrapper for OMAP clock framework
546 * Finds best target rate based on the source clock and possible dividers.
547 * rates. The divider array must be sorted with smallest divider first.
548 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
549 * they are only settable as part of virtual_prcm set.
551 * Returns the rounded clock rate or returns 0xffffffff on error.
553 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
557 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
561 /* Given a clock and a rate apply a clock specific rounding function */
562 long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
565 return clk->round_rate(clk, rate);
567 if (clk->flags & RATE_FIXED)
568 printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
569 "on fixed-rate clock %s\n", clk->name);
575 * omap2_clksel_to_divisor() - turn clksel field value into integer divider
576 * @clk: OMAP struct clk to use
577 * @field_val: register field value to find
579 * Given a struct clk of a rate-selectable clksel clock, and a register field
580 * value to search for, find the corresponding clock divisor. The register
581 * field value should be pre-masked and shifted down so the LSB is at bit 0
582 * before calling. Returns 0 on error
584 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
586 const struct clksel *clks;
587 const struct clksel_rate *clkr;
589 clks = omap2_get_clksel_by_parent(clk, clk->parent);
593 for (clkr = clks->rates; clkr->div; clkr++) {
594 if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
599 printk(KERN_ERR "clock: Could not find fieldval %d for "
600 "clock %s parent %s\n", field_val, clk->name,
609 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
610 * @clk: OMAP struct clk to use
611 * @div: integer divisor to search for
613 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
614 * find the corresponding register field value. The return register value is
615 * the value before left-shifting. Returns 0xffffffff on error
617 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
619 const struct clksel *clks;
620 const struct clksel_rate *clkr;
622 /* should never happen */
625 clks = omap2_get_clksel_by_parent(clk, clk->parent);
629 for (clkr = clks->rates; clkr->div; clkr++) {
630 if ((clkr->flags & cpu_mask) && (clkr->div == div))
635 printk(KERN_ERR "clock: Could not find divisor %d for "
636 "clock %s parent %s\n", div, clk->name,
645 * omap2_get_clksel - find clksel register addr & field mask for a clk
646 * @clk: struct clk to use
647 * @field_mask: ptr to u32 to store the register field mask
649 * Returns the address of the clksel register upon success or NULL on error.
651 static void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
653 if (!clk->clksel_reg || (clk->clksel_mask == 0))
656 *field_mask = clk->clksel_mask;
658 return clk->clksel_reg;
662 * omap2_clksel_get_divisor - get current divider applied to parent clock.
663 * @clk: OMAP struct clk to use.
665 * Returns the integer divisor upon success or 0 on error.
667 u32 omap2_clksel_get_divisor(struct clk *clk)
669 u32 field_mask, field_val;
670 void __iomem *div_addr;
672 div_addr = omap2_get_clksel(clk, &field_mask);
676 field_val = __raw_readl(div_addr) & field_mask;
677 field_val >>= __ffs(field_mask);
679 return omap2_clksel_to_divisor(clk, field_val);
682 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
684 u32 field_mask, field_val, validrate, new_div = 0;
685 void __iomem *div_addr;
688 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
689 if (validrate != rate)
692 div_addr = omap2_get_clksel(clk, &field_mask);
696 field_val = omap2_divisor_to_clksel(clk, new_div);
700 v = __raw_readl(div_addr);
702 v |= field_val << __ffs(field_mask);
703 __raw_writel(v, div_addr);
707 clk->rate = clk->parent->rate / new_div;
709 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
710 prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
711 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
719 /* Set the clock rate for a clock source */
720 int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
724 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
726 /* CONFIG_PARTICIPANT clocks are changed only in sets via the
727 rate table mechanism, driven by mpu_speed */
728 if (clk->flags & CONFIG_PARTICIPANT)
731 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
733 ret = clk->set_rate(clk, rate);
735 if (ret == 0 && (clk->flags & RATE_PROPAGATES))
742 * Converts encoded control register address into a full address
743 * On error, *src_addr will be returned as 0.
745 static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
746 struct clk *src_clk, u32 *field_mask,
747 struct clk *clk, u32 *parent_div)
749 const struct clksel *clks;
750 const struct clksel_rate *clkr;
755 clks = omap2_get_clksel_by_parent(clk, src_clk);
759 for (clkr = clks->rates; clkr->div; clkr++) {
760 if (clkr->flags & (cpu_mask | DEFAULT_RATE))
761 break; /* Found the default rate for this platform */
765 printk(KERN_ERR "clock: Could not find default rate for "
766 "clock %s parent %s\n", clk->name,
767 src_clk->parent->name);
771 /* Should never happen. Add a clksel mask to the struct clk. */
772 WARN_ON(clk->clksel_mask == 0);
774 *field_mask = clk->clksel_mask;
775 *src_addr = clk->clksel_reg;
776 *parent_div = clkr->div;
781 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
783 void __iomem *src_addr;
784 u32 field_val, field_mask, reg_val, parent_div;
786 if (clk->flags & CONFIG_PARTICIPANT)
792 field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
793 &field_mask, clk, &parent_div);
797 if (clk->usecount > 0)
798 _omap2_clk_disable(clk);
800 /* Set new source value (previous dividers if any in effect) */
801 reg_val = __raw_readl(src_addr) & ~field_mask;
802 reg_val |= (field_val << __ffs(field_mask));
803 __raw_writel(reg_val, src_addr);
806 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
807 prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
808 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
812 if (clk->usecount > 0)
813 _omap2_clk_enable(clk);
815 clk->parent = new_parent;
817 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
818 clk->rate = new_parent->rate;
821 clk->rate /= parent_div;
823 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
824 clk->name, clk->parent->name, clk->rate);
826 if (clk->flags & RATE_PROPAGATES)
832 /* DPLL rate rounding code */
835 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
836 * @clk: struct clk * of the DPLL
837 * @tolerance: maximum rate error tolerance
839 * Set the maximum DPLL rate error tolerance for the rate rounding
840 * algorithm. The rate tolerance is an attempt to balance DPLL power
841 * saving (the least divider value "n") vs. rate fidelity (the least
842 * difference between the desired DPLL target rate and the rounded
843 * rate out of the algorithm). So, increasing the tolerance is likely
844 * to decrease DPLL power consumption and increase DPLL rate error.
845 * Returns -EINVAL if provided a null clock ptr or a clk that is not a
846 * DPLL; or 0 upon success.
848 int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
850 if (!clk || !clk->dpll_data)
853 clk->dpll_data->rate_tolerance = tolerance;
858 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
859 unsigned int m, unsigned int n)
861 unsigned long long num;
863 num = (unsigned long long)parent_rate * m;
869 * _dpll_test_mult - test a DPLL multiplier value
870 * @m: pointer to the DPLL m (multiplier) value under test
871 * @n: current DPLL n (divider) value under test
872 * @new_rate: pointer to storage for the resulting rounded rate
873 * @target_rate: the desired DPLL rate
874 * @parent_rate: the DPLL's parent clock rate
876 * This code tests a DPLL multiplier value, ensuring that the
877 * resulting rate will not be higher than the target_rate, and that
878 * the multiplier value itself is valid for the DPLL. Initially, the
879 * integer pointed to by the m argument should be prescaled by
880 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
881 * a non-scaled m upon return. This non-scaled m will result in a
882 * new_rate as close as possible to target_rate (but not greater than
883 * target_rate) given the current (parent_rate, n, prescaled m)
884 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
885 * non-scaled m attempted to underflow, which can allow the calling
886 * function to bail out early; or 0 upon success.
888 static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
889 unsigned long target_rate,
890 unsigned long parent_rate)
892 int flags = 0, carry = 0;
894 /* Unscale m and round if necessary */
895 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
897 *m = (*m / DPLL_SCALE_FACTOR) + carry;
900 * The new rate must be <= the target rate to avoid programming
901 * a rate that is impossible for the hardware to handle
903 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
904 if (*new_rate > target_rate) {
909 /* Guard against m underflow */
910 if (*m < DPLL_MIN_MULTIPLIER) {
911 *m = DPLL_MIN_MULTIPLIER;
913 flags = DPLL_MULT_UNDERFLOW;
917 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
923 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
924 * @clk: struct clk * for a DPLL
925 * @target_rate: desired DPLL clock rate
927 * Given a DPLL, a desired target rate, and a rate tolerance, round
928 * the target rate to a possible, programmable rate for this DPLL.
929 * Rate tolerance is assumed to be set by the caller before this
930 * function is called. Attempts to select the minimum possible n
931 * within the tolerance to reduce power consumption. Stores the
932 * computed (m, n) in the DPLL's dpll_data structure so set_rate()
933 * will not need to call this (expensive) function again. Returns ~0
934 * if the target rate cannot be rounded, either because the rate is
935 * too low or because the rate tolerance is set too tightly; or the
936 * rounded rate upon success.
938 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
940 int m, n, r, e, scaled_max_m;
941 unsigned long scaled_rt_rp, new_rate;
942 int min_e = -1, min_e_m = -1, min_e_n = -1;
944 if (!clk || !clk->dpll_data)
947 pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
948 "%ld\n", clk->name, target_rate);
950 scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR);
951 scaled_max_m = clk->dpll_data->max_multiplier * DPLL_SCALE_FACTOR;
953 clk->dpll_data->last_rounded_rate = 0;
955 for (n = clk->dpll_data->max_divider; n >= DPLL_MIN_DIVIDER; n--) {
957 /* Compute the scaled DPLL multiplier, based on the divider */
958 m = scaled_rt_rp * n;
961 * Since we're counting n down, a m overflow means we can
962 * can immediately skip to the next n
964 if (m > scaled_max_m)
967 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
970 e = target_rate - new_rate;
971 pr_debug("clock: n = %d: m = %d: rate error is %d "
972 "(new_rate = %ld)\n", n, m, e, new_rate);
975 min_e >= (int)(abs(e) - clk->dpll_data->rate_tolerance)) {
980 pr_debug("clock: found new least error %d\n", min_e);
984 * Since we're counting n down, a m underflow means we
985 * can bail out completely (since as n decreases in
986 * the next iteration, there's no way that m can
987 * increase beyond the current m)
989 if (r & DPLL_MULT_UNDERFLOW)
994 pr_debug("clock: error: target rate or tolerance too low\n");
998 clk->dpll_data->last_rounded_m = min_e_m;
999 clk->dpll_data->last_rounded_n = min_e_n;
1000 clk->dpll_data->last_rounded_rate =
1001 _dpll_compute_new_rate(clk->parent->rate, min_e_m, min_e_n);
1003 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
1004 min_e, min_e_m, min_e_n);
1005 pr_debug("clock: final rate: %ld (target rate: %ld)\n",
1006 clk->dpll_data->last_rounded_rate, target_rate);
1008 return clk->dpll_data->last_rounded_rate;
1011 /*-------------------------------------------------------------------------
1012 * Omap2 clock reset and init functions
1013 *-------------------------------------------------------------------------*/
1015 #ifdef CONFIG_OMAP_RESET_CLOCKS
1016 void omap2_clk_disable_unused(struct clk *clk)
1020 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
1022 regval32 = __raw_readl(clk->enable_reg);
1023 if ((regval32 & (1 << clk->enable_bit)) == v)
1026 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
1027 _omap2_clk_disable(clk);