arch/arm/mach-omap2/clock.c

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock.c
   3  *
   4  *  Copyright (C) 2005 Texas Instruments Inc.
   5  *  Richard Woodruff <r-woodruff2@ti.com>
   6  *  Created for OMAP2.
   7  *
   8  *  Cleaned up and modified to use omap shared clock framework by
   9  *  Tony Lindgren <tony@atomide.com>
  10  *
  11  *  Based on omap1 clock.c, Copyright (C) 2004 - 2005 Nokia corporation
  12  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/device.h>
  21 #include <linux/list.h>
  22 #include <linux/errno.h>
  23 #include <linux/delay.h>
  24 #include <linux/clk.h>
  25
  26 #include <asm/io.h>
  27
  28 #include <asm/arch/clock.h>
  29 #include <asm/arch/sram.h>
  30 #include <asm/div64.h>
  31
  32 #include "memory.h"
  33 #include "clock.h"
  34 #include "prm.h"
  35 #include "prm_regbits_24xx.h"
  36 #include "cm.h"
  37 #include "cm_regbits_24xx.h"
  38
  39 #undef DEBUG
  40
  41 /* CM_CLKSEL1_CORE.CLKSEL_VLYNQ options (2420) */
  42 #define CLKSEL_VLYNQ_96MHZ              0
  43 #define CLKSEL_VLYNQ_CORECLK_16         0x10
  44
  45 //#define DOWN_VARIABLE_DPLL 1                  /* Experimental */
  46
  47 static struct prcm_config *curr_prcm_set;
  48 static u32 curr_perf_level = PRCM_FULL_SPEED;
  49 static struct clk *vclk;
  50 static struct clk *sclk;
  51 static u8 cpu_mask;
  52
  53 /*-------------------------------------------------------------------------
  54  * Omap2 specific clock functions
  55  *-------------------------------------------------------------------------*/
  56
  57 /* Recalculate SYST_CLK */
  58 static void omap2_sys_clk_recalc(struct clk * clk)
  59 {
  60         u32 div;
  61
  62         if (!cpu_is_omap34xx()) {
  63                 div = prm_read_reg(OMAP24XX_PRCM_CLKSRC_CTRL);
  64                 /* Test if ext clk divided by 1 or 2 */
  65                 div &= (0x3 << OMAP_SYSCLKDIV_SHIFT);
  66                 div >>= clk->rate_offset;
  67                 clk->rate = (clk->parent->rate / div);
  68         }
  69         propagate_rate(clk);
  70 }
  71
  72 static u32 omap2_get_dpll_rate(struct clk * tclk)
  73 {
  74         long long dpll_clk;
  75         int dpll_mult, dpll_div, amult;
  76         u32 dpll;
  77
  78         dpll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
  79
  80         dpll_mult = dpll & OMAP24XX_DPLL_MULT_MASK;
  81         dpll_mult >>= OMAP24XX_DPLL_MULT_SHIFT;         /* 10 bits */
  82         dpll_div = dpll & OMAP24XX_DPLL_DIV_MASK;
  83         dpll_div >>= OMAP24XX_DPLL_DIV_SHIFT;           /* 4 bits */
  84         dpll_clk = (long long)tclk->parent->rate * dpll_mult;
  85         do_div(dpll_clk, dpll_div + 1);
  86         amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
  87         amult &= OMAP24XX_CORE_CLK_SRC_MASK;
  88         dpll_clk *= amult;
  89
  90         return dpll_clk;
  91 }
  92
  93 static void omap2_followparent_recalc(struct clk *clk)
  94 {
  95         followparent_recalc(clk);
  96 }
  97
  98 static void omap2_propagate_rate(struct clk * clk)
  99 {
 100         if (!(clk->flags & RATE_FIXED))
 101                 clk->rate = clk->parent->rate;
 102
 103         propagate_rate(clk);
 104 }
 105
 106 static void omap2_set_osc_ck(int enable)
 107 {
 108         u32 pcc;
 109
 110         pcc = prm_read_reg(OMAP24XX_PRCM_CLKSRC_CTRL);
 111
 112         if (enable)
 113                 prm_write_reg(pcc & ~OMAP_AUTOEXTCLKMODE_MASK,
 114                               OMAP24XX_PRCM_CLKSRC_CTRL);
 115         else
 116                 prm_write_reg(pcc | OMAP_AUTOEXTCLKMODE_MASK,
 117                               OMAP24XX_PRCM_CLKSRC_CTRL);
 118 }
 119
 120 /* Enable an APLL if off */
 121 static void omap2_clk_fixed_enable(struct clk *clk)
 122 {
 123         u32 cval, i=0;
 124
 125         if (clk->enable_bit == PARENT_CONTROLS_CLOCK)   /* Parent will do it */
 126                 return;
 127
 128         cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 129
 130         if ((cval & (0x3 << clk->enable_bit)) == (0x3 << clk->enable_bit))
 131                 return;
 132
 133         cval &= ~(0x3 << clk->enable_bit);
 134         cval |= (0x3 << clk->enable_bit);
 135         cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 136
 137         if (clk == &apll96_ck)
 138                 cval = OMAP24XX_ST_96M_APLL;
 139         else if (clk == &apll54_ck)
 140                 cval = OMAP24XX_ST_54M_CLK;
 141
 142         /* Wait for lock */
 143         while (!(cm_read_mod_reg(PLL_MOD, CM_IDLEST) & cval)) {
 144                 ++i;
 145                 udelay(1);
 146                 if (i == 100000) {
 147                         printk(KERN_ERR "Clock %s didn't lock\n", clk->name);
 148                         break;
 149                 }
 150         }
 151 }
 152
 153 static void omap2_clk_wait_ready(struct clk *clk)
 154 {
 155         unsigned long reg, other_reg, st_reg;
 156         u32 bit;
 157         int i;
 158
 159         reg = (unsigned long) clk->enable_reg;
 160         if (reg == (unsigned long)OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1) ||
 161             reg == (unsigned long)OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2))
 162                 other_reg = (reg & ~0xf0) | 0x10; /* CM_ICLKEN* */
 163         else if (reg == (unsigned long)OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1) ||
 164                  reg == (unsigned long)OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2))
 165                 other_reg = (reg & ~0xf0) | 0x00; /* CM_FCLKEN* */
 166         else
 167                 return;
 168
 169         /* No check for DSS or cam clocks */
 170         if ((reg & 0x0f) == 0) {
 171                 if (clk->enable_bit <= 1 || clk->enable_bit == 31)
 172                         return;
 173         }
 174
 175         /* Check if both functional and interface clocks
 176          * are running. */
 177         bit = 1 << clk->enable_bit;
 178         if (!(cm_read_reg((void __iomem *)other_reg) & bit))
 179                 return;
 180         st_reg = (other_reg & ~0xf0) | 0x20; /* CM_IDLEST* */
 181         i = 0;
 182         while (!(cm_read_reg((void __iomem *)st_reg) & bit)) {
 183                 i++;
 184                 if (i == 100000) {
 185                         printk(KERN_ERR "Timeout enabling clock %s\n", clk->name);
 186                         break;
 187                 }
 188         }
 189         if (i)
 190                 pr_debug("Clock %s stable after %d loops\n", clk->name, i);
 191 }
 192
 193 /* Enables clock without considering parent dependencies or use count
 194  * REVISIT: Maybe change this to use clk->enable like on omap1?
 195  */
 196 static int _omap2_clk_enable(struct clk * clk)
 197 {
 198         u32 regval32;
 199
 200         if (clk->flags & ALWAYS_ENABLED)
 201                 return 0;
 202
 203         if (unlikely(clk == &osc_ck)) {
 204                 omap2_set_osc_ck(1);
 205                 return 0;
 206         }
 207
 208         if (unlikely(clk->enable_reg == 0)) {
 209                 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
 210                        clk->name);
 211                 return 0;
 212         }
 213
 214         if (clk->enable_reg == (void __iomem *)OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN)) {
 215                 omap2_clk_fixed_enable(clk);
 216                 return 0;
 217         }
 218
 219         regval32 = cm_read_reg(clk->enable_reg);
 220         regval32 |= (1 << clk->enable_bit);
 221         cm_write_reg(regval32, clk->enable_reg);
 222         wmb();
 223
 224         omap2_clk_wait_ready(clk);
 225
 226         return 0;
 227 }
 228
 229 /* Stop APLL */
 230 static void omap2_clk_fixed_disable(struct clk *clk)
 231 {
 232         u32 cval;
 233
 234         if (clk->enable_bit == PARENT_CONTROLS_CLOCK)
 235                 return;         /* let parent off do it */
 236
 237         cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 238         cval &= ~(0x3 << clk->enable_bit);
 239         cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 240 }
 241
 242 /* Disables clock without considering parent dependencies or use count */
 243 static void _omap2_clk_disable(struct clk *clk)
 244 {
 245         u32 regval32;
 246
 247         if (unlikely(clk == &osc_ck)) {
 248                 omap2_set_osc_ck(0);
 249                 return;
 250         }
 251
 252         if (clk->enable_reg == 0)
 253                 return;
 254
 255         if (clk->enable_reg == (void __iomem *)OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN)) {
 256                 omap2_clk_fixed_disable(clk);
 257                 return;
 258         }
 259
 260         regval32 = cm_read_reg(clk->enable_reg);
 261         regval32 &= ~(1 << clk->enable_bit);
 262         cm_write_reg(regval32, clk->enable_reg);
 263         wmb();
 264 }
 265
 266 static int omap2_clk_enable(struct clk *clk)
 267 {
 268         int ret = 0;
 269
 270         if (clk->usecount++ == 0) {
 271                 if (likely((u32)clk->parent))
 272                         ret = omap2_clk_enable(clk->parent);
 273
 274                 if (unlikely(ret != 0)) {
 275                         clk->usecount--;
 276                         return ret;
 277                 }
 278
 279                 ret = _omap2_clk_enable(clk);
 280
 281                 if (unlikely(ret != 0) && clk->parent) {
 282                         omap2_clk_disable(clk->parent);
 283                         clk->usecount--;
 284                 }
 285         }
 286
 287         return ret;
 288 }
 289
 290 static void omap2_clk_disable(struct clk *clk)
 291 {
 292         if (clk->usecount > 0 && !(--clk->usecount)) {
 293                 _omap2_clk_disable(clk);
 294                 if (likely((u32)clk->parent))
 295                         omap2_clk_disable(clk->parent);
 296         }
 297 }
 298
 299 /*
 300  * Uses the current prcm set to tell if a rate is valid.
 301  * You can go slower, but not faster within a given rate set.
 302  */
 303 static u32 omap2_dpll_round_rate(unsigned long target_rate)
 304 {
 305         u32 high, low, core_clk_src;
 306
 307         core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 308         core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
 309
 310         if (core_clk_src == 1) {        /* DPLL clockout */
 311                 high = curr_prcm_set->dpll_speed * 2;
 312                 low = curr_prcm_set->dpll_speed;
 313         } else {                                /* DPLL clockout x 2 */
 314                 high = curr_prcm_set->dpll_speed;
 315                 low = curr_prcm_set->dpll_speed / 2;
 316         }
 317
 318 #ifdef DOWN_VARIABLE_DPLL
 319         if (target_rate > high)
 320                 return high;
 321         else
 322                 return target_rate;
 323 #else
 324         if (target_rate > low)
 325                 return high;
 326         else
 327                 return low;
 328 #endif
 329
 330 }
 331
 332 /*
 333  * Used for clocks that are part of CLKSEL_xyz governed clocks.
 334  * REVISIT: Maybe change to use clk->enable() functions like on omap1?
 335  */
 336 static void omap2_clksel_recalc(struct clk * clk)
 337 {
 338         u32 fixed = 0, div = 0;
 339         u32 clksel1_core;
 340
 341         if (clk == &dpll_ck) {
 342                 clk->rate = omap2_get_dpll_rate(clk);
 343                 fixed = 1;
 344                 div = 0;
 345         }
 346
 347         if (clk == &iva1_mpu_int_ifck) {
 348                 div = 2;
 349                 fixed = 1;
 350         }
 351
 352         clksel1_core = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1);
 353
 354         if ((clk == &dss1_fck) &&
 355             (clksel1_core & OMAP24XX_CLKSEL_DSS1_MASK) == 0) {
 356                 clk->rate = sys_ck.rate;
 357                 return;
 358         }
 359
 360         if ((clk == &vlynq_fck) && cpu_is_omap2420() &&
 361             (clksel1_core & OMAP2420_CLKSEL_VLYNQ_MASK) == CLKSEL_VLYNQ_96MHZ) {
 362                 clk->rate = func_96m_ck.rate;
 363                 return;
 364         }
 365
 366         if (!fixed) {
 367                 div = omap2_clksel_get_divisor(clk);
 368                 if (div == 0)
 369                         return;
 370         }
 371
 372         if (div != 0) {
 373                 if (unlikely(clk->rate == clk->parent->rate / div))
 374                         return;
 375                 clk->rate = clk->parent->rate / div;
 376         }
 377
 378         if (unlikely(clk->flags & RATE_PROPAGATES))
 379                 propagate_rate(clk);
 380 }
 381
 382 /*
 383  * Finds best divider value in an array based on the source and target
 384  * rates. The divider array must be sorted with smallest divider first.
 385  */
 386 static inline u32 omap2_divider_from_table(u32 size, u32 *div_array,
 387                                            u32 src_rate, u32 tgt_rate)
 388 {
 389         int i, test_rate;
 390
 391         if (div_array == NULL)
 392                 return ~1;
 393
 394         for (i = 0; i < size; i++) {
 395                 test_rate = src_rate / *div_array;
 396                 if (test_rate <= tgt_rate)
 397                         return *div_array;
 398                 ++div_array;
 399         }
 400
 401         return ~0;      /* No acceptable divider */
 402 }
 403
 404 /*
 405  * Find divisor for the given clock and target rate.
 406  *
 407  * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
 408  * they are only settable as part of virtual_prcm set.
 409  */
 410 static u32 omap2_clksel_round_rate(struct clk *tclk, u32 target_rate,
 411         u32 *new_div)
 412 {
 413         u32 gfx_div[] = {2, 3, 4};
 414         u32 sysclkout_div[] = {1, 2, 4, 8, 16};
 415         u32 dss1_div[] = {1, 2, 3, 4, 5, 6, 8, 9, 12, 16};
 416         u32 vlynq_div[] = {1, 2, 3, 4, 6, 8, 9, 12, 16, 18};
 417         u32 best_div = ~0, asize = 0;
 418         u32 *div_array = NULL;
 419
 420         switch (tclk->flags & SRC_RATE_SEL_MASK) {
 421         case CM_GFX_SEL1:
 422                 asize = ARRAY_SIZE(gfx_div);
 423                 div_array = gfx_div;
 424                 break;
 425         case CM_PLL_SEL1:
 426                 return omap2_dpll_round_rate(target_rate);
 427         case CM_SYSCLKOUT_SEL1:
 428                 asize = ARRAY_SIZE(sysclkout_div);
 429                 div_array = sysclkout_div;
 430                 break;
 431         case CM_CORE_SEL1:
 432                 if (tclk == &dss1_fck) {
 433                         if (tclk->parent == &core_ck) {
 434                                 asize = ARRAY_SIZE(dss1_div);
 435                                 div_array = dss1_div;
 436                         } else {
 437                                 *new_div = 0; /* fixed clk */
 438                                 return(tclk->parent->rate);
 439                         }
 440                 } else if ((tclk == &vlynq_fck) && cpu_is_omap2420()) {
 441                         if (tclk->parent == &core_ck) {
 442                                 asize = ARRAY_SIZE(vlynq_div);
 443                                 div_array = vlynq_div;
 444                         } else {
 445                                 *new_div = 0; /* fixed clk */
 446                                 return (tclk->parent->rate);
 447                         }
 448                 }
 449                 break;
 450         }
 451
 452         best_div = omap2_divider_from_table(asize, div_array,
 453                                             tclk->parent->rate, target_rate);
 454         if (best_div == ~0) {
 455                 *new_div = 1;
 456                 return best_div; /* signal error */
 457         }
 458
 459         *new_div = best_div;
 460         return (tclk->parent->rate / best_div);
 461 }
 462
 463 /* Given a clock and a rate apply a clock specific rounding function */
 464 static long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
 465 {
 466         u32 new_div = 0;
 467
 468         if (clk->flags & RATE_FIXED)
 469                 return clk->rate;
 470
 471         if (clk->flags & RATE_CKCTL)
 472                 return omap2_clksel_round_rate(clk, rate, &new_div);
 473
 474         if (clk->round_rate != 0)
 475                 return clk->round_rate(clk, rate);
 476
 477         return clk->rate;
 478 }
 479
 480 static int omap2_reprogram_dpll(struct clk * clk, unsigned long rate)
 481 {
 482         u32 flags, cur_rate, low, mult, div, valid_rate, done_rate;
 483         u32 bypass = 0;
 484         struct prcm_config tmpset;
 485         int ret = -EINVAL;
 486
 487         local_irq_save(flags);
 488         cur_rate = omap2_get_dpll_rate(&dpll_ck);
 489         mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 490         mult &= OMAP24XX_CORE_CLK_SRC_MASK;
 491
 492         if ((rate == (cur_rate / 2)) && (mult == 2)) {
 493                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
 494         } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
 495                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
 496         } else if (rate != cur_rate) {
 497                 valid_rate = omap2_dpll_round_rate(rate);
 498                 if (valid_rate != rate)
 499                         goto dpll_exit;
 500
 501                 if (mult == 1)
 502                         low = curr_prcm_set->dpll_speed;
 503                 else
 504                         low = curr_prcm_set->dpll_speed / 2;
 505
 506                 /* REVISIT: This sets several reserved bits? */
 507                 tmpset.cm_clksel1_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
 508                 tmpset.cm_clksel1_pll &= ~(0x3FFF << 8);
 509                 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
 510                 tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 511                 tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
 512                 if (rate > low) {
 513                         tmpset.cm_clksel2_pll |= 0x2;
 514                         mult = ((rate / 2) / 1000000);
 515                         done_rate = CORE_CLK_SRC_DPLL_X2;
 516                 } else {
 517                         tmpset.cm_clksel2_pll |= 0x1;
 518                         mult = (rate / 1000000);
 519                         done_rate = CORE_CLK_SRC_DPLL;
 520                 }
 521                 tmpset.cm_clksel1_pll |= (div << OMAP24XX_DPLL_DIV_SHIFT);
 522                 tmpset.cm_clksel1_pll |= (mult << OMAP24XX_DPLL_MULT_SHIFT);
 523
 524                 /* Worst case */
 525                 tmpset.base_sdrc_rfr = V24XX_SDRC_RFR_CTRL_BYPASS;
 526
 527                 if (rate == curr_prcm_set->xtal_speed)  /* If asking for 1-1 */
 528                         bypass = 1;
 529
 530                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */
 531
 532                 /* Force dll lock mode */
 533                 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
 534                                bypass);
 535
 536                 /* Errata: ret dll entry state */
 537                 omap2_init_memory_params(omap2_dll_force_needed());
 538                 omap2_reprogram_sdrc(done_rate, 0);
 539         }
 540         omap2_clksel_recalc(&dpll_ck);
 541         ret = 0;
 542
 543 dpll_exit:
 544         local_irq_restore(flags);
 545         return(ret);
 546 }
 547
 548 /* Just return the MPU speed */
 549 static void omap2_mpu_recalc(struct clk * clk)
 550 {
 551         clk->rate = curr_prcm_set->mpu_speed;
 552 }
 553
 554 /*
 555  * Look for a rate equal or less than the target rate given a configuration set.
 556  *
 557  * What's not entirely clear is "which" field represents the key field.
 558  * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
 559  * just uses the ARM rates.
 560  */
 561 static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate)
 562 {
 563         struct prcm_config * ptr;
 564         long highest_rate;
 565
 566         if (clk != &virt_prcm_set)
 567                 return -EINVAL;
 568
 569         highest_rate = -EINVAL;
 570
 571         for (ptr = rate_table; ptr->mpu_speed; ptr++) {
 572                 if (!(ptr->flags & cpu_mask))
 573                         continue;
 574                 if (ptr->xtal_speed != sys_ck.rate)
 575                         continue;
 576
 577                 highest_rate = ptr->mpu_speed;
 578
 579                 /* Can check only after xtal frequency check */
 580                 if (ptr->mpu_speed <= rate)
 581                         break;
 582         }
 583         return highest_rate;
 584 }
 585
 586 /*
 587  * omap2_convert_field_to_div() - turn field value into integer divider
 588  */
 589 static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val)
 590 {
 591         u32 i;
 592         u32 clkout_array[] = {1, 2, 4, 8, 16};
 593
 594         if ((div_sel & SRC_RATE_SEL_MASK) == CM_SYSCLKOUT_SEL1) {
 595                 for (i = 0; i < 5; i++) {
 596                         if (field_val == i)
 597                                 return clkout_array[i];
 598                 }
 599                 return ~0;
 600         } else
 601                 return field_val;
 602 }
 603
 604 /*
 605  * Returns the CLKSEL divider register value
 606  * REVISIT: This should be cleaned up to work nicely with void __iomem *
 607  */
 608 static u32 omap2_get_clksel(u32 *div_sel, u32 *field_mask,
 609                             struct clk *clk)
 610 {
 611         int ret = ~0;
 612         u32 reg_val, div_off;
 613         void __iomem *div_addr = 0;
 614         u32 mask = ~0;
 615
 616         div_off = clk->rate_offset;
 617
 618         switch ((*div_sel & SRC_RATE_SEL_MASK)) {
 619         case CM_MPU_SEL1:
 620                 div_addr = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL);
 621                 mask = OMAP24XX_CLKSEL_MPU_MASK;
 622                 break;
 623         case CM_DSP_SEL1:
 624                 div_addr = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL);
 625                 if (cpu_is_omap2420()) {
 626                         if (div_off == OMAP24XX_CLKSEL_DSP_SHIFT)
 627                                 mask = OMAP24XX_CLKSEL_DSP_MASK;
 628                         else if (div_off == OMAP2420_CLKSEL_IVA_SHIFT)
 629                                 mask = OMAP2420_CLKSEL_IVA_MASK;
 630                         else if (div_off == OMAP24XX_CLKSEL_DSP_IF_SHIFT)
 631                                 mask = OMAP24XX_CLKSEL_DSP_IF_MASK;
 632                 } else if (cpu_is_omap2430()) {
 633                         if (div_off == OMAP24XX_CLKSEL_DSP_SHIFT)
 634                                 mask = OMAP24XX_CLKSEL_DSP_MASK;
 635                         else if (div_off == OMAP24XX_CLKSEL_DSP_IF_SHIFT)
 636                                 mask = OMAP24XX_CLKSEL_DSP_IF_MASK;
 637                 }
 638         case CM_GFX_SEL1:
 639                 div_addr = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL);
 640                 if (div_off == OMAP_CLKSEL_GFX_SHIFT)
 641                         mask = OMAP_CLKSEL_GFX_MASK;
 642                 break;
 643         case CM_MODEM_SEL1:
 644                 div_addr = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL);
 645                 if (div_off == OMAP2430_CLKSEL_MDM_SHIFT)
 646                         mask = OMAP2430_CLKSEL_MDM_MASK;
 647                 break;
 648         case CM_SYSCLKOUT_SEL1:
 649                 div_addr = OMAP24XX_PRCM_CLKOUT_CTRL;
 650                 if (div_off == OMAP24XX_CLKOUT_DIV_SHIFT)
 651                         mask = OMAP24XX_CLKOUT_DIV_MASK;
 652                 else if (div_off == OMAP2420_CLKOUT2_DIV_SHIFT)
 653                         mask = OMAP2420_CLKOUT2_DIV_MASK;
 654                 break;
 655         case CM_CORE_SEL1:
 656                 div_addr = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1);
 657                 switch (div_off) {
 658                 case OMAP24XX_CLKSEL_L3_SHIFT:
 659                         mask = OMAP24XX_CLKSEL_L3_MASK;
 660                         break;
 661                 case OMAP24XX_CLKSEL_L4_SHIFT:
 662                         mask = OMAP24XX_CLKSEL_L4_MASK;
 663                         break;
 664                 case OMAP24XX_CLKSEL_DSS1_SHIFT:
 665                         mask = OMAP24XX_CLKSEL_DSS1_MASK;
 666                         break;
 667                 case OMAP24XX_CLKSEL_DSS2_SHIFT:
 668                         mask = OMAP24XX_CLKSEL_DSS2_MASK;
 669                         break;
 670                 case OMAP2420_CLKSEL_VLYNQ_SHIFT:
 671                         mask = OMAP2420_CLKSEL_VLYNQ_MASK;
 672                         break;
 673                 case OMAP24XX_CLKSEL_SSI_SHIFT:
 674                         mask = OMAP24XX_CLKSEL_SSI_MASK;
 675                         break;
 676                 case OMAP24XX_CLKSEL_USB_SHIFT:
 677                         mask = OMAP24XX_CLKSEL_USB_MASK;
 678                         break;
 679                 }
 680         }
 681
 682         *field_mask = (mask >> div_off);
 683
 684         if (unlikely(mask == ~0))
 685                 div_addr = 0;
 686
 687         *div_sel = (u32)div_addr;
 688
 689         if (unlikely(div_addr == 0))
 690                 return ret;
 691
 692         /* Isolate field */
 693         reg_val = cm_read_reg(div_addr) & mask;
 694
 695         /* Normalize back to divider value */
 696         reg_val >>= div_off;
 697
 698         return reg_val;
 699 }
 700
 701 /*
 702  * Return divider to be applied to parent clock.
 703  * Return 0 on error.
 704  */
 705 static u32 omap2_clksel_get_divisor(struct clk *clk)
 706 {
 707         int ret = 0;
 708         u32 div, div_sel, div_off, field_mask, field_val;
 709
 710         /* isolate control register */
 711         div_sel = (SRC_RATE_SEL_MASK & clk->flags);
 712
 713         div_off = clk->rate_offset;
 714         field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
 715         if (div_sel == 0)
 716                 return ret;
 717
 718         div_sel = (SRC_RATE_SEL_MASK & clk->flags);
 719         div = omap2_clksel_to_divisor(div_sel, field_val);
 720
 721         return div;
 722 }
 723
 724 /* Set the clock rate for a clock source */
 725 static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
 726 {
 727         int ret = -EINVAL;
 728         void __iomem * reg;
 729         u32 div_sel, div_off, field_mask, field_val, reg_val, validrate;
 730         u32 new_div = 0;
 731
 732         if (!(clk->flags & CONFIG_PARTICIPANT) && (clk->flags & RATE_CKCTL)) {
 733                 if (clk == &dpll_ck)
 734                         return omap2_reprogram_dpll(clk, rate);
 735
 736                 /* Isolate control register */
 737                 div_sel = (SRC_RATE_SEL_MASK & clk->flags);
 738                 div_off = clk->rate_offset;
 739
 740                 validrate = omap2_clksel_round_rate(clk, rate, &new_div);
 741                 if (validrate != rate)
 742                         return ret;
 743
 744                 field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
 745                 if (div_sel == 0)
 746                         return ret;
 747
 748                 if (clk->flags & CM_SYSCLKOUT_SEL1) {
 749                         switch (new_div) {
 750                         case 16:
 751                                 field_val = 4;
 752                                 break;
 753                         case 8:
 754                                 field_val = 3;
 755                                 break;
 756                         case 4:
 757                                 field_val = 2;
 758                                 break;
 759                         case 2:
 760                                 field_val = 1;
 761                                 break;
 762                         case 1:
 763                                 field_val = 0;
 764                                 break;
 765                         }
 766                 } else
 767                         field_val = new_div;
 768
 769                 reg = (void __iomem *)div_sel;
 770
 771                 reg_val = cm_read_reg(reg);
 772                 reg_val &= ~(field_mask << div_off);
 773                 reg_val |= (field_val << div_off);
 774                 cm_write_reg(reg_val, reg);
 775                 wmb();
 776                 clk->rate = clk->parent->rate / new_div;
 777
 778                 if (clk->flags & DELAYED_APP) {
 779                         prm_write_reg(OMAP24XX_VALID_CONFIG,
 780                                       OMAP24XX_PRCM_CLKCFG_CTRL);
 781                         wmb();
 782                 }
 783                 ret = 0;
 784         } else if (clk->set_rate != 0) {
 785                 ret = clk->set_rate(clk, rate);
 786         }
 787
 788         if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
 789                 propagate_rate(clk);
 790
 791         return ret;
 792 }
 793
 794 /* Converts encoded control register address into a full address */
 795 static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset,
 796                                struct clk *src_clk, u32 *field_mask)
 797 {
 798         u32 val = ~0, mask = 0;
 799         void __iomem *src_reg_addr = 0;
 800
 801         /* Find target control register.*/
 802         switch ((*type_to_addr & SRC_RATE_SEL_MASK)) {
 803         case CM_CORE_SEL1:
 804                 src_reg_addr = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1);
 805                 if (reg_offset == OMAP24XX_CLKSEL_DSS2_SHIFT) {
 806                         mask = OMAP24XX_CLKSEL_DSS2_MASK;
 807                         mask >>= OMAP24XX_CLKSEL_DSS2_SHIFT;
 808                         if (src_clk == &sys_ck)
 809                                 val = 0;
 810                         if (src_clk == &func_48m_ck)
 811                                 val = 1;
 812                 } else if (reg_offset == OMAP24XX_CLKSEL_DSS1_SHIFT) {
 813                         mask = OMAP24XX_CLKSEL_DSS1_MASK;
 814                         mask >>= OMAP24XX_CLKSEL_DSS1_SHIFT;
 815                         if (src_clk == &sys_ck)
 816                                 val = 0;
 817                         else if (src_clk == &core_ck)   /* divided clock */
 818                                 val = 0x10;             /* rate needs fixing */
 819                 } else if ((reg_offset == OMAP2420_CLKSEL_VLYNQ_SHIFT) &&
 820                            cpu_is_omap2420()) {
 821                         mask = OMAP2420_CLKSEL_VLYNQ_MASK;
 822                         mask >>= OMAP2420_CLKSEL_VLYNQ_SHIFT;
 823                         if (src_clk == &func_96m_ck)
 824                                 val = 0;
 825                         else if (src_clk == &core_ck)
 826                                 val = 0x10;
 827                 }
 828                 break;
 829         case CM_CORE_SEL2:
 830                 src_reg_addr = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2);
 831                 mask = 0x3;
 832                 if (src_clk == &func_32k_ck)
 833                         val = 0x0;
 834                 if (src_clk == &sys_ck)
 835                         val = 0x1;
 836                 if (src_clk == &alt_ck)
 837                         val = 0x2;
 838                 break;
 839         case CM_WKUP_SEL1:
 840                 src_reg_addr = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL);
 841                 mask = 0x3;
 842                 if (src_clk == &func_32k_ck)
 843                         val = 0x0;
 844                 if (src_clk == &sys_ck)
 845                         val = 0x1;
 846                 if (src_clk == &alt_ck)
 847                         val = 0x2;
 848                 break;
 849         case CM_PLL_SEL1:
 850                 src_reg_addr = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1);
 851                 mask = 0x1;
 852                 if (reg_offset == 0x3) {
 853                         if (src_clk == &apll96_ck)
 854                                 val = 0;
 855                         if (src_clk == &alt_ck)
 856                                 val = 1;
 857                 }
 858                 else if (reg_offset == 0x5) {
 859                         if (src_clk == &apll54_ck)
 860                                 val = 0;
 861                         if (src_clk == &alt_ck)
 862                                 val = 1;
 863                 }
 864                 break;
 865         case CM_PLL_SEL2:
 866                 src_reg_addr = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2);
 867                 mask = 0x3;
 868                 if (src_clk == &func_32k_ck)
 869                         val = 0x0;
 870                 if (src_clk == &dpll_ck)
 871                         val = 0x2;
 872                 break;
 873         case CM_SYSCLKOUT_SEL1:
 874                 src_reg_addr = OMAP24XX_PRCM_CLKOUT_CTRL;
 875                 mask = 0x3;
 876                 if (src_clk == &dpll_ck)
 877                         val = 0;
 878                 if (src_clk == &sys_ck)
 879                         val = 1;
 880                 if (src_clk == &func_96m_ck)
 881                         val = 2;
 882                 if (src_clk == &func_54m_ck)
 883                         val = 3;
 884                 break;
 885         }
 886
 887         if (val == ~0)                  /* Catch errors in offset */
 888                 *type_to_addr = 0;
 889         else
 890                 *type_to_addr = (u32)src_reg_addr;
 891         *field_mask = mask;
 892
 893         return val;
 894 }
 895
 896 static int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
 897 {
 898         void __iomem * reg;
 899         u32 src_sel, src_off, field_val, field_mask, reg_val, rate;
 900         int ret = -EINVAL;
 901
 902         if (unlikely(clk->flags & CONFIG_PARTICIPANT))
 903                 return ret;
 904
 905         if (clk->flags & SRC_SEL_MASK) {        /* On-chip SEL collection */
 906                 src_sel = (SRC_RATE_SEL_MASK & clk->flags);
 907                 src_off = clk->src_offset;
 908
 909                 if (src_sel == 0)
 910                         goto set_parent_error;
 911
 912                 field_val = omap2_get_src_field(&src_sel, src_off, new_parent,
 913                                                 &field_mask);
 914
 915                 reg = (void __iomem *)src_sel;
 916
 917                 if (clk->usecount > 0)
 918                         _omap2_clk_disable(clk);
 919
 920                 /* Set new source value (previous dividers if any in effect) */
 921                 reg_val = __raw_readl(reg) & ~(field_mask << src_off);
 922                 reg_val |= (field_val << src_off);
 923                 __raw_writel(reg_val, reg);
 924                 wmb();
 925
 926                 if (clk->flags & DELAYED_APP) {
 927                         prm_write_reg(OMAP24XX_VALID_CONFIG,
 928                                       OMAP24XX_PRCM_CLKCFG_CTRL);
 929                         wmb();
 930                 }
 931                 if (clk->usecount > 0)
 932                         _omap2_clk_enable(clk);
 933
 934                 clk->parent = new_parent;
 935
 936                 /* SRC_RATE_SEL_MASK clocks follow their parents rates.*/
 937                 if ((new_parent == &core_ck) && (clk == &dss1_fck))
 938                         clk->rate = new_parent->rate / 0x10;
 939                 else
 940                         clk->rate = new_parent->rate;
 941
 942                 if (unlikely(clk->flags & RATE_PROPAGATES))
 943                         propagate_rate(clk);
 944
 945                 return 0;
 946         } else {
 947                 clk->parent = new_parent;
 948                 rate = new_parent->rate;
 949                 omap2_clk_set_rate(clk, rate);
 950                 ret = 0;
 951         }
 952
 953  set_parent_error:
 954         return ret;
 955 }
 956
 957 /* Sets basic clocks based on the specified rate */
 958 static int omap2_select_table_rate(struct clk * clk, unsigned long rate)
 959 {
 960         u32 flags, cur_rate, done_rate, bypass = 0, tmp;
 961         struct prcm_config *prcm;
 962         unsigned long found_speed = 0;
 963
 964         if (clk != &virt_prcm_set)
 965                 return -EINVAL;
 966
 967         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
 968                 if (!(prcm->flags & cpu_mask))
 969                         continue;
 970
 971                 if (prcm->xtal_speed != sys_ck.rate)
 972                         continue;
 973
 974                 if (prcm->mpu_speed <= rate) {
 975                         found_speed = prcm->mpu_speed;
 976                         break;
 977                 }
 978         }
 979
 980         if (!found_speed) {
 981                 printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
 982                        rate / 1000000);
 983                 return -EINVAL;
 984         }
 985
 986         curr_prcm_set = prcm;
 987         cur_rate = omap2_get_dpll_rate(&dpll_ck);
 988
 989         if (prcm->dpll_speed == cur_rate / 2) {
 990                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
 991         } else if (prcm->dpll_speed == cur_rate * 2) {
 992                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
 993         } else if (prcm->dpll_speed != cur_rate) {
 994                 local_irq_save(flags);
 995
 996                 if (prcm->dpll_speed == prcm->xtal_speed)
 997                         bypass = 1;
 998
 999                 if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) == 2)
1000                         done_rate = CORE_CLK_SRC_DPLL_X2;
1001                 else
1002                         done_rate = CORE_CLK_SRC_DPLL;
1003
1004                 /* MPU divider */
1005                 cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
1006
1007                 /* dsp + iva1 div(2420), iva2.1(2430) */
1008                 cm_write_mod_reg(prcm->cm_clksel_dsp,
1009                                  OMAP24XX_DSP_MOD, CM_CLKSEL);
1010
1011                 cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
1012
1013                 /* Major subsystem dividers */
1014                 tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & 0x2000;
1015                 cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1);
1016                 if (cpu_is_omap2430())
1017                         cm_write_mod_reg(prcm->cm_clksel_mdm,
1018                                          OMAP2430_MDM_MOD, CM_CLKSEL);
1019
1020                 /* x2 to enter init_mem */
1021                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
1022
1023                 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
1024                                bypass);
1025
1026                 omap2_init_memory_params(omap2_dll_force_needed());
1027                 omap2_reprogram_sdrc(done_rate, 0);
1028
1029                 local_irq_restore(flags);
1030         }
1031         omap2_clksel_recalc(&dpll_ck);
1032
1033         return 0;
1034 }
1035
1036 /*-------------------------------------------------------------------------
1037  * Omap2 clock reset and init functions
1038  *-------------------------------------------------------------------------*/
1039
1040 #ifdef CONFIG_OMAP_RESET_CLOCKS
1041 static void __init omap2_clk_disable_unused(struct clk *clk)
1042 {
1043         u32 regval32;
1044
1045         regval32 = cm_read_reg(clk->enable_reg);
1046         if ((regval32 & (1 << clk->enable_bit)) == 0)
1047                 return;
1048
1049         printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
1050         _omap2_clk_disable(clk);
1051 }
1052 #else
1053 #define omap2_clk_disable_unused        NULL
1054 #endif
1055
1056 static struct clk_functions omap2_clk_functions = {
1057         .clk_enable             = omap2_clk_enable,
1058         .clk_disable            = omap2_clk_disable,
1059         .clk_round_rate         = omap2_clk_round_rate,
1060         .clk_set_rate           = omap2_clk_set_rate,
1061         .clk_set_parent         = omap2_clk_set_parent,
1062         .clk_disable_unused     = omap2_clk_disable_unused,
1063 };
1064
1065 static void __init omap2_get_crystal_rate(struct clk *osc, struct clk *sys)
1066 {
1067         u32 div, aplls, sclk = 13000000;
1068
1069         aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
1070         aplls &= OMAP24XX_APLLS_CLKIN_MASK;
1071         aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;   /* Isolate field, 0,2,3 */
1072
1073         if (aplls == 0)
1074                 sclk = 19200000;
1075         else if (aplls == 2)
1076                 sclk = 13000000;
1077         else if (aplls == 3)
1078                 sclk = 12000000;
1079
1080         div = prm_read_reg(OMAP24XX_PRCM_CLKSRC_CTRL);
1081         div &= OMAP_SYSCLKDIV_MASK;
1082         div >>= sys->rate_offset;
1083
1084         osc->rate = sclk;
1085         sys->rate = osc->rate / div;
1086 }
1087
1088 /*
1089  * Set clocks for bypass mode for reboot to work.
1090  */
1091 void omap2_clk_prepare_for_reboot(void)
1092 {
1093         u32 rate;
1094
1095         if (vclk == NULL || sclk == NULL)
1096                 return;
1097
1098         rate = clk_get_rate(sclk);
1099         clk_set_rate(vclk, rate);
1100 }
1101
1102 /*
1103  * Switch the MPU rate if specified on cmdline.
1104  * We cannot do this early until cmdline is parsed.
1105  */
1106 static int __init omap2_clk_arch_init(void)
1107 {
1108         if (!mpurate)
1109                 return -EINVAL;
1110
1111         if (omap2_select_table_rate(&virt_prcm_set, mpurate))
1112                 printk(KERN_ERR "Could not find matching MPU rate\n");
1113
1114         propagate_rate(&osc_ck);                /* update main root fast */
1115         propagate_rate(&func_32k_ck);           /* update main root slow */
1116
1117         printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
1118                "%ld.%01ld/%ld/%ld MHz\n",
1119                (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
1120                (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
1121
1122         return 0;
1123 }
1124 arch_initcall(omap2_clk_arch_init);
1125
1126 int __init omap2_clk_init(void)
1127 {
1128         struct prcm_config *prcm;
1129         struct clk ** clkp;
1130         u32 clkrate;
1131
1132         clk_init(&omap2_clk_functions);
1133         omap2_get_crystal_rate(&osc_ck, &sys_ck);
1134
1135         for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
1136              clkp++) {
1137
1138                 if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
1139                         clk_register(*clkp);
1140                         continue;
1141                 }
1142
1143                 if ((*clkp)->flags & CLOCK_IN_OMAP243X && (cpu_is_omap2430() || cpu_is_omap34xx())) {
1144                         clk_register(*clkp);
1145                         continue;
1146                 }
1147         }
1148
1149         if (cpu_is_omap242x())
1150                 cpu_mask = RATE_IN_242X;
1151         else if (cpu_is_omap2430())
1152                 cpu_mask = RATE_IN_243X;
1153
1154         /* Check the MPU rate set by bootloader */
1155         clkrate = omap2_get_dpll_rate(&dpll_ck);
1156         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
1157                 if (!(prcm->flags & cpu_mask))
1158                         continue;
1159                 if (prcm->xtal_speed != sys_ck.rate)
1160                         continue;
1161                 if (prcm->dpll_speed <= clkrate)
1162                          break;
1163         }
1164         curr_prcm_set = prcm;
1165
1166         propagate_rate(&osc_ck);                /* update main root fast */
1167         propagate_rate(&func_32k_ck);           /* update main root slow */
1168
1169         printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
1170                "%ld.%01ld/%ld/%ld MHz\n",
1171                (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
1172                (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
1173
1174         /*
1175          * Only enable those clocks we will need, let the drivers
1176          * enable other clocks as necessary
1177          */
1178         clk_enable(&sync_32k_ick);
1179         clk_enable(&omapctrl_ick);
1180
1181         /* Force the APLLs always active. The clocks are idled
1182          * automatically by hardware. */
1183         clk_enable(&apll96_ck);
1184         clk_enable(&apll54_ck);
1185
1186         if (cpu_is_omap2430())
1187                 clk_enable(&sdrc_ick);
1188
1189         /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
1190         vclk = clk_get(NULL, "virt_prcm_set");
1191         sclk = clk_get(NULL, "sys_ck");
1192
1193         return 0;
1194 }