2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/list.h>
21 #include <linux/errno.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
24 #include <linux/bitops.h>
27 #include <asm/arch/clock.h>
28 #include <asm/arch/clockdomain.h>
29 #include <asm/arch/sram.h>
30 #include <asm/arch/cpu.h>
31 #include <asm/div64.h>
37 #include "prm-regbits-24xx.h"
39 #include "cm-regbits-24xx.h"
40 #include "cm-regbits-34xx.h"
42 #define MAX_CLOCK_ENABLE_WAIT 100000
44 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
45 #define DPLL_MIN_MULTIPLIER 1
46 #define DPLL_MIN_DIVIDER 1
48 /* Possible error results from _dpll_test_mult */
49 #define DPLL_MULT_UNDERFLOW (1 << 0)
52 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
53 * The higher the scale factor, the greater the risk of arithmetic overflow,
54 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
55 * must be a power of DPLL_SCALE_BASE.
57 #define DPLL_SCALE_FACTOR 64
58 #define DPLL_SCALE_BASE 2
59 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
60 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
64 /*-------------------------------------------------------------------------
65 * OMAP2/3 specific clock functions
66 *-------------------------------------------------------------------------*/
69 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
70 * @clk: OMAP clock struct ptr to use
72 * Convert a clockdomain name stored in a struct clk 'clk' into a
73 * clockdomain pointer, and save it into the struct clk. Intended to be
74 * called during clk_register(). No return value.
76 void omap2_init_clk_clkdm(struct clk *clk)
78 struct clockdomain *clkdm;
83 clkdm = clkdm_lookup(clk->clkdm_name);
85 pr_debug("clock: associated clk %s to clkdm %s\n",
86 clk->name, clk->clkdm_name);
89 pr_debug("clock: could not associate clk %s to "
90 "clkdm %s\n", clk->name, clk->clkdm_name);
95 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
96 * @clk: OMAP clock struct ptr to use
98 * Given a pointer to a source-selectable struct clk, read the hardware
99 * register and determine what its parent is currently set to. Update the
100 * clk->parent field with the appropriate clk ptr.
102 void omap2_init_clksel_parent(struct clk *clk)
104 const struct clksel *clks;
105 const struct clksel_rate *clkr;
111 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
112 r >>= __ffs(clk->clksel_mask);
114 for (clks = clk->clksel; clks->parent && !found; clks++) {
115 for (clkr = clks->rates; clkr->div && !found; clkr++) {
116 if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
117 if (clk->parent != clks->parent) {
118 pr_debug("clock: inited %s parent "
120 clk->name, clks->parent->name,
122 clk->parent->name : "NULL"));
123 clk->parent = clks->parent;
131 printk(KERN_ERR "clock: init parent: could not find "
132 "regval %0x for clock %s\n", r, clk->name);
137 /* Returns the DPLL rate */
138 u32 omap2_get_dpll_rate(struct clk *clk)
141 u32 dpll_mult, dpll_div, dpll;
142 struct dpll_data *dd;
145 /* REVISIT: What do we return on error? */
149 dpll = __raw_readl(dd->mult_div1_reg);
150 dpll_mult = dpll & dd->mult_mask;
151 dpll_mult >>= __ffs(dd->mult_mask);
152 dpll_div = dpll & dd->div1_mask;
153 dpll_div >>= __ffs(dd->div1_mask);
155 dpll_clk = (long long)clk->parent->rate * dpll_mult;
156 do_div(dpll_clk, dpll_div + 1);
162 * Used for clocks that have the same value as the parent clock,
163 * divided by some factor
165 void omap2_fixed_divisor_recalc(struct clk *clk)
167 WARN_ON(!clk->fixed_div);
169 clk->rate = clk->parent->rate / clk->fixed_div;
171 if (clk->flags & RATE_PROPAGATES)
176 * omap2_wait_clock_ready - wait for clock to enable
177 * @reg: physical address of clock IDLEST register
178 * @mask: value to mask against to determine if the clock is active
179 * @name: name of the clock (for printk)
181 * Returns 1 if the clock enabled in time, or 0 if it failed to enable
182 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
184 int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
190 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
191 * 34xx reverses this, just to keep us on our toes
193 if (cpu_mask & (RATE_IN_242X | RATE_IN_243X))
195 else if (cpu_mask & RATE_IN_343X)
199 while (((__raw_readl(reg) & mask) != ena) &&
200 (i++ < MAX_CLOCK_ENABLE_WAIT)) {
204 if (i < MAX_CLOCK_ENABLE_WAIT)
205 pr_debug("Clock %s stable after %d loops\n", name, i);
207 printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
208 name, MAX_CLOCK_ENABLE_WAIT);
211 return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
216 * Note: We don't need special code here for INVERT_ENABLE
217 * for the time being since INVERT_ENABLE only applies to clocks enabled by
220 * REVISIT: This code is ugly and does not belong here.
222 static void omap2_clk_wait_ready(struct clk *clk)
224 u32 bit, reg, other_reg, st_reg;
226 reg = (__force u32)clk->enable_reg;
227 if (((reg & 0xff) >= CM_FCLKEN1) &&
228 ((reg & 0xff) <= OMAP24XX_CM_FCLKEN2))
229 other_reg = ((reg & ~0xf0) | 0x10); /* CM_ICLKEN* */
230 else if (((reg & 0xff) >= CM_ICLKEN1) &&
231 ((reg & 0xff) <= OMAP24XX_CM_ICLKEN4))
232 other_reg = ((reg & ~0xf0) | 0x00); /* CM_FCLKEN* */
236 /* REVISIT: What are the appropriate exclusions for 34XX? */
237 /* No check for DSS or cam clocks */
238 if (cpu_is_omap24xx() && (reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
239 if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
240 clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
241 clk->enable_bit == OMAP24XX_EN_CAM_SHIFT)
245 /* REVISIT: What are the appropriate exclusions for 34XX? */
246 /* OMAP3: ignore DSS-mod clocks */
247 if (cpu_is_omap34xx() &&
248 ((reg & ~0xff) == (__force u32)OMAP_CM_REGADDR(OMAP3430_DSS_MOD, 0) ||
249 (((reg & ~0xff) == (__force u32)OMAP_CM_REGADDR(CORE_MOD, 0)) &&
250 clk->enable_bit == OMAP3430_EN_SSI_SHIFT)))
253 /* Check if both functional and interface clocks
255 bit = 1 << clk->enable_bit;
256 if (!(__raw_readl((__force void __iomem *)other_reg) & bit))
258 st_reg = ((other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
260 omap2_wait_clock_ready((__force void __iomem *)st_reg, bit, clk->name);
263 /* Enables clock without considering parent dependencies or use count
264 * REVISIT: Maybe change this to use clk->enable like on omap1?
266 static int _omap2_clk_enable(struct clk *clk)
270 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
274 return clk->enable(clk);
276 if (!clk->enable_reg) {
277 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
279 return 0; /* REVISIT: -EINVAL */
282 regval32 = __raw_readl(clk->enable_reg);
283 if (clk->flags & INVERT_ENABLE)
284 regval32 &= ~(1 << clk->enable_bit);
286 regval32 |= (1 << clk->enable_bit);
287 __raw_writel(regval32, clk->enable_reg);
290 omap2_clk_wait_ready(clk);
295 /* Disables clock without considering parent dependencies or use count */
296 static void _omap2_clk_disable(struct clk *clk)
300 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
308 if (!clk->enable_reg) {
310 * 'Independent' here refers to a clock which is not
311 * controlled by its parent.
313 printk(KERN_ERR "clock: clk_disable called on independent "
314 "clock %s which has no enable_reg\n", clk->name);
318 regval32 = __raw_readl(clk->enable_reg);
319 if (clk->flags & INVERT_ENABLE)
320 regval32 |= (1 << clk->enable_bit);
322 regval32 &= ~(1 << clk->enable_bit);
323 __raw_writel(regval32, clk->enable_reg);
327 void omap2_clk_disable(struct clk *clk)
329 if (clk->usecount > 0 && !(--clk->usecount)) {
330 _omap2_clk_disable(clk);
332 omap2_clk_disable(clk->parent);
334 omap2_clkdm_clk_disable(clk->clkdm, clk);
339 int omap2_clk_enable(struct clk *clk)
343 if (clk->usecount++ == 0) {
345 ret = omap2_clk_enable(clk->parent);
353 omap2_clkdm_clk_enable(clk->clkdm, clk);
355 ret = _omap2_clk_enable(clk);
359 omap2_clkdm_clk_disable(clk->clkdm, clk);
362 omap2_clk_disable(clk->parent);
372 * Used for clocks that are part of CLKSEL_xyz governed clocks.
373 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
375 void omap2_clksel_recalc(struct clk *clk)
379 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
381 div = omap2_clksel_get_divisor(clk);
385 if (clk->rate == (clk->parent->rate / div))
387 clk->rate = clk->parent->rate / div;
389 pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
391 if (clk->flags & RATE_PROPAGATES)
396 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
397 * @clk: OMAP struct clk ptr to inspect
398 * @src_clk: OMAP struct clk ptr of the parent clk to search for
400 * Scan the struct clksel array associated with the clock to find
401 * the element associated with the supplied parent clock address.
402 * Returns a pointer to the struct clksel on success or NULL on error.
404 static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
407 const struct clksel *clks;
412 for (clks = clk->clksel; clks->parent; clks++) {
413 if (clks->parent == src_clk)
414 break; /* Found the requested parent */
418 printk(KERN_ERR "clock: Could not find parent clock %s in "
419 "clksel array of clock %s\n", src_clk->name,
428 * omap2_clksel_round_rate_div - find divisor for the given clock and rate
429 * @clk: OMAP struct clk to use
430 * @target_rate: desired clock rate
431 * @new_div: ptr to where we should store the divisor
433 * Finds 'best' divider value in an array based on the source and target
434 * rates. The divider array must be sorted with smallest divider first.
435 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
436 * they are only settable as part of virtual_prcm set.
438 * Returns the rounded clock rate or returns 0xffffffff on error.
440 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
443 unsigned long test_rate;
444 const struct clksel *clks;
445 const struct clksel_rate *clkr;
448 printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
449 clk->name, target_rate);
453 clks = omap2_get_clksel_by_parent(clk, clk->parent);
457 for (clkr = clks->rates; clkr->div; clkr++) {
458 if (!(clkr->flags & cpu_mask))
462 if (clkr->div <= last_div)
463 printk(KERN_ERR "clock: clksel_rate table not sorted "
464 "for clock %s", clk->name);
466 last_div = clkr->div;
468 test_rate = clk->parent->rate / clkr->div;
470 if (test_rate <= target_rate)
471 break; /* found it */
475 printk(KERN_ERR "clock: Could not find divisor for target "
476 "rate %ld for clock %s parent %s\n", target_rate,
477 clk->name, clk->parent->name);
481 *new_div = clkr->div;
483 printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
484 (clk->parent->rate / clkr->div));
486 return (clk->parent->rate / clkr->div);
490 * omap2_clksel_round_rate - find rounded rate for the given clock and rate
491 * @clk: OMAP struct clk to use
492 * @target_rate: desired clock rate
494 * Compatibility wrapper for OMAP clock framework
495 * Finds best target rate based on the source clock and possible dividers.
496 * rates. The divider array must be sorted with smallest divider first.
497 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
498 * they are only settable as part of virtual_prcm set.
500 * Returns the rounded clock rate or returns 0xffffffff on error.
502 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
506 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
510 /* Given a clock and a rate apply a clock specific rounding function */
511 long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
514 return clk->round_rate(clk, rate);
516 if (clk->flags & RATE_FIXED)
517 printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
518 "on fixed-rate clock %s\n", clk->name);
524 * omap2_clksel_to_divisor() - turn clksel field value into integer divider
525 * @clk: OMAP struct clk to use
526 * @field_val: register field value to find
528 * Given a struct clk of a rate-selectable clksel clock, and a register field
529 * value to search for, find the corresponding clock divisor. The register
530 * field value should be pre-masked and shifted down so the LSB is at bit 0
531 * before calling. Returns 0 on error
533 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
535 const struct clksel *clks;
536 const struct clksel_rate *clkr;
538 clks = omap2_get_clksel_by_parent(clk, clk->parent);
542 for (clkr = clks->rates; clkr->div; clkr++) {
543 if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
548 printk(KERN_ERR "clock: Could not find fieldval %d for "
549 "clock %s parent %s\n", field_val, clk->name,
558 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
559 * @clk: OMAP struct clk to use
560 * @div: integer divisor to search for
562 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
563 * find the corresponding register field value. The return register value is
564 * the value before left-shifting. Returns 0xffffffff on error
566 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
568 const struct clksel *clks;
569 const struct clksel_rate *clkr;
571 /* should never happen */
574 clks = omap2_get_clksel_by_parent(clk, clk->parent);
578 for (clkr = clks->rates; clkr->div; clkr++) {
579 if ((clkr->flags & cpu_mask) && (clkr->div == div))
584 printk(KERN_ERR "clock: Could not find divisor %d for "
585 "clock %s parent %s\n", div, clk->name,
594 * omap2_get_clksel - find clksel register addr & field mask for a clk
595 * @clk: struct clk to use
596 * @field_mask: ptr to u32 to store the register field mask
598 * Returns the address of the clksel register upon success or NULL on error.
600 static void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
602 if (!clk->clksel_reg || (clk->clksel_mask == 0))
605 *field_mask = clk->clksel_mask;
607 return clk->clksel_reg;
611 * omap2_clksel_get_divisor - get current divider applied to parent clock.
612 * @clk: OMAP struct clk to use.
614 * Returns the integer divisor upon success or 0 on error.
616 u32 omap2_clksel_get_divisor(struct clk *clk)
618 u32 field_mask, field_val;
619 void __iomem *div_addr;
621 div_addr = omap2_get_clksel(clk, &field_mask);
625 field_val = __raw_readl(div_addr) & field_mask;
626 field_val >>= __ffs(field_mask);
628 return omap2_clksel_to_divisor(clk, field_val);
631 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
633 u32 field_mask, field_val, validrate, new_div = 0;
634 void __iomem *div_addr;
636 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
637 if (validrate != rate)
640 div_addr = omap2_get_clksel(clk, &field_mask);
644 field_val = omap2_divisor_to_clksel(clk, new_div);
648 cm_rmw_reg_bits(field_mask, field_val << __ffs(field_mask), div_addr);
652 clk->rate = clk->parent->rate / new_div;
654 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
655 prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
656 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
664 /* Set the clock rate for a clock source */
665 int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
669 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
671 /* CONFIG_PARTICIPANT clocks are changed only in sets via the
672 rate table mechanism, driven by mpu_speed */
673 if (clk->flags & CONFIG_PARTICIPANT)
676 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
678 ret = clk->set_rate(clk, rate);
680 if (ret == 0 && (clk->flags & RATE_PROPAGATES))
687 * Converts encoded control register address into a full address
688 * On error, *src_addr will be returned as 0.
690 static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
691 struct clk *src_clk, u32 *field_mask,
692 struct clk *clk, u32 *parent_div)
694 const struct clksel *clks;
695 const struct clksel_rate *clkr;
700 clks = omap2_get_clksel_by_parent(clk, src_clk);
704 for (clkr = clks->rates; clkr->div; clkr++) {
705 if (clkr->flags & (cpu_mask | DEFAULT_RATE))
706 break; /* Found the default rate for this platform */
710 printk(KERN_ERR "clock: Could not find default rate for "
711 "clock %s parent %s\n", clk->name,
712 src_clk->parent->name);
716 /* Should never happen. Add a clksel mask to the struct clk. */
717 WARN_ON(clk->clksel_mask == 0);
719 *field_mask = clk->clksel_mask;
720 *src_addr = clk->clksel_reg;
721 *parent_div = clkr->div;
726 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
728 void __iomem *src_addr;
729 u32 field_val, field_mask, reg_val, parent_div;
731 if (clk->flags & CONFIG_PARTICIPANT)
737 field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
738 &field_mask, clk, &parent_div);
742 if (clk->usecount > 0)
743 _omap2_clk_disable(clk);
745 /* Set new source value (previous dividers if any in effect) */
746 reg_val = __raw_readl(src_addr) & ~field_mask;
747 reg_val |= (field_val << __ffs(field_mask));
748 __raw_writel(reg_val, src_addr);
751 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
752 prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
753 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
757 if (clk->usecount > 0)
758 _omap2_clk_enable(clk);
760 clk->parent = new_parent;
762 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
763 clk->rate = new_parent->rate;
766 clk->rate /= parent_div;
768 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
769 clk->name, clk->parent->name, clk->rate);
771 if (clk->flags & RATE_PROPAGATES)
777 /* DPLL rate rounding code */
780 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
781 * @clk: struct clk * of the DPLL
782 * @tolerance: maximum rate error tolerance
784 * Set the maximum DPLL rate error tolerance for the rate rounding
785 * algorithm. The rate tolerance is an attempt to balance DPLL power
786 * saving (the least divider value "n") vs. rate fidelity (the least
787 * difference between the desired DPLL target rate and the rounded
788 * rate out of the algorithm). So, increasing the tolerance is likely
789 * to decrease DPLL power consumption and increase DPLL rate error.
790 * Returns -EINVAL if provided a null clock ptr or a clk that is not a
791 * DPLL; or 0 upon success.
793 int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
795 if (!clk || !clk->dpll_data)
798 clk->dpll_data->rate_tolerance = tolerance;
803 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
804 unsigned int m, unsigned int n)
806 unsigned long long num;
808 num = (unsigned long long)parent_rate * m;
814 * _dpll_test_mult - test a DPLL multiplier value
815 * @m: pointer to the DPLL m (multiplier) value under test
816 * @n: current DPLL n (divider) value under test
817 * @new_rate: pointer to storage for the resulting rounded rate
818 * @target_rate: the desired DPLL rate
819 * @parent_rate: the DPLL's parent clock rate
821 * This code tests a DPLL multiplier value, ensuring that the
822 * resulting rate will not be higher than the target_rate, and that
823 * the multiplier value itself is valid for the DPLL. Initially, the
824 * integer pointed to by the m argument should be prescaled by
825 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
826 * a non-scaled m upon return. This non-scaled m will result in a
827 * new_rate as close as possible to target_rate (but not greater than
828 * target_rate) given the current (parent_rate, n, prescaled m)
829 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
830 * non-scaled m attempted to underflow, which can allow the calling
831 * function to bail out early; or 0 upon success.
833 static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
834 unsigned long target_rate,
835 unsigned long parent_rate)
837 int flags = 0, carry = 0;
839 /* Unscale m and round if necessary */
840 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
842 *m = (*m / DPLL_SCALE_FACTOR) + carry;
845 * The new rate must be <= the target rate to avoid programming
846 * a rate that is impossible for the hardware to handle
848 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
849 if (*new_rate > target_rate) {
854 /* Guard against m underflow */
855 if (*m < DPLL_MIN_MULTIPLIER) {
856 *m = DPLL_MIN_MULTIPLIER;
858 flags = DPLL_MULT_UNDERFLOW;
862 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
868 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
869 * @clk: struct clk * for a DPLL
870 * @target_rate: desired DPLL clock rate
872 * Given a DPLL, a desired target rate, and a rate tolerance, round
873 * the target rate to a possible, programmable rate for this DPLL.
874 * Rate tolerance is assumed to be set by the caller before this
875 * function is called. Attempts to select the minimum possible n
876 * within the tolerance to reduce power consumption. Stores the
877 * computed (m, n) in the DPLL's dpll_data structure so set_rate()
878 * will not need to call this (expensive) function again. Returns ~0
879 * if the target rate cannot be rounded, either because the rate is
880 * too low or because the rate tolerance is set too tightly; or the
881 * rounded rate upon success.
883 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
885 int m, n, r, e, scaled_max_m;
886 unsigned long scaled_rt_rp, new_rate;
887 int min_e = -1, min_e_m = -1, min_e_n = -1;
889 if (!clk || !clk->dpll_data)
892 pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
893 "%ld\n", clk->name, target_rate);
895 scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR);
896 scaled_max_m = clk->dpll_data->max_multiplier * DPLL_SCALE_FACTOR;
898 clk->dpll_data->last_rounded_rate = 0;
900 for (n = clk->dpll_data->max_divider; n >= DPLL_MIN_DIVIDER; n--) {
902 /* Compute the scaled DPLL multiplier, based on the divider */
903 m = scaled_rt_rp * n;
906 * Since we're counting n down, a m overflow means we can
907 * can immediately skip to the next n
909 if (m > scaled_max_m)
912 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
915 e = target_rate - new_rate;
916 pr_debug("clock: n = %d: m = %d: rate error is %d "
917 "(new_rate = %ld)\n", n, m, e, new_rate);
920 min_e >= (int)(abs(e) - clk->dpll_data->rate_tolerance)) {
925 pr_debug("clock: found new least error %d\n", min_e);
929 * Since we're counting n down, a m underflow means we
930 * can bail out completely (since as n decreases in
931 * the next iteration, there's no way that m can
932 * increase beyond the current m)
934 if (r & DPLL_MULT_UNDERFLOW)
939 pr_debug("clock: error: target rate or tolerance too low\n");
943 clk->dpll_data->last_rounded_m = min_e_m;
944 clk->dpll_data->last_rounded_n = min_e_n;
945 clk->dpll_data->last_rounded_rate =
946 _dpll_compute_new_rate(clk->parent->rate, min_e_m, min_e_n);
948 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
949 min_e, min_e_m, min_e_n);
950 pr_debug("clock: final rate: %ld (target rate: %ld)\n",
951 clk->dpll_data->last_rounded_rate, target_rate);
953 return clk->dpll_data->last_rounded_rate;
956 /*-------------------------------------------------------------------------
957 * Omap2 clock reset and init functions
958 *-------------------------------------------------------------------------*/
960 #ifdef CONFIG_OMAP_RESET_CLOCKS
961 void omap2_clk_disable_unused(struct clk *clk)
965 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
967 regval32 = __raw_readl(clk->enable_reg);
968 if ((regval32 & (1 << clk->enable_bit)) == v)
971 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
972 _omap2_clk_disable(clk);