2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/list.h>
21 #include <linux/errno.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
24 #include <asm/bitops.h>
28 #include <asm/arch/clock.h>
29 #include <asm/arch/sram.h>
30 #include <asm/arch/cpu.h>
31 #include <asm/div64.h>
37 #include "prm-regbits-24xx.h"
39 #include "cm-regbits-24xx.h"
40 #include "cm-regbits-34xx.h"
42 #define MAX_CLOCK_ENABLE_WAIT 100000
44 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
45 #define DPLL_MIN_MULTIPLIER 1
46 #define DPLL_MIN_DIVIDER 1
48 /* Possible error results from _dpll_test_mult */
49 #define DPLL_MULT_UNDERFLOW (1 << 0)
52 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
53 * The higher the scale factor, the greater the risk of arithmetic overflow,
54 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
55 * must be a power of DPLL_SCALE_BASE.
57 #define DPLL_SCALE_FACTOR 64
58 #define DPLL_SCALE_BASE 2
59 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
60 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
64 /*-------------------------------------------------------------------------
65 * Omap2 specific clock functions
66 *-------------------------------------------------------------------------*/
69 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
70 * @clk: OMAP clock struct ptr to use
72 * Given a pointer to a source-selectable struct clk, read the hardware
73 * register and determine what its parent is currently set to. Update the
74 * clk->parent field with the appropriate clk ptr.
76 void omap2_init_clksel_parent(struct clk *clk)
78 const struct clksel *clks;
79 const struct clksel_rate *clkr;
85 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
86 r >>= __ffs(clk->clksel_mask);
88 for (clks = clk->clksel; clks->parent && !found; clks++) {
89 for (clkr = clks->rates; clkr->div && !found; clkr++) {
90 if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
91 if (clk->parent != clks->parent) {
92 pr_debug("clock: inited %s parent "
94 clk->name, clks->parent->name,
96 clk->parent->name : "NULL"));
97 clk->parent = clks->parent;
105 printk(KERN_ERR "clock: init parent: could not find "
106 "regval %0x for clock %s\n", r, clk->name);
111 /* Returns the DPLL rate */
112 u32 omap2_get_dpll_rate(struct clk *clk)
115 u32 dpll_mult, dpll_div, dpll;
116 struct dpll_data *dd;
119 /* REVISIT: What do we return on error? */
123 dpll = __raw_readl(dd->mult_div1_reg);
124 dpll_mult = dpll & dd->mult_mask;
125 dpll_mult >>= __ffs(dd->mult_mask);
126 dpll_div = dpll & dd->div1_mask;
127 dpll_div >>= __ffs(dd->div1_mask);
129 dpll_clk = (long long)clk->parent->rate * dpll_mult;
130 do_div(dpll_clk, dpll_div + 1);
136 * Used for clocks that have the same value as the parent clock,
137 * divided by some factor
139 void omap2_fixed_divisor_recalc(struct clk *clk)
141 WARN_ON(!clk->fixed_div);
143 clk->rate = clk->parent->rate / clk->fixed_div;
145 if (clk->flags & RATE_PROPAGATES)
150 * omap2_wait_clock_ready - wait for clock to enable
151 * @reg: physical address of clock IDLEST register
152 * @mask: value to mask against to determine if the clock is active
153 * @name: name of the clock (for printk)
155 * Returns 1 if the clock enabled in time, or 0 if it failed to enable
156 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
158 int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
164 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
165 * 34xx reverses this, just to keep us on our toes
167 if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) {
169 } else if (cpu_mask & RATE_IN_343X) {
174 while (((__raw_readl(reg) & mask) != ena) &&
175 (i++ < MAX_CLOCK_ENABLE_WAIT)) {
179 if (i < MAX_CLOCK_ENABLE_WAIT)
180 pr_debug("Clock %s stable after %d loops\n", name, i);
182 printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
183 name, MAX_CLOCK_ENABLE_WAIT);
186 return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
191 * Note: We don't need special code here for INVERT_ENABLE
192 * for the time being since INVERT_ENABLE only applies to clocks enabled by
195 static void omap2_clk_wait_ready(struct clk *clk)
197 void __iomem *reg, *other_reg, *st_reg;
201 * REVISIT: This code is pretty ugly. It would be nice to generalize
202 * it and pull it into struct clk itself somehow.
204 reg = clk->enable_reg;
205 if ((((u32)reg & 0xff) >= CM_FCLKEN1) &&
206 (((u32)reg & 0xff) <= OMAP24XX_CM_FCLKEN2))
207 other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x10); /* CM_ICLKEN* */
208 else if ((((u32)reg & 0xff) >= CM_ICLKEN1) &&
209 (((u32)reg & 0xff) <= OMAP24XX_CM_ICLKEN4))
210 other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x00); /* CM_FCLKEN* */
214 /* REVISIT: What are the appropriate exclusions for 34XX? */
215 /* No check for DSS or cam clocks */
216 if (cpu_is_omap24xx() && ((u32)reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
217 if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
218 clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
219 clk->enable_bit == OMAP24XX_EN_CAM_SHIFT)
223 /* REVISIT: What are the appropriate exclusions for 34XX? */
224 /* OMAP3: ignore DSS-mod clocks */
225 if (cpu_is_omap34xx() &&
226 (((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(OMAP3430_DSS_MOD, 0)))
229 /* Check if both functional and interface clocks
231 bit = 1 << clk->enable_bit;
232 if (!(__raw_readl(other_reg) & bit))
234 st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
236 omap2_wait_clock_ready(st_reg, bit, clk->name);
239 /* Enables clock without considering parent dependencies or use count
240 * REVISIT: Maybe change this to use clk->enable like on omap1?
242 int _omap2_clk_enable(struct clk *clk)
246 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
250 return clk->enable(clk);
252 if (unlikely(clk->enable_reg == 0)) {
253 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
255 return 0; /* REVISIT: -EINVAL */
258 regval32 = __raw_readl(clk->enable_reg);
259 if (clk->flags & INVERT_ENABLE)
260 regval32 &= ~(1 << clk->enable_bit);
262 regval32 |= (1 << clk->enable_bit);
263 __raw_writel(regval32, clk->enable_reg);
266 omap2_clk_wait_ready(clk);
271 /* Disables clock without considering parent dependencies or use count */
272 void _omap2_clk_disable(struct clk *clk)
276 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
284 if (clk->enable_reg == 0) {
286 * 'Independent' here refers to a clock which is not
287 * controlled by its parent.
289 printk(KERN_ERR "clock: clk_disable called on independent "
290 "clock %s which has no enable_reg\n", clk->name);
294 regval32 = __raw_readl(clk->enable_reg);
295 if (clk->flags & INVERT_ENABLE)
296 regval32 |= (1 << clk->enable_bit);
298 regval32 &= ~(1 << clk->enable_bit);
299 __raw_writel(regval32, clk->enable_reg);
303 void omap2_clk_disable(struct clk *clk)
305 if (clk->usecount > 0 && !(--clk->usecount)) {
306 _omap2_clk_disable(clk);
307 if (likely((u32)clk->parent))
308 omap2_clk_disable(clk->parent);
312 int omap2_clk_enable(struct clk *clk)
316 if (clk->usecount++ == 0) {
317 if (likely((u32)clk->parent))
318 ret = omap2_clk_enable(clk->parent);
320 if (unlikely(ret != 0)) {
325 ret = _omap2_clk_enable(clk);
327 if (unlikely(ret != 0) && clk->parent) {
328 omap2_clk_disable(clk->parent);
337 * Used for clocks that are part of CLKSEL_xyz governed clocks.
338 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
340 void omap2_clksel_recalc(struct clk *clk)
344 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
346 div = omap2_clksel_get_divisor(clk);
350 if (unlikely(clk->rate == clk->parent->rate / div))
352 clk->rate = clk->parent->rate / div;
354 pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
356 if (unlikely(clk->flags & RATE_PROPAGATES))
361 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
362 * @clk: OMAP struct clk ptr to inspect
363 * @src_clk: OMAP struct clk ptr of the parent clk to search for
365 * Scan the struct clksel array associated with the clock to find
366 * the element associated with the supplied parent clock address.
367 * Returns a pointer to the struct clksel on success or NULL on error.
369 const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
372 const struct clksel *clks;
377 for (clks = clk->clksel; clks->parent; clks++) {
378 if (clks->parent == src_clk)
379 break; /* Found the requested parent */
383 printk(KERN_ERR "clock: Could not find parent clock %s in "
384 "clksel array of clock %s\n", src_clk->name,
393 * omap2_clksel_round_rate_div - find divisor for the given clock and rate
394 * @clk: OMAP struct clk to use
395 * @target_rate: desired clock rate
396 * @new_div: ptr to where we should store the divisor
398 * Finds 'best' divider value in an array based on the source and target
399 * rates. The divider array must be sorted with smallest divider first.
400 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
401 * they are only settable as part of virtual_prcm set.
403 * Returns the rounded clock rate or returns 0xffffffff on error.
405 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
408 unsigned long test_rate;
409 const struct clksel *clks;
410 const struct clksel_rate *clkr;
413 printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
414 clk->name, target_rate);
418 clks = omap2_get_clksel_by_parent(clk, clk->parent);
422 for (clkr = clks->rates; clkr->div; clkr++) {
423 if (!(clkr->flags & cpu_mask))
427 if (clkr->div <= last_div)
428 printk(KERN_ERR "clock: clksel_rate table not sorted "
429 "for clock %s", clk->name);
431 last_div = clkr->div;
433 test_rate = clk->parent->rate / clkr->div;
435 if (test_rate <= target_rate)
436 break; /* found it */
440 printk(KERN_ERR "clock: Could not find divisor for target "
441 "rate %ld for clock %s parent %s\n", target_rate,
442 clk->name, clk->parent->name);
446 *new_div = clkr->div;
448 printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
449 (clk->parent->rate / clkr->div));
451 return (clk->parent->rate / clkr->div);
455 * omap2_clksel_round_rate - find rounded rate for the given clock and rate
456 * @clk: OMAP struct clk to use
457 * @target_rate: desired clock rate
459 * Compatibility wrapper for OMAP clock framework
460 * Finds best target rate based on the source clock and possible dividers.
461 * rates. The divider array must be sorted with smallest divider first.
462 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
463 * they are only settable as part of virtual_prcm set.
465 * Returns the rounded clock rate or returns 0xffffffff on error.
467 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
471 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
475 /* Given a clock and a rate apply a clock specific rounding function */
476 long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
478 if (clk->round_rate != 0)
479 return clk->round_rate(clk, rate);
481 if (clk->flags & RATE_FIXED)
482 printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
483 "on fixed-rate clock %s\n", clk->name);
489 * omap2_clksel_to_divisor() - turn clksel field value into integer divider
490 * @clk: OMAP struct clk to use
491 * @field_val: register field value to find
493 * Given a struct clk of a rate-selectable clksel clock, and a register field
494 * value to search for, find the corresponding clock divisor. The register
495 * field value should be pre-masked and shifted down so the LSB is at bit 0
496 * before calling. Returns 0 on error
498 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
500 const struct clksel *clks;
501 const struct clksel_rate *clkr;
503 clks = omap2_get_clksel_by_parent(clk, clk->parent);
507 for (clkr = clks->rates; clkr->div; clkr++) {
508 if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
513 printk(KERN_ERR "clock: Could not find fieldval %d for "
514 "clock %s parent %s\n", field_val, clk->name,
523 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
524 * @clk: OMAP struct clk to use
525 * @div: integer divisor to search for
527 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
528 * find the corresponding register field value. The return register value is
529 * the value before left-shifting. Returns 0xffffffff on error
531 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
533 const struct clksel *clks;
534 const struct clksel_rate *clkr;
536 /* should never happen */
539 clks = omap2_get_clksel_by_parent(clk, clk->parent);
543 for (clkr = clks->rates; clkr->div; clkr++) {
544 if ((clkr->flags & cpu_mask) && (clkr->div == div))
549 printk(KERN_ERR "clock: Could not find divisor %d for "
550 "clock %s parent %s\n", div, clk->name,
559 * omap2_get_clksel - find clksel register addr & field mask for a clk
560 * @clk: struct clk to use
561 * @field_mask: ptr to u32 to store the register field mask
563 * Returns the address of the clksel register upon success or NULL on error.
565 void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
567 if (unlikely((clk->clksel_reg == 0) || (clk->clksel_mask == 0)))
570 *field_mask = clk->clksel_mask;
572 return clk->clksel_reg;
576 * omap2_clksel_get_divisor - get current divider applied to parent clock.
577 * @clk: OMAP struct clk to use.
579 * Returns the integer divisor upon success or 0 on error.
581 u32 omap2_clksel_get_divisor(struct clk *clk)
583 u32 field_mask, field_val;
584 void __iomem *div_addr;
586 div_addr = omap2_get_clksel(clk, &field_mask);
590 field_val = __raw_readl(div_addr) & field_mask;
591 field_val >>= __ffs(field_mask);
593 return omap2_clksel_to_divisor(clk, field_val);
596 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
598 u32 field_mask, field_val, validrate, new_div = 0;
599 void __iomem *div_addr;
601 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
602 if (validrate != rate)
605 div_addr = omap2_get_clksel(clk, &field_mask);
609 field_val = omap2_divisor_to_clksel(clk, new_div);
613 cm_rmw_reg_bits(field_mask, field_val << __ffs(field_mask), div_addr);
617 clk->rate = clk->parent->rate / new_div;
619 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
620 __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL);
628 /* Set the clock rate for a clock source */
629 int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
633 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
635 /* CONFIG_PARTICIPANT clocks are changed only in sets via the
636 rate table mechanism, driven by mpu_speed */
637 if (clk->flags & CONFIG_PARTICIPANT)
640 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
641 if (clk->set_rate != 0)
642 ret = clk->set_rate(clk, rate);
644 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
651 * Converts encoded control register address into a full address
652 * On error, *src_addr will be returned as 0.
654 static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
655 struct clk *src_clk, u32 *field_mask,
656 struct clk *clk, u32 *parent_div)
658 const struct clksel *clks;
659 const struct clksel_rate *clkr;
664 clks = omap2_get_clksel_by_parent(clk, src_clk);
668 for (clkr = clks->rates; clkr->div; clkr++) {
669 if (clkr->flags & (cpu_mask | DEFAULT_RATE))
670 break; /* Found the default rate for this platform */
674 printk(KERN_ERR "clock: Could not find default rate for "
675 "clock %s parent %s\n", clk->name,
676 src_clk->parent->name);
680 /* Should never happen. Add a clksel mask to the struct clk. */
681 WARN_ON(clk->clksel_mask == 0);
683 *field_mask = clk->clksel_mask;
684 *src_addr = clk->clksel_reg;
685 *parent_div = clkr->div;
690 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
692 void __iomem *src_addr;
693 u32 field_val, field_mask, reg_val, parent_div;
695 if (unlikely(clk->flags & CONFIG_PARTICIPANT))
701 field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
702 &field_mask, clk, &parent_div);
706 if (clk->usecount > 0)
707 _omap2_clk_disable(clk);
709 /* Set new source value (previous dividers if any in effect) */
710 reg_val = __raw_readl(src_addr) & ~field_mask;
711 reg_val |= (field_val << __ffs(field_mask));
712 __raw_writel(reg_val, src_addr);
715 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
716 __raw_writel(OMAP24XX_VALID_CONFIG,
717 OMAP24XX_PRCM_CLKCFG_CTRL);
721 if (clk->usecount > 0)
722 _omap2_clk_enable(clk);
724 clk->parent = new_parent;
726 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
727 clk->rate = new_parent->rate;
730 clk->rate /= parent_div;
732 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
733 clk->name, clk->parent->name, clk->rate);
735 if (unlikely(clk->flags & RATE_PROPAGATES))
741 /* DPLL rate rounding code */
744 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
745 * @clk: struct clk * of the DPLL
746 * @tolerance: maximum rate error tolerance
748 * Set the maximum DPLL rate error tolerance for the rate rounding
749 * algorithm. The rate tolerance is an attempt to balance DPLL power
750 * saving (the least divider value "n") vs. rate fidelity (the least
751 * difference between the desired DPLL target rate and the rounded
752 * rate out of the algorithm). So, increasing the tolerance is likely
753 * to decrease DPLL power consumption and increase DPLL rate error.
754 * Returns -EINVAL if provided a null clock ptr or a clk that is not a
755 * DPLL; or 0 upon success.
757 int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
759 if (!clk || !clk->dpll_data)
762 clk->dpll_data->rate_tolerance = tolerance;
767 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, unsigned int m, unsigned int n)
769 unsigned long long num;
771 num = (unsigned long long)parent_rate * m;
777 * _dpll_test_mult - test a DPLL multiplier value
778 * @m: pointer to the DPLL m (multiplier) value under test
779 * @n: current DPLL n (divider) value under test
780 * @new_rate: pointer to storage for the resulting rounded rate
781 * @target_rate: the desired DPLL rate
782 * @parent_rate: the DPLL's parent clock rate
784 * This code tests a DPLL multiplier value, ensuring that the
785 * resulting rate will not be higher than the target_rate, and that
786 * the multiplier value itself is valid for the DPLL. Initially, the
787 * integer pointed to by the m argument should be prescaled by
788 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
789 * a non-scaled m upon return. This non-scaled m will result in a
790 * new_rate as close as possible to target_rate (but not greater than
791 * target_rate) given the current (parent_rate, n, prescaled m)
792 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
793 * non-scaled m attempted to underflow, which can allow the calling
794 * function to bail out early; or 0 upon success.
796 static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
797 unsigned long target_rate,
798 unsigned long parent_rate)
800 int flags = 0, carry = 0;
802 /* Unscale m and round if necessary */
803 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
805 *m = (*m / DPLL_SCALE_FACTOR) + carry;
808 * The new rate must be <= the target rate to avoid programming
809 * a rate that is impossible for the hardware to handle
811 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
812 if (*new_rate > target_rate) {
817 /* Guard against m underflow */
818 if (*m < DPLL_MIN_MULTIPLIER) {
819 *m = DPLL_MIN_MULTIPLIER;
821 flags = DPLL_MULT_UNDERFLOW;
825 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
831 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
832 * @clk: struct clk * for a DPLL
833 * @target_rate: desired DPLL clock rate
835 * Given a DPLL, a desired target rate, and a rate tolerance, round
836 * the target rate to a possible, programmable rate for this DPLL.
837 * Rate tolerance is assumed to be set by the caller before this
838 * function is called. Attempts to select the minimum possible n
839 * within the tolerance to reduce power consumption. Stores the
840 * computed (m, n) in the DPLL's dpll_data structure so set_rate()
841 * will not need to call this (expensive) function again. Returns ~0
842 * if the target rate cannot be rounded, either because the rate is
843 * too low or because the rate tolerance is set too tightly; or the
844 * rounded rate upon success.
846 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
848 int m, n, r, e, scaled_max_m;
849 unsigned long scaled_rt_rp, new_rate;
850 int min_e = -1, min_e_m = -1, min_e_n = -1;
852 if (!clk || !clk->dpll_data)
855 pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
856 "%ld\n", clk->name, target_rate);
858 scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR);
859 scaled_max_m = clk->dpll_data->max_multiplier * DPLL_SCALE_FACTOR;
861 clk->dpll_data->last_rounded_rate = 0;
863 for (n = clk->dpll_data->max_divider; n >= DPLL_MIN_DIVIDER; n--) {
865 /* Compute the scaled DPLL multiplier, based on the divider */
866 m = scaled_rt_rp * n;
869 * Since we're counting n down, a m overflow means we can
870 * can immediately skip to the next n
872 if (m > scaled_max_m)
875 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
878 e = target_rate - new_rate;
879 pr_debug("clock: n = %d: m = %d: rate error is %d "
880 "(new_rate = %ld)\n", n, m, e, new_rate);
883 min_e >= (int)(abs(e) - clk->dpll_data->rate_tolerance)) {
888 pr_debug("clock: found new least error %d\n", min_e);
892 * Since we're counting n down, a m underflow means we
893 * can bail out completely (since as n decreases in
894 * the next iteration, there's no way that m can
895 * increase beyond the current m)
897 if (r & DPLL_MULT_UNDERFLOW)
902 pr_debug("clock: error: target rate or tolerance too low\n");
906 clk->dpll_data->last_rounded_m = min_e_m;
907 clk->dpll_data->last_rounded_n = min_e_n;
908 clk->dpll_data->last_rounded_rate =
909 _dpll_compute_new_rate(clk->parent->rate, min_e_m, min_e_n);
911 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
912 min_e, min_e_m, min_e_n);
913 pr_debug("clock: final rate: %ld (target rate: %ld)\n",
914 clk->dpll_data->last_rounded_rate, target_rate);
916 return clk->dpll_data->last_rounded_rate;
919 /*-------------------------------------------------------------------------
920 * Omap2 clock reset and init functions
921 *-------------------------------------------------------------------------*/
923 #ifdef CONFIG_OMAP_RESET_CLOCKS
924 void omap2_clk_disable_unused(struct clk *clk)
928 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
930 regval32 = __raw_readl(clk->enable_reg);
931 if ((regval32 & (1 << clk->enable_bit)) == v)
934 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
935 _omap2_clk_disable(clk);