2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/list.h>
21 #include <linux/errno.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
24 #include <linux/bitops.h>
27 #include <mach/clock.h>
28 #include <mach/clockdomain.h>
29 #include <mach/sram.h>
31 #include <mach/prcm.h>
32 #include <mach/control.h>
33 #include <asm/div64.h>
35 #include <mach/sdrc.h>
39 #include "prm-regbits-24xx.h"
41 #include "cm-regbits-24xx.h"
42 #include "cm-regbits-34xx.h"
44 #define MAX_CLOCK_ENABLE_WAIT 100000
46 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
47 #define DPLL_MIN_MULTIPLIER 1
48 #define DPLL_MIN_DIVIDER 1
50 /* Possible error results from _dpll_test_mult */
51 #define DPLL_MULT_UNDERFLOW (1 << 0)
54 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
55 * The higher the scale factor, the greater the risk of arithmetic overflow,
56 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
57 * must be a power of DPLL_SCALE_BASE.
59 #define DPLL_SCALE_FACTOR 64
60 #define DPLL_SCALE_BASE 2
61 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
62 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
64 /* Some OMAP2xxx CM_CLKSEL_PLL.ST_CORE_CLK bits - for omap2_get_dpll_rate() */
65 #define ST_CORE_CLK_REF 0x1
66 #define ST_CORE_CLK_32K 0x3
68 /* Bitmask to isolate the register type of clk.enable_reg */
69 #define PRCM_REGTYPE_MASK 0xf0
70 /* various CM register type options */
71 #define CM_FCLKEN_REGTYPE 0x00
72 #define CM_ICLKEN_REGTYPE 0x10
73 #define CM_IDLEST_REGTYPE 0x20
77 /*-------------------------------------------------------------------------
78 * OMAP2/3 specific clock functions
79 *-------------------------------------------------------------------------*/
82 * _omap2_clk_read_reg - read a clock register
85 * Given a struct clk *, returns the value of the clock's register.
87 static u32 _omap2_clk_read_reg(u16 reg_offset, struct clk *clk)
89 if (clk->prcm_mod & CLK_REG_IN_SCM)
90 return omap_ctrl_readl(reg_offset);
91 else if (clk->prcm_mod & CLK_REG_IN_PRM)
92 return prm_read_mod_reg(clk->prcm_mod & PRCM_MOD_ADDR_MASK,
95 return cm_read_mod_reg(clk->prcm_mod, reg_offset);
99 * _omap2_clk_write_reg - write a clock's register
100 * @v: value to write to the clock's enable_reg
103 * Given a register value @v and struct clk * @clk, writes the value of @v to
104 * the clock's enable register. No return value.
106 static void _omap2_clk_write_reg(u32 v, u16 reg_offset, struct clk *clk)
108 if (clk->prcm_mod & CLK_REG_IN_SCM)
109 omap_ctrl_writel(v, reg_offset);
110 else if (clk->prcm_mod & CLK_REG_IN_PRM)
111 prm_write_mod_reg(v, clk->prcm_mod & PRCM_MOD_ADDR_MASK,
114 cm_write_mod_reg(v, clk->prcm_mod, reg_offset);
119 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
120 * @clk: OMAP clock struct ptr to use
122 * Convert a clockdomain name stored in a struct clk 'clk' into a
123 * clockdomain pointer, and save it into the struct clk. Intended to be
124 * called during clk_register(). No return value.
126 void omap2_init_clk_clkdm(struct clk *clk)
128 struct clockdomain *clkdm;
130 if (!clk->clkdm.name) {
131 pr_err("clock: %s: missing clockdomain", clk->name);
135 clkdm = clkdm_lookup(clk->clkdm.name);
137 pr_debug("clock: associated clk %s to clkdm %s\n",
138 clk->name, clk->clkdm.name);
139 clk->clkdm.ptr = clkdm;
141 pr_err("clock: %s: could not associate to clkdm %s\n",
142 clk->name, clk->clkdm.name);
147 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
148 * @clk: OMAP clock struct ptr to use
150 * Given a pointer to a source-selectable struct clk, read the hardware
151 * register and determine what its parent is currently set to. Update the
152 * clk->parent field with the appropriate clk ptr.
154 void omap2_init_clksel_parent(struct clk *clk)
156 const struct clksel *clks;
157 const struct clksel_rate *clkr;
163 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
164 r >>= __ffs(clk->clksel_mask);
166 for (clks = clk->clksel; clks->parent && !found; clks++) {
167 for (clkr = clks->rates; clkr->div && !found; clkr++) {
168 if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
169 if (clk->parent != clks->parent) {
170 pr_debug("clock: inited %s parent "
172 clk->name, clks->parent->name,
174 clk->parent->name : "NULL"));
175 clk->parent = clks->parent;
183 printk(KERN_ERR "clock: init parent: could not find "
184 "regval %0x for clock %s\n", r, clk->name);
190 * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
191 * @clk: struct clk * of a DPLL
193 * DPLLs can be locked or bypassed - basically, enabled or disabled.
194 * When locked, the DPLL output depends on the M and N values. When
195 * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
196 * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
197 * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
198 * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
199 * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
200 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
201 * if the clock @clk is not a DPLL.
203 u32 omap2_get_dpll_rate(struct clk *clk)
206 u32 dpll_mult, dpll_div, v;
207 struct dpll_data *dd;
213 /* Return bypass rate if DPLL is bypassed */
214 v = __raw_readl(dd->idlest_reg) & dd->idlest_mask;
215 v >>= __ffs(dd->idlest_mask);
216 if (cpu_is_omap24xx()) {
218 if (v == ST_CORE_CLK_REF)
219 return clk->parent->rate; /* sys_clk */
220 else if (v == ST_CORE_CLK_32K)
223 } else if (cpu_is_omap34xx()) {
226 return dd->bypass_clk->rate;
230 v = __raw_readl(dd->mult_div1_reg);
231 dpll_mult = v & dd->mult_mask;
232 dpll_mult >>= __ffs(dd->mult_mask);
233 dpll_div = v & dd->div1_mask;
234 dpll_div >>= __ffs(dd->div1_mask);
236 dpll_clk = (long long)clk->parent->rate * dpll_mult;
237 do_div(dpll_clk, dpll_div + 1);
243 * Used for clocks that have the same value as the parent clock,
244 * divided by some factor
246 void omap2_fixed_divisor_recalc(struct clk *clk)
248 WARN_ON(!clk->fixed_div);
250 clk->rate = clk->parent->rate / clk->fixed_div;
252 if (clk->flags & RATE_PROPAGATES)
257 * omap2_wait_clock_ready - wait for clock to enable
258 * @prcm_mod: CM submodule offset from CM_BASE (e.g., "MPU_MOD")
259 * @reg_index: offset of CM register address from prcm_mod
260 * @mask: value to mask against to determine if the clock is active
261 * @name: name of the clock (for printk)
263 * Returns 1 if the clock enabled in time, or 0 if it failed to enable
264 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
266 int omap2_wait_clock_ready(s16 prcm_mod, u16 reg_index, u32 mask,
272 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
273 * 34xx reverses this, just to keep us on our toes
275 if (cpu_mask & (RATE_IN_242X | RATE_IN_243X))
277 else if (cpu_mask & RATE_IN_343X)
281 while (((cm_read_mod_reg(prcm_mod, reg_index) & mask) != ena) &&
282 (i++ < MAX_CLOCK_ENABLE_WAIT)) {
286 if (i < MAX_CLOCK_ENABLE_WAIT)
287 pr_debug("Clock %s stable after %d loops\n", name, i);
289 printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
290 name, MAX_CLOCK_ENABLE_WAIT);
292 return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
297 * Note: We don't need special code here for INVERT_ENABLE
298 * for the time being since INVERT_ENABLE only applies to clocks enabled by
301 * REVISIT: This code is ugly and does not belong here.
303 static void omap2_clk_wait_ready(struct clk *clk)
305 u32 other_bit, idlest_bit;
306 unsigned long reg, other_reg, idlest_reg, prcm_regid;
308 /* Only CM-controlled clocks affect module IDLEST */
309 if (clk->prcm_mod & ~PRCM_MOD_ADDR_MASK)
312 reg = (unsigned long)clk->enable_reg;
313 prcm_regid = reg & 0xff;
315 other_reg = reg & ~PRCM_REGTYPE_MASK;
317 /* If we are enabling an fclk, also test the iclk; and vice versa */
318 if (prcm_regid >= CM_FCLKEN1 && prcm_regid <= OMAP24XX_CM_FCLKEN2)
319 other_reg |= CM_ICLKEN_REGTYPE;
321 other_reg |= CM_FCLKEN_REGTYPE;
323 /* Covers most of the cases - a few exceptions are below */
324 other_bit = 1 << clk->enable_bit;
325 idlest_bit = other_bit;
327 /* 24xx: DSS and CAM have no idlest bits for their target agents */
328 if (cpu_is_omap24xx() && clk->prcm_mod == CORE_MOD &&
329 (reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
331 if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
332 clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
333 clk->enable_bit == OMAP24XX_EN_CAM_SHIFT)
338 /* REVISIT: What are the appropriate exclusions for 34XX? */
339 if (cpu_is_omap34xx()) {
342 if (clk->prcm_mod == CORE_MOD &&
344 clk->enable_bit == OMAP3430_EN_SSI_SHIFT) {
346 if (system_rev == OMAP3430_REV_ES1_0)
349 idlest_bit = OMAP3430ES2_ST_SSI_IDLE;
353 if (clk->prcm_mod == OMAP3430_DSS_MOD) {
355 /* 3430ES1 DSS has no target idlest bits */
356 if (system_rev == OMAP3430_REV_ES1_0)
360 * For 3430ES2+ DSS, only wait once (dss1_alwon_fclk,
361 * dss_l3_iclk, dss_l4_iclk) are enabled
363 if (clk->enable_bit != OMAP3430_EN_DSS1_SHIFT)
366 idlest_bit = OMAP3430ES2_ST_DSS_IDLE;
370 if (system_rev > OMAP3430_REV_ES1_0 &&
371 clk->prcm_mod == OMAP3430ES2_USBHOST_MOD) {
374 * The 120MHz clock apparently has nothing to do with
375 * USBHOST module accessibility
377 if (clk->enable_bit == OMAP3430ES2_EN_USBHOST2_SHIFT)
380 idlest_bit = OMAP3430ES2_ST_USBHOST_IDLE;
385 /* Check if both functional and interface clocks
387 if (!(__raw_readl((void __iomem *)other_reg) & other_bit))
390 idlest_reg = other_reg & ~PRCM_REGTYPE_MASK;
391 idlest_reg |= CM_IDLEST_REGTYPE;
393 idlest_reg &= 0xff; /* convert to PRCM register index */
395 omap2_wait_clock_ready(clk->prcm_mod, idlest_reg, idlest_bit,
399 /* Enables clock without considering parent dependencies or use count
400 * REVISIT: Maybe change this to use clk->enable like on omap1?
402 static int _omap2_clk_enable(struct clk *clk)
406 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
410 return clk->enable(clk);
412 if (unlikely(clk->enable_reg == NULL)) {
413 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
415 return 0; /* REVISIT: -EINVAL */
418 v = __raw_readl(clk->enable_reg);
419 if (clk->flags & INVERT_ENABLE)
420 v &= ~(1 << clk->enable_bit);
422 v |= (1 << clk->enable_bit);
423 __raw_writel(v, clk->enable_reg);
426 omap2_clk_wait_ready(clk);
431 /* Disables clock without considering parent dependencies or use count */
432 static void _omap2_clk_disable(struct clk *clk)
436 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
444 if (clk->enable_reg == NULL) {
446 * 'Independent' here refers to a clock which is not
447 * controlled by its parent.
449 printk(KERN_ERR "clock: clk_disable called on independent "
450 "clock %s which has no enable_reg\n", clk->name);
454 v = __raw_readl(clk->enable_reg);
455 if (clk->flags & INVERT_ENABLE)
456 v |= (1 << clk->enable_bit);
458 v &= ~(1 << clk->enable_bit);
459 __raw_writel(v, clk->enable_reg);
463 void omap2_clk_disable(struct clk *clk)
465 if (clk->usecount > 0 && !(--clk->usecount)) {
466 _omap2_clk_disable(clk);
468 omap2_clk_disable(clk->parent);
470 omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
475 int omap2_clk_enable(struct clk *clk)
479 if (clk->usecount++ == 0) {
481 ret = omap2_clk_enable(clk->parent);
489 omap2_clkdm_clk_enable(clk->clkdm.ptr, clk);
491 ret = _omap2_clk_enable(clk);
495 omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
498 omap2_clk_disable(clk->parent);
508 * Used for clocks that are part of CLKSEL_xyz governed clocks.
509 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
511 void omap2_clksel_recalc(struct clk *clk)
515 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
517 div = omap2_clksel_get_divisor(clk);
521 if (clk->rate == (clk->parent->rate / div))
523 clk->rate = clk->parent->rate / div;
525 pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
527 if (clk->flags & RATE_PROPAGATES)
532 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
533 * @clk: OMAP struct clk ptr to inspect
534 * @src_clk: OMAP struct clk ptr of the parent clk to search for
536 * Scan the struct clksel array associated with the clock to find
537 * the element associated with the supplied parent clock address.
538 * Returns a pointer to the struct clksel on success or NULL on error.
540 static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
543 const struct clksel *clks;
548 for (clks = clk->clksel; clks->parent; clks++) {
549 if (clks->parent == src_clk)
550 break; /* Found the requested parent */
554 printk(KERN_ERR "clock: Could not find parent clock %s in "
555 "clksel array of clock %s\n", src_clk->name,
564 * omap2_clksel_round_rate_div - find divisor for the given clock and rate
565 * @clk: OMAP struct clk to use
566 * @target_rate: desired clock rate
567 * @new_div: ptr to where we should store the divisor
569 * Finds 'best' divider value in an array based on the source and target
570 * rates. The divider array must be sorted with smallest divider first.
571 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
572 * they are only settable as part of virtual_prcm set.
574 * Returns the rounded clock rate or returns 0xffffffff on error.
576 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
579 unsigned long test_rate;
580 const struct clksel *clks;
581 const struct clksel_rate *clkr;
584 printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
585 clk->name, target_rate);
589 clks = omap2_get_clksel_by_parent(clk, clk->parent);
593 for (clkr = clks->rates; clkr->div; clkr++) {
594 if (!(clkr->flags & cpu_mask))
598 if (clkr->div <= last_div)
599 printk(KERN_ERR "clock: clksel_rate table not sorted "
600 "for clock %s", clk->name);
602 last_div = clkr->div;
604 test_rate = clk->parent->rate / clkr->div;
606 if (test_rate <= target_rate)
607 break; /* found it */
611 printk(KERN_ERR "clock: Could not find divisor for target "
612 "rate %ld for clock %s parent %s\n", target_rate,
613 clk->name, clk->parent->name);
617 *new_div = clkr->div;
619 printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
620 (clk->parent->rate / clkr->div));
622 return (clk->parent->rate / clkr->div);
626 * omap2_clksel_round_rate - find rounded rate for the given clock and rate
627 * @clk: OMAP struct clk to use
628 * @target_rate: desired clock rate
630 * Compatibility wrapper for OMAP clock framework
631 * Finds best target rate based on the source clock and possible dividers.
632 * rates. The divider array must be sorted with smallest divider first.
633 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
634 * they are only settable as part of virtual_prcm set.
636 * Returns the rounded clock rate or returns 0xffffffff on error.
638 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
642 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
646 /* Given a clock and a rate apply a clock specific rounding function */
647 long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
649 if (clk->round_rate != NULL)
650 return clk->round_rate(clk, rate);
652 if (clk->flags & RATE_FIXED)
653 printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
654 "on fixed-rate clock %s\n", clk->name);
660 * omap2_clksel_to_divisor() - turn clksel field value into integer divider
661 * @clk: OMAP struct clk to use
662 * @field_val: register field value to find
664 * Given a struct clk of a rate-selectable clksel clock, and a register field
665 * value to search for, find the corresponding clock divisor. The register
666 * field value should be pre-masked and shifted down so the LSB is at bit 0
667 * before calling. Returns 0 on error
669 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
671 const struct clksel *clks;
672 const struct clksel_rate *clkr;
674 clks = omap2_get_clksel_by_parent(clk, clk->parent);
678 for (clkr = clks->rates; clkr->div; clkr++) {
679 if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
684 printk(KERN_ERR "clock: Could not find fieldval %d for "
685 "clock %s parent %s\n", field_val, clk->name,
694 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
695 * @clk: OMAP struct clk to use
696 * @div: integer divisor to search for
698 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
699 * find the corresponding register field value. The return register value is
700 * the value before left-shifting. Returns 0xffffffff on error
702 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
704 const struct clksel *clks;
705 const struct clksel_rate *clkr;
707 /* should never happen */
710 clks = omap2_get_clksel_by_parent(clk, clk->parent);
714 for (clkr = clks->rates; clkr->div; clkr++) {
715 if ((clkr->flags & cpu_mask) && (clkr->div == div))
720 printk(KERN_ERR "clock: Could not find divisor %d for "
721 "clock %s parent %s\n", div, clk->name,
730 * omap2_get_clksel - find clksel register addr & field mask for a clk
731 * @clk: struct clk to use
732 * @field_mask: ptr to u32 to store the register field mask
734 * Returns the address of the clksel register upon success or NULL on error.
736 static void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
738 if (unlikely((clk->clksel_reg == NULL) || (clk->clksel_mask == NULL)))
741 *field_mask = clk->clksel_mask;
743 return clk->clksel_reg;
747 * omap2_clksel_get_divisor - get current divider applied to parent clock.
748 * @clk: OMAP struct clk to use.
750 * Returns the integer divisor upon success or 0 on error.
752 u32 omap2_clksel_get_divisor(struct clk *clk)
755 void __iomem *div_addr;
757 div_addr = omap2_get_clksel(clk, &field_mask);
758 if (div_addr == NULL)
761 v = __raw_readl(div_addr) & field_mask;
762 v >>= __ffs(field_mask);
764 return omap2_clksel_to_divisor(clk, v);
767 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
769 u32 field_mask, field_val, validrate, new_div = 0;
770 void __iomem *div_addr;
773 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
774 if (validrate != rate)
777 div_addr = omap2_get_clksel(clk, &field_mask);
778 if (div_addr == NULL)
781 field_val = omap2_divisor_to_clksel(clk, new_div);
785 v = __raw_readl(div_addr);
787 v |= field_val << __ffs(field_mask);
788 __raw_writel(v, div_addr);
792 clk->rate = clk->parent->rate / new_div;
794 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
795 prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
796 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
804 /* Set the clock rate for a clock source */
805 int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
809 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
811 /* CONFIG_PARTICIPANT clocks are changed only in sets via the
812 rate table mechanism, driven by mpu_speed */
813 if (clk->flags & CONFIG_PARTICIPANT)
816 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
817 if (clk->set_rate != NULL)
818 ret = clk->set_rate(clk, rate);
820 if (ret == 0 && (clk->flags & RATE_PROPAGATES))
827 * Converts encoded control register address into a full address
828 * On error, *src_addr will be returned as 0.
830 static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
831 struct clk *src_clk, u32 *field_mask,
832 struct clk *clk, u32 *parent_div)
834 const struct clksel *clks;
835 const struct clksel_rate *clkr;
840 clks = omap2_get_clksel_by_parent(clk, src_clk);
844 for (clkr = clks->rates; clkr->div; clkr++) {
845 if (clkr->flags & (cpu_mask | DEFAULT_RATE))
846 break; /* Found the default rate for this platform */
850 printk(KERN_ERR "clock: Could not find default rate for "
851 "clock %s parent %s\n", clk->name,
852 src_clk->parent->name);
856 /* Should never happen. Add a clksel mask to the struct clk. */
857 WARN_ON(clk->clksel_mask == 0);
859 *field_mask = clk->clksel_mask;
860 *src_addr = clk->clksel_reg;
861 *parent_div = clkr->div;
866 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
868 void __iomem *src_addr;
869 u32 field_val, field_mask, v, parent_div;
871 if (clk->flags & CONFIG_PARTICIPANT)
877 field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
878 &field_mask, clk, &parent_div);
879 if (src_addr == NULL)
882 if (clk->usecount > 0)
883 _omap2_clk_disable(clk);
885 /* Set new source value (previous dividers if any in effect) */
886 v = __raw_readl(src_addr) & ~field_mask;
887 v |= (field_val << __ffs(field_mask));
888 __raw_writel(v, src_addr);
891 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
892 prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
893 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
897 if (clk->usecount > 0)
898 _omap2_clk_enable(clk);
900 clk->parent = new_parent;
902 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
903 clk->rate = new_parent->rate;
906 clk->rate /= parent_div;
908 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
909 clk->name, clk->parent->name, clk->rate);
911 if (clk->flags & RATE_PROPAGATES)
917 /* DPLL rate rounding code */
920 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
921 * @clk: struct clk * of the DPLL
922 * @tolerance: maximum rate error tolerance
924 * Set the maximum DPLL rate error tolerance for the rate rounding
925 * algorithm. The rate tolerance is an attempt to balance DPLL power
926 * saving (the least divider value "n") vs. rate fidelity (the least
927 * difference between the desired DPLL target rate and the rounded
928 * rate out of the algorithm). So, increasing the tolerance is likely
929 * to decrease DPLL power consumption and increase DPLL rate error.
930 * Returns -EINVAL if provided a null clock ptr or a clk that is not a
931 * DPLL; or 0 upon success.
933 int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
935 if (!clk || !clk->dpll_data)
938 clk->dpll_data->rate_tolerance = tolerance;
943 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
944 unsigned int m, unsigned int n)
946 unsigned long long num;
948 num = (unsigned long long)parent_rate * m;
954 * _dpll_test_mult - test a DPLL multiplier value
955 * @m: pointer to the DPLL m (multiplier) value under test
956 * @n: current DPLL n (divider) value under test
957 * @new_rate: pointer to storage for the resulting rounded rate
958 * @target_rate: the desired DPLL rate
959 * @parent_rate: the DPLL's parent clock rate
961 * This code tests a DPLL multiplier value, ensuring that the
962 * resulting rate will not be higher than the target_rate, and that
963 * the multiplier value itself is valid for the DPLL. Initially, the
964 * integer pointed to by the m argument should be prescaled by
965 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
966 * a non-scaled m upon return. This non-scaled m will result in a
967 * new_rate as close as possible to target_rate (but not greater than
968 * target_rate) given the current (parent_rate, n, prescaled m)
969 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
970 * non-scaled m attempted to underflow, which can allow the calling
971 * function to bail out early; or 0 upon success.
973 static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
974 unsigned long target_rate,
975 unsigned long parent_rate)
977 int flags = 0, carry = 0;
979 /* Unscale m and round if necessary */
980 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
982 *m = (*m / DPLL_SCALE_FACTOR) + carry;
985 * The new rate must be <= the target rate to avoid programming
986 * a rate that is impossible for the hardware to handle
988 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
989 if (*new_rate > target_rate) {
994 /* Guard against m underflow */
995 if (*m < DPLL_MIN_MULTIPLIER) {
996 *m = DPLL_MIN_MULTIPLIER;
998 flags = DPLL_MULT_UNDERFLOW;
1002 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
1008 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
1009 * @clk: struct clk * for a DPLL
1010 * @target_rate: desired DPLL clock rate
1012 * Given a DPLL, a desired target rate, and a rate tolerance, round
1013 * the target rate to a possible, programmable rate for this DPLL.
1014 * Rate tolerance is assumed to be set by the caller before this
1015 * function is called. Attempts to select the minimum possible n
1016 * within the tolerance to reduce power consumption. Stores the
1017 * computed (m, n) in the DPLL's dpll_data structure so set_rate()
1018 * will not need to call this (expensive) function again. Returns ~0
1019 * if the target rate cannot be rounded, either because the rate is
1020 * too low or because the rate tolerance is set too tightly; or the
1021 * rounded rate upon success.
1023 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
1025 int m, n, r, e, scaled_max_m;
1026 unsigned long scaled_rt_rp, new_rate;
1027 int min_e = -1, min_e_m = -1, min_e_n = -1;
1029 if (!clk || !clk->dpll_data)
1032 pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
1033 "%ld\n", clk->name, target_rate);
1035 scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR);
1036 scaled_max_m = clk->dpll_data->max_multiplier * DPLL_SCALE_FACTOR;
1038 clk->dpll_data->last_rounded_rate = 0;
1040 for (n = clk->dpll_data->max_divider; n >= DPLL_MIN_DIVIDER; n--) {
1042 /* Compute the scaled DPLL multiplier, based on the divider */
1043 m = scaled_rt_rp * n;
1046 * Since we're counting n down, a m overflow means we can
1047 * can immediately skip to the next n
1049 if (m > scaled_max_m)
1052 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
1055 e = target_rate - new_rate;
1056 pr_debug("clock: n = %d: m = %d: rate error is %d "
1057 "(new_rate = %ld)\n", n, m, e, new_rate);
1060 min_e >= (int)(abs(e) - clk->dpll_data->rate_tolerance)) {
1065 pr_debug("clock: found new least error %d\n", min_e);
1069 * Since we're counting n down, a m underflow means we
1070 * can bail out completely (since as n decreases in
1071 * the next iteration, there's no way that m can
1072 * increase beyond the current m)
1074 if (r & DPLL_MULT_UNDERFLOW)
1079 pr_debug("clock: error: target rate or tolerance too low\n");
1083 clk->dpll_data->last_rounded_m = min_e_m;
1084 clk->dpll_data->last_rounded_n = min_e_n;
1085 clk->dpll_data->last_rounded_rate =
1086 _dpll_compute_new_rate(clk->parent->rate, min_e_m, min_e_n);
1088 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
1089 min_e, min_e_m, min_e_n);
1090 pr_debug("clock: final rate: %ld (target rate: %ld)\n",
1091 clk->dpll_data->last_rounded_rate, target_rate);
1093 return clk->dpll_data->last_rounded_rate;
1096 /*-------------------------------------------------------------------------
1097 * Omap2 clock reset and init functions
1098 *-------------------------------------------------------------------------*/
1100 #ifdef CONFIG_OMAP_RESET_CLOCKS
1101 void omap2_clk_disable_unused(struct clk *clk)
1105 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
1107 regval32 = __raw_readl(clk->enable_reg);
1108 if ((regval32 & (1 << clk->enable_bit)) == v)
1111 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
1112 _omap2_clk_disable(clk);