2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005 Texas Instruments Inc.
5 * Richard Woodruff <r-woodruff2@ti.com>
8 * Cleaned up and modified to use omap shared clock framework by
9 * Tony Lindgren <tony@atomide.com>
11 * Copyright (C) 2007 Texas Instruments, Inc.
12 * Copyright (C) 2007 Nokia Corporation
15 * Based on omap1 clock.c, Copyright (C) 2004 - 2005 Nokia corporation
16 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/device.h>
27 #include <linux/list.h>
28 #include <linux/errno.h>
29 #include <linux/delay.h>
30 #include <linux/clk.h>
34 #include <asm/arch/clock.h>
35 #include <asm/arch/sram.h>
36 #include <asm/arch/cpu.h>
37 #include <asm/div64.h>
43 #include "prm_regbits_24xx.h"
45 #include "cm_regbits_24xx.h"
47 #define MAX_CLOCK_ENABLE_WAIT 100000
51 /*-------------------------------------------------------------------------
52 * Omap2 specific clock functions
53 *-------------------------------------------------------------------------*/
55 u8 mask_to_shift(u32 mask)
61 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
62 * @clk: OMAP clock struct ptr to use
64 * Given a pointer to a source-selectable struct clk, read the hardware
65 * register and determine what its parent is currently set to. Update the
66 * clk->parent field with the appropriate clk ptr.
68 void omap2_init_clksel_parent(struct clk *clk)
70 const struct clksel *clks;
71 const struct clksel_rate *clkr;
77 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
78 r >>= mask_to_shift(clk->clksel_mask);
80 for (clks = clk->clksel; clks->parent && !found; clks++) {
81 for (clkr = clks->rates; clkr->div && !found; clkr++) {
82 if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
83 if (clk->parent != clks->parent) {
84 pr_debug("clock: inited %s parent "
86 clk->name, clks->parent->name,
88 clk->parent->name : "NULL"));
89 clk->parent = clks->parent;
97 printk(KERN_ERR "clock: init parent: could not find "
98 "regval %0x for clock %s\n", r, clk->name);
103 /* Returns the DPLL rate */
104 u32 omap2_get_dpll_rate(struct clk *clk)
107 u32 dpll_mult, dpll_div, dpll;
108 const struct dpll_data *dd;
111 /* REVISIT: What do we return on error? */
115 dpll = cm_read_reg(dd->mult_div1_reg);
116 dpll_mult = dpll & dd->mult_mask;
117 dpll_mult >>= mask_to_shift(dd->mult_mask);
118 dpll_div = dpll & dd->div1_mask;
119 dpll_div >>= mask_to_shift(dd->div1_mask);
121 dpll_clk = (long long)clk->parent->rate * dpll_mult;
122 do_div(dpll_clk, dpll_div + 1);
126 dpll = cm_read_reg(dd->div2_reg);
127 dpll_div = dpll & dd->div2_mask;
128 dpll_div >>= mask_to_shift(dd->div2_mask);
129 do_div(dpll_clk, dpll_div + 1);
136 * Used for clocks that have the same value as the parent clock,
137 * divided by some factor
139 void omap2_fixed_divisor_recalc(struct clk *clk)
141 WARN_ON(!clk->fixed_div);
143 clk->rate = clk->parent->rate / clk->fixed_div;
145 if (clk->flags & RATE_PROPAGATES)
150 * omap2_wait_clock_ready - wait for clock to enable
151 * @reg: physical address of clock IDLEST register
152 * @mask: value to mask against to determine if the clock is active
153 * @name: name of the clock (for printk)
155 * Returns 1 if the clock enabled in time, or 0 if it failed to enable
156 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
158 int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
164 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
165 * 34xx reverses this, just to keep us on our toes
167 if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) {
169 } else if (cpu_mask & RATE_IN_343X) {
174 while (((cm_read_reg(reg) & mask) != ena) &&
175 (i++ < MAX_CLOCK_ENABLE_WAIT)) {
179 if (i < MAX_CLOCK_ENABLE_WAIT)
180 pr_debug("Clock %s stable after %d loops\n", name, i);
182 printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
183 name, MAX_CLOCK_ENABLE_WAIT);
186 return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
191 * Note: We don't need special code here for INVERT_ENABLE
192 * for the time being since INVERT_ENABLE only applies to clocks enabled by
195 static void omap2_clk_wait_ready(struct clk *clk)
197 void __iomem *reg, *other_reg, *st_reg;
201 * REVISIT: This code is pretty ugly. It would be nice to generalize
202 * it and pull it into struct clk itself somehow.
204 reg = clk->enable_reg;
205 if (reg == OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1) ||
206 reg == OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2))
207 other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x10); /* CM_ICLKEN* */
208 else if (reg == OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1) ||
209 reg == OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2))
210 other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x00); /* CM_FCLKEN* */
214 /* REVISIT: What are the appropriate exclusions for 34XX? */
215 /* No check for DSS or cam clocks */
216 if (cpu_is_omap24xx() && ((u32)reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
217 if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
218 clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
219 clk->enable_bit == OMAP24XX_EN_CAM_SHIFT)
223 /* Check if both functional and interface clocks
225 bit = 1 << clk->enable_bit;
226 if (!(cm_read_reg(other_reg) & bit))
228 st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
230 omap2_wait_clock_ready(st_reg, bit, clk->name);
233 /* Enables clock without considering parent dependencies or use count
234 * REVISIT: Maybe change this to use clk->enable like on omap1?
236 int _omap2_clk_enable(struct clk *clk)
240 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
244 return clk->enable(clk);
246 if (unlikely(clk->enable_reg == 0)) {
247 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
249 return 0; /* REVISIT: -EINVAL */
252 regval32 = cm_read_reg(clk->enable_reg);
253 if (clk->flags & INVERT_ENABLE)
254 regval32 &= ~(1 << clk->enable_bit);
256 regval32 |= (1 << clk->enable_bit);
257 cm_write_reg(regval32, clk->enable_reg);
260 omap2_clk_wait_ready(clk);
265 /* Disables clock without considering parent dependencies or use count */
266 void _omap2_clk_disable(struct clk *clk)
270 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
278 if (clk->enable_reg == 0) {
280 * 'Independent' here refers to a clock which is not
281 * controlled by its parent.
283 printk(KERN_ERR "clock: clk_disable called on independent "
284 "clock %s which has no enable_reg\n", clk->name);
288 regval32 = cm_read_reg(clk->enable_reg);
289 if (clk->flags & INVERT_ENABLE)
290 regval32 |= (1 << clk->enable_bit);
292 regval32 &= ~(1 << clk->enable_bit);
293 cm_write_reg(regval32, clk->enable_reg);
297 void omap2_clk_disable(struct clk *clk)
299 if (clk->usecount > 0 && !(--clk->usecount)) {
300 _omap2_clk_disable(clk);
301 if (likely((u32)clk->parent))
302 omap2_clk_disable(clk->parent);
306 int omap2_clk_enable(struct clk *clk)
310 if (clk->usecount++ == 0) {
311 if (likely((u32)clk->parent))
312 ret = omap2_clk_enable(clk->parent);
314 if (unlikely(ret != 0)) {
319 ret = _omap2_clk_enable(clk);
321 if (unlikely(ret != 0) && clk->parent) {
322 omap2_clk_disable(clk->parent);
331 * Used for clocks that are part of CLKSEL_xyz governed clocks.
332 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
334 void omap2_clksel_recalc(struct clk *clk)
338 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
340 div = omap2_clksel_get_divisor(clk);
344 if (unlikely(clk->rate == clk->parent->rate / div))
346 clk->rate = clk->parent->rate / div;
348 pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
350 if (unlikely(clk->flags & RATE_PROPAGATES))
355 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
356 * @clk: OMAP struct clk ptr to inspect
357 * @src_clk: OMAP struct clk ptr of the parent clk to search for
359 * Scan the struct clksel array associated with the clock to find
360 * the element associated with the supplied parent clock address.
361 * Returns a pointer to the struct clksel on success or NULL on error.
363 const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
366 const struct clksel *clks;
371 for (clks = clk->clksel; clks->parent; clks++) {
372 if (clks->parent == src_clk)
373 break; /* Found the requested parent */
377 printk(KERN_ERR "clock: Could not find parent clock %s in "
378 "clksel array of clock %s\n", src_clk->name,
387 * omap2_clksel_round_rate_div - find divisor for the given clock and rate
388 * @clk: OMAP struct clk to use
389 * @target_rate: desired clock rate
390 * @new_div: ptr to where we should store the divisor
392 * Finds 'best' divider value in an array based on the source and target
393 * rates. The divider array must be sorted with smallest divider first.
394 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
395 * they are only settable as part of virtual_prcm set.
397 * Returns the rounded clock rate or returns 0xffffffff on error.
399 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
402 unsigned long test_rate;
403 const struct clksel *clks;
404 const struct clksel_rate *clkr;
407 printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
408 clk->name, target_rate);
412 clks = omap2_get_clksel_by_parent(clk, clk->parent);
416 for (clkr = clks->rates; clkr->div; clkr++) {
417 if (!(clkr->flags & cpu_mask))
421 if (clkr->div <= last_div)
422 printk(KERN_ERR "clock: clksel_rate table not sorted "
423 "for clock %s", clk->name);
425 last_div = clkr->div;
427 test_rate = clk->parent->rate / clkr->div;
429 if (test_rate <= target_rate)
430 break; /* found it */
434 printk(KERN_ERR "clock: Could not find divisor for target "
435 "rate %ld for clock %s parent %s\n", target_rate,
436 clk->name, clk->parent->name);
440 *new_div = clkr->div;
442 printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
443 (clk->parent->rate / clkr->div));
445 return (clk->parent->rate / clkr->div);
449 * omap2_clksel_round_rate - find rounded rate for the given clock and rate
450 * @clk: OMAP struct clk to use
451 * @target_rate: desired clock rate
453 * Compatibility wrapper for OMAP clock framework
454 * Finds best target rate based on the source clock and possible dividers.
455 * rates. The divider array must be sorted with smallest divider first.
456 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
457 * they are only settable as part of virtual_prcm set.
459 * Returns the rounded clock rate or returns 0xffffffff on error.
461 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
465 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
469 /* Given a clock and a rate apply a clock specific rounding function */
470 long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
472 if (clk->round_rate != 0)
473 return clk->round_rate(clk, rate);
475 if (clk->flags & RATE_FIXED)
476 printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
477 "on fixed-rate clock %s\n", clk->name);
483 * omap2_clksel_to_divisor() - turn clksel field value into integer divider
484 * @clk: OMAP struct clk to use
485 * @field_val: register field value to find
487 * Given a struct clk of a rate-selectable clksel clock, and a register field
488 * value to search for, find the corresponding clock divisor. The register
489 * field value should be pre-masked and shifted down so the LSB is at bit 0
490 * before calling. Returns 0 on error
492 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
494 const struct clksel *clks;
495 const struct clksel_rate *clkr;
497 clks = omap2_get_clksel_by_parent(clk, clk->parent);
501 for (clkr = clks->rates; clkr->div; clkr++) {
502 if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
507 printk(KERN_ERR "clock: Could not find fieldval %d for "
508 "clock %s parent %s\n", field_val, clk->name,
517 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
518 * @clk: OMAP struct clk to use
519 * @div: integer divisor to search for
521 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
522 * find the corresponding register field value. The return register value is
523 * the value before left-shifting. Returns 0xffffffff on error
525 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
527 const struct clksel *clks;
528 const struct clksel_rate *clkr;
530 /* should never happen */
533 clks = omap2_get_clksel_by_parent(clk, clk->parent);
537 for (clkr = clks->rates; clkr->div; clkr++) {
538 if ((clkr->flags & cpu_mask) && (clkr->div == div))
543 printk(KERN_ERR "clock: Could not find divisor %d for "
544 "clock %s parent %s\n", div, clk->name,
553 * omap2_get_clksel - find clksel register addr & field mask for a clk
554 * @clk: struct clk to use
555 * @field_mask: ptr to u32 to store the register field mask
557 * Returns the address of the clksel register upon success or NULL on error.
559 void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
561 if (unlikely((clk->clksel_reg == 0) || (clk->clksel_mask == 0)))
564 *field_mask = clk->clksel_mask;
566 return clk->clksel_reg;
570 * omap2_clksel_get_divisor - get current divider applied to parent clock.
571 * @clk: OMAP struct clk to use.
573 * Returns the integer divisor upon success or 0 on error.
575 u32 omap2_clksel_get_divisor(struct clk *clk)
577 u32 field_mask, field_val;
578 void __iomem *div_addr;
580 div_addr = omap2_get_clksel(clk, &field_mask);
584 field_val = cm_read_reg(div_addr) & field_mask;
585 field_val >>= mask_to_shift(field_mask);
587 return omap2_clksel_to_divisor(clk, field_val);
590 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
592 u32 field_mask, field_val, reg_val, validrate, new_div = 0;
593 void __iomem *div_addr;
595 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
596 if (validrate != rate)
599 div_addr = omap2_get_clksel(clk, &field_mask);
603 field_val = omap2_divisor_to_clksel(clk, new_div);
607 reg_val = cm_read_reg(div_addr);
608 reg_val &= ~field_mask;
609 reg_val |= (field_val << mask_to_shift(field_mask));
610 cm_write_reg(reg_val, div_addr);
613 clk->rate = clk->parent->rate / new_div;
615 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
616 prm_write_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL);
624 /* Set the clock rate for a clock source */
625 int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
629 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
631 /* CONFIG_PARTICIPANT clocks are changed only in sets via the
632 rate table mechanism, driven by mpu_speed */
633 if (clk->flags & CONFIG_PARTICIPANT)
636 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
637 if (clk->set_rate != 0)
638 ret = clk->set_rate(clk, rate);
640 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
647 * Converts encoded control register address into a full address
648 * On error, *src_addr will be returned as 0.
650 static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
651 struct clk *src_clk, u32 *field_mask,
652 struct clk *clk, u32 *parent_div)
654 const struct clksel *clks;
655 const struct clksel_rate *clkr;
660 clks = omap2_get_clksel_by_parent(clk, src_clk);
664 for (clkr = clks->rates; clkr->div; clkr++) {
665 if (clkr->flags & (cpu_mask | DEFAULT_RATE))
666 break; /* Found the default rate for this platform */
670 printk(KERN_ERR "clock: Could not find default rate for "
671 "clock %s parent %s\n", clk->name,
672 src_clk->parent->name);
676 /* Should never happen. Add a clksel mask to the struct clk. */
677 WARN_ON(clk->clksel_mask == 0);
679 *field_mask = clk->clksel_mask;
680 *src_addr = clk->clksel_reg;
681 *parent_div = clkr->div;
686 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
688 void __iomem *src_addr;
689 u32 field_val, field_mask, reg_val, parent_div;
691 if (unlikely(clk->flags & CONFIG_PARTICIPANT))
697 field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
698 &field_mask, clk, &parent_div);
702 if (clk->usecount > 0)
703 _omap2_clk_disable(clk);
705 /* Set new source value (previous dividers if any in effect) */
706 reg_val = __raw_readl(src_addr) & ~field_mask;
707 reg_val |= (field_val << mask_to_shift(field_mask));
708 __raw_writel(reg_val, src_addr);
711 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
712 prm_write_reg(OMAP24XX_VALID_CONFIG,
713 OMAP24XX_PRCM_CLKCFG_CTRL);
717 if (clk->usecount > 0)
718 _omap2_clk_enable(clk);
720 clk->parent = new_parent;
722 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
723 clk->rate = new_parent->rate;
726 clk->rate /= parent_div;
728 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
729 clk->name, clk->parent->name, clk->rate);
731 if (unlikely(clk->flags & RATE_PROPAGATES))
737 /*-------------------------------------------------------------------------
738 * Omap2 clock reset and init functions
739 *-------------------------------------------------------------------------*/
741 #ifdef CONFIG_OMAP_RESET_CLOCKS
742 void omap2_clk_disable_unused(struct clk *clk)
746 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
748 regval32 = cm_read_reg(clk->enable_reg);
749 if ((regval32 & (1 << clk->enable_bit)) == v)
752 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
753 _omap2_clk_disable(clk);