2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/list.h>
21 #include <linux/errno.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
24 #include <linux/bitops.h>
27 #include <mach/clock.h>
28 #include <mach/clockdomain.h>
29 #include <mach/sram.h>
31 #include <mach/prcm.h>
32 #include <asm/div64.h>
34 #include <mach/sdrc.h>
38 #include "prm-regbits-24xx.h"
40 #include "cm-regbits-24xx.h"
41 #include "cm-regbits-34xx.h"
43 #define MAX_CLOCK_ENABLE_WAIT 100000
45 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
46 #define DPLL_MIN_MULTIPLIER 1
47 #define DPLL_MIN_DIVIDER 1
49 /* Possible error results from _dpll_test_mult */
50 #define DPLL_MULT_UNDERFLOW (1 << 0)
53 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
54 * The higher the scale factor, the greater the risk of arithmetic overflow,
55 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
56 * must be a power of DPLL_SCALE_BASE.
58 #define DPLL_SCALE_FACTOR 64
59 #define DPLL_SCALE_BASE 2
60 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
61 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
65 /*-------------------------------------------------------------------------
66 * OMAP2/3 specific clock functions
67 *-------------------------------------------------------------------------*/
70 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
71 * @clk: OMAP clock struct ptr to use
73 * Convert a clockdomain name stored in a struct clk 'clk' into a
74 * clockdomain pointer, and save it into the struct clk. Intended to be
75 * called during clk_register(). No return value.
77 void omap2_init_clk_clkdm(struct clk *clk)
79 struct clockdomain *clkdm;
81 if (!clk->clkdm.name) {
82 pr_err("clock: %s: missing clockdomain", clk->name);
86 clkdm = clkdm_lookup(clk->clkdm.name);
88 pr_debug("clock: associated clk %s to clkdm %s\n",
89 clk->name, clk->clkdm.name);
90 clk->clkdm.ptr = clkdm;
92 pr_err("clock: %s: could not associate to clkdm %s\n",
93 clk->name, clk->clkdm.name);
98 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
99 * @clk: OMAP clock struct ptr to use
101 * Given a pointer to a source-selectable struct clk, read the hardware
102 * register and determine what its parent is currently set to. Update the
103 * clk->parent field with the appropriate clk ptr.
105 void omap2_init_clksel_parent(struct clk *clk)
107 const struct clksel *clks;
108 const struct clksel_rate *clkr;
114 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
115 r >>= __ffs(clk->clksel_mask);
117 for (clks = clk->clksel; clks->parent && !found; clks++) {
118 for (clkr = clks->rates; clkr->div && !found; clkr++) {
119 if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
120 if (clk->parent != clks->parent) {
121 pr_debug("clock: inited %s parent "
123 clk->name, clks->parent->name,
125 clk->parent->name : "NULL"));
126 clk->parent = clks->parent;
134 printk(KERN_ERR "clock: init parent: could not find "
135 "regval %0x for clock %s\n", r, clk->name);
140 /* Returns the DPLL rate */
141 u32 omap2_get_dpll_rate(struct clk *clk)
144 u32 dpll_mult, dpll_div, dpll;
145 struct dpll_data *dd;
148 /* REVISIT: What do we return on error? */
152 dpll = __raw_readl(dd->mult_div1_reg);
153 dpll_mult = dpll & dd->mult_mask;
154 dpll_mult >>= __ffs(dd->mult_mask);
155 dpll_div = dpll & dd->div1_mask;
156 dpll_div >>= __ffs(dd->div1_mask);
158 dpll_clk = (long long)clk->parent->rate * dpll_mult;
159 do_div(dpll_clk, dpll_div + 1);
165 * Used for clocks that have the same value as the parent clock,
166 * divided by some factor
168 void omap2_fixed_divisor_recalc(struct clk *clk)
170 WARN_ON(!clk->fixed_div);
172 clk->rate = clk->parent->rate / clk->fixed_div;
174 if (clk->flags & RATE_PROPAGATES)
179 * omap2_wait_clock_ready - wait for clock to enable
180 * @reg: physical address of clock IDLEST register
181 * @mask: value to mask against to determine if the clock is active
182 * @name: name of the clock (for printk)
184 * Returns 1 if the clock enabled in time, or 0 if it failed to enable
185 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
187 int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
193 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
194 * 34xx reverses this, just to keep us on our toes
196 if (cpu_mask & (RATE_IN_242X | RATE_IN_243X))
198 else if (cpu_mask & RATE_IN_343X)
202 while (((__raw_readl(reg) & mask) != ena) &&
203 (i++ < MAX_CLOCK_ENABLE_WAIT)) {
207 if (i < MAX_CLOCK_ENABLE_WAIT)
208 pr_debug("Clock %s stable after %d loops\n", name, i);
210 printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
211 name, MAX_CLOCK_ENABLE_WAIT);
214 return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
219 * Note: We don't need special code here for INVERT_ENABLE
220 * for the time being since INVERT_ENABLE only applies to clocks enabled by
223 * REVISIT: This code is ugly and does not belong here.
225 static void omap2_clk_wait_ready(struct clk *clk)
227 u32 other_bit, idlest_bit;
228 unsigned long reg, other_reg, idlest_reg, prcm_mod, prcm_regid;
230 reg = (unsigned long)clk->enable_reg;
231 prcm_mod = reg & ~0xff;
232 prcm_regid = reg & 0xff;
234 if (prcm_regid >= CM_FCLKEN1 && prcm_regid <= OMAP24XX_CM_FCLKEN2)
235 other_reg = ((reg & ~0xf0) | 0x10); /* CM_ICLKEN* */
236 else if (prcm_regid >= CM_ICLKEN1 && prcm_regid <= OMAP24XX_CM_ICLKEN4)
237 other_reg = ((reg & ~0xf0) | 0x00); /* CM_FCLKEN* */
241 /* Covers most of the cases - a few exceptions are below */
242 other_bit = 1 << clk->enable_bit;
243 idlest_bit = other_bit;
245 /* 24xx: DSS and CAM have no idlest bits for their target agents */
246 if (cpu_is_omap24xx() &&
247 (prcm_mod == OMAP2420_CM_REGADDR(CORE_MOD, 0) ||
248 prcm_mod == OMAP2430_CM_REGADDR(CORE_MOD, 0)) &&
249 (reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
251 if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
252 clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
253 clk->enable_bit == OMAP24XX_EN_CAM_SHIFT)
258 /* REVISIT: What are the appropriate exclusions for 34XX? */
259 if (cpu_is_omap34xx()) {
262 if (prcm_mod == OMAP34XX_CM_REGADDR(CORE_MOD, 0) &&
264 clk->enable_bit == OMAP3430_EN_SSI_SHIFT) {
266 if (system_rev == OMAP3430_REV_ES1_0)
269 idlest_bit = OMAP3430ES2_ST_SSI_IDLE;
273 if (prcm_mod == OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0)) {
275 /* 3430ES1 DSS has no target idlest bits */
276 if (system_rev == OMAP3430_REV_ES1_0)
280 * For 3430ES2+ DSS, only wait once (dss1_alwon_fclk,
281 * dss_l3_iclk, dss_l4_iclk) are enabled
283 if (clk->enable_bit != OMAP3430_EN_DSS1_SHIFT)
286 idlest_bit = OMAP3430ES2_ST_DSS_IDLE;
290 if (system_rev > OMAP3430_REV_ES1_0 &&
291 prcm_mod == OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, 0)) {
294 * The 120MHz clock apparently has nothing to do with
295 * USBHOST module accessibility
297 if (clk->enable_bit == OMAP3430ES2_EN_USBHOST2_SHIFT)
300 idlest_bit = OMAP3430ES2_ST_USBHOST_IDLE;
305 /* Check if both functional and interface clocks
307 if (!(__raw_readl((void __iomem *)other_reg) & other_bit))
310 idlest_reg = ((other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
312 omap2_wait_clock_ready((void __iomem *)idlest_reg, idlest_bit,
316 /* Enables clock without considering parent dependencies or use count
317 * REVISIT: Maybe change this to use clk->enable like on omap1?
319 static int _omap2_clk_enable(struct clk *clk)
323 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
327 return clk->enable(clk);
329 if (unlikely(clk->enable_reg == NULL)) {
330 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
332 return 0; /* REVISIT: -EINVAL */
335 regval32 = __raw_readl(clk->enable_reg);
336 if (clk->flags & INVERT_ENABLE)
337 regval32 &= ~(1 << clk->enable_bit);
339 regval32 |= (1 << clk->enable_bit);
340 __raw_writel(regval32, clk->enable_reg);
343 omap2_clk_wait_ready(clk);
348 /* Disables clock without considering parent dependencies or use count */
349 static void _omap2_clk_disable(struct clk *clk)
353 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
361 if (clk->enable_reg == NULL) {
363 * 'Independent' here refers to a clock which is not
364 * controlled by its parent.
366 printk(KERN_ERR "clock: clk_disable called on independent "
367 "clock %s which has no enable_reg\n", clk->name);
371 regval32 = __raw_readl(clk->enable_reg);
372 if (clk->flags & INVERT_ENABLE)
373 regval32 |= (1 << clk->enable_bit);
375 regval32 &= ~(1 << clk->enable_bit);
376 __raw_writel(regval32, clk->enable_reg);
380 void omap2_clk_disable(struct clk *clk)
382 if (clk->usecount > 0 && !(--clk->usecount)) {
383 _omap2_clk_disable(clk);
385 omap2_clk_disable(clk->parent);
387 omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
392 int omap2_clk_enable(struct clk *clk)
396 if (clk->usecount++ == 0) {
398 ret = omap2_clk_enable(clk->parent);
406 omap2_clkdm_clk_enable(clk->clkdm.ptr, clk);
408 ret = _omap2_clk_enable(clk);
412 omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
415 omap2_clk_disable(clk->parent);
425 * Used for clocks that are part of CLKSEL_xyz governed clocks.
426 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
428 void omap2_clksel_recalc(struct clk *clk)
432 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
434 div = omap2_clksel_get_divisor(clk);
438 if (clk->rate == (clk->parent->rate / div))
440 clk->rate = clk->parent->rate / div;
442 pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
444 if (clk->flags & RATE_PROPAGATES)
449 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
450 * @clk: OMAP struct clk ptr to inspect
451 * @src_clk: OMAP struct clk ptr of the parent clk to search for
453 * Scan the struct clksel array associated with the clock to find
454 * the element associated with the supplied parent clock address.
455 * Returns a pointer to the struct clksel on success or NULL on error.
457 static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
460 const struct clksel *clks;
465 for (clks = clk->clksel; clks->parent; clks++) {
466 if (clks->parent == src_clk)
467 break; /* Found the requested parent */
471 printk(KERN_ERR "clock: Could not find parent clock %s in "
472 "clksel array of clock %s\n", src_clk->name,
481 * omap2_clksel_round_rate_div - find divisor for the given clock and rate
482 * @clk: OMAP struct clk to use
483 * @target_rate: desired clock rate
484 * @new_div: ptr to where we should store the divisor
486 * Finds 'best' divider value in an array based on the source and target
487 * rates. The divider array must be sorted with smallest divider first.
488 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
489 * they are only settable as part of virtual_prcm set.
491 * Returns the rounded clock rate or returns 0xffffffff on error.
493 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
496 unsigned long test_rate;
497 const struct clksel *clks;
498 const struct clksel_rate *clkr;
501 printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
502 clk->name, target_rate);
506 clks = omap2_get_clksel_by_parent(clk, clk->parent);
510 for (clkr = clks->rates; clkr->div; clkr++) {
511 if (!(clkr->flags & cpu_mask))
515 if (clkr->div <= last_div)
516 printk(KERN_ERR "clock: clksel_rate table not sorted "
517 "for clock %s", clk->name);
519 last_div = clkr->div;
521 test_rate = clk->parent->rate / clkr->div;
523 if (test_rate <= target_rate)
524 break; /* found it */
528 printk(KERN_ERR "clock: Could not find divisor for target "
529 "rate %ld for clock %s parent %s\n", target_rate,
530 clk->name, clk->parent->name);
534 *new_div = clkr->div;
536 printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
537 (clk->parent->rate / clkr->div));
539 return (clk->parent->rate / clkr->div);
543 * omap2_clksel_round_rate - find rounded rate for the given clock and rate
544 * @clk: OMAP struct clk to use
545 * @target_rate: desired clock rate
547 * Compatibility wrapper for OMAP clock framework
548 * Finds best target rate based on the source clock and possible dividers.
549 * rates. The divider array must be sorted with smallest divider first.
550 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
551 * they are only settable as part of virtual_prcm set.
553 * Returns the rounded clock rate or returns 0xffffffff on error.
555 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
559 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
563 /* Given a clock and a rate apply a clock specific rounding function */
564 long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
566 if (clk->round_rate != NULL)
567 return clk->round_rate(clk, rate);
569 if (clk->flags & RATE_FIXED)
570 printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
571 "on fixed-rate clock %s\n", clk->name);
577 * omap2_clksel_to_divisor() - turn clksel field value into integer divider
578 * @clk: OMAP struct clk to use
579 * @field_val: register field value to find
581 * Given a struct clk of a rate-selectable clksel clock, and a register field
582 * value to search for, find the corresponding clock divisor. The register
583 * field value should be pre-masked and shifted down so the LSB is at bit 0
584 * before calling. Returns 0 on error
586 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
588 const struct clksel *clks;
589 const struct clksel_rate *clkr;
591 clks = omap2_get_clksel_by_parent(clk, clk->parent);
595 for (clkr = clks->rates; clkr->div; clkr++) {
596 if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
601 printk(KERN_ERR "clock: Could not find fieldval %d for "
602 "clock %s parent %s\n", field_val, clk->name,
611 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
612 * @clk: OMAP struct clk to use
613 * @div: integer divisor to search for
615 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
616 * find the corresponding register field value. The return register value is
617 * the value before left-shifting. Returns 0xffffffff on error
619 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
621 const struct clksel *clks;
622 const struct clksel_rate *clkr;
624 /* should never happen */
627 clks = omap2_get_clksel_by_parent(clk, clk->parent);
631 for (clkr = clks->rates; clkr->div; clkr++) {
632 if ((clkr->flags & cpu_mask) && (clkr->div == div))
637 printk(KERN_ERR "clock: Could not find divisor %d for "
638 "clock %s parent %s\n", div, clk->name,
647 * omap2_get_clksel - find clksel register addr & field mask for a clk
648 * @clk: struct clk to use
649 * @field_mask: ptr to u32 to store the register field mask
651 * Returns the address of the clksel register upon success or NULL on error.
653 static void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
655 if (unlikely((clk->clksel_reg == NULL) || (clk->clksel_mask == NULL)))
658 *field_mask = clk->clksel_mask;
660 return clk->clksel_reg;
664 * omap2_clksel_get_divisor - get current divider applied to parent clock.
665 * @clk: OMAP struct clk to use.
667 * Returns the integer divisor upon success or 0 on error.
669 u32 omap2_clksel_get_divisor(struct clk *clk)
671 u32 field_mask, field_val;
672 void __iomem *div_addr;
674 div_addr = omap2_get_clksel(clk, &field_mask);
675 if (div_addr == NULL)
678 field_val = __raw_readl(div_addr) & field_mask;
679 field_val >>= __ffs(field_mask);
681 return omap2_clksel_to_divisor(clk, field_val);
684 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
686 u32 field_mask, field_val, validrate, new_div = 0;
687 void __iomem *div_addr;
690 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
691 if (validrate != rate)
694 div_addr = omap2_get_clksel(clk, &field_mask);
695 if (div_addr == NULL)
698 field_val = omap2_divisor_to_clksel(clk, new_div);
702 v = __raw_readl(div_addr);
704 v |= field_val << __ffs(field_mask);
705 __raw_writel(v, div_addr);
709 clk->rate = clk->parent->rate / new_div;
711 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
712 prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
713 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
721 /* Set the clock rate for a clock source */
722 int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
726 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
728 /* CONFIG_PARTICIPANT clocks are changed only in sets via the
729 rate table mechanism, driven by mpu_speed */
730 if (clk->flags & CONFIG_PARTICIPANT)
733 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
734 if (clk->set_rate != NULL)
735 ret = clk->set_rate(clk, rate);
737 if (ret == 0 && (clk->flags & RATE_PROPAGATES))
744 * Converts encoded control register address into a full address
745 * On error, *src_addr will be returned as 0.
747 static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
748 struct clk *src_clk, u32 *field_mask,
749 struct clk *clk, u32 *parent_div)
751 const struct clksel *clks;
752 const struct clksel_rate *clkr;
757 clks = omap2_get_clksel_by_parent(clk, src_clk);
761 for (clkr = clks->rates; clkr->div; clkr++) {
762 if (clkr->flags & (cpu_mask | DEFAULT_RATE))
763 break; /* Found the default rate for this platform */
767 printk(KERN_ERR "clock: Could not find default rate for "
768 "clock %s parent %s\n", clk->name,
769 src_clk->parent->name);
773 /* Should never happen. Add a clksel mask to the struct clk. */
774 WARN_ON(clk->clksel_mask == 0);
776 *field_mask = clk->clksel_mask;
777 *src_addr = clk->clksel_reg;
778 *parent_div = clkr->div;
783 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
785 void __iomem *src_addr;
786 u32 field_val, field_mask, reg_val, parent_div;
788 if (clk->flags & CONFIG_PARTICIPANT)
794 field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
795 &field_mask, clk, &parent_div);
796 if (src_addr == NULL)
799 if (clk->usecount > 0)
800 _omap2_clk_disable(clk);
802 /* Set new source value (previous dividers if any in effect) */
803 reg_val = __raw_readl(src_addr) & ~field_mask;
804 reg_val |= (field_val << __ffs(field_mask));
805 __raw_writel(reg_val, src_addr);
808 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
809 prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
810 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
814 if (clk->usecount > 0)
815 _omap2_clk_enable(clk);
817 clk->parent = new_parent;
819 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
820 clk->rate = new_parent->rate;
823 clk->rate /= parent_div;
825 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
826 clk->name, clk->parent->name, clk->rate);
828 if (clk->flags & RATE_PROPAGATES)
834 /* DPLL rate rounding code */
837 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
838 * @clk: struct clk * of the DPLL
839 * @tolerance: maximum rate error tolerance
841 * Set the maximum DPLL rate error tolerance for the rate rounding
842 * algorithm. The rate tolerance is an attempt to balance DPLL power
843 * saving (the least divider value "n") vs. rate fidelity (the least
844 * difference between the desired DPLL target rate and the rounded
845 * rate out of the algorithm). So, increasing the tolerance is likely
846 * to decrease DPLL power consumption and increase DPLL rate error.
847 * Returns -EINVAL if provided a null clock ptr or a clk that is not a
848 * DPLL; or 0 upon success.
850 int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
852 if (!clk || !clk->dpll_data)
855 clk->dpll_data->rate_tolerance = tolerance;
860 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
861 unsigned int m, unsigned int n)
863 unsigned long long num;
865 num = (unsigned long long)parent_rate * m;
871 * _dpll_test_mult - test a DPLL multiplier value
872 * @m: pointer to the DPLL m (multiplier) value under test
873 * @n: current DPLL n (divider) value under test
874 * @new_rate: pointer to storage for the resulting rounded rate
875 * @target_rate: the desired DPLL rate
876 * @parent_rate: the DPLL's parent clock rate
878 * This code tests a DPLL multiplier value, ensuring that the
879 * resulting rate will not be higher than the target_rate, and that
880 * the multiplier value itself is valid for the DPLL. Initially, the
881 * integer pointed to by the m argument should be prescaled by
882 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
883 * a non-scaled m upon return. This non-scaled m will result in a
884 * new_rate as close as possible to target_rate (but not greater than
885 * target_rate) given the current (parent_rate, n, prescaled m)
886 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
887 * non-scaled m attempted to underflow, which can allow the calling
888 * function to bail out early; or 0 upon success.
890 static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
891 unsigned long target_rate,
892 unsigned long parent_rate)
894 int flags = 0, carry = 0;
896 /* Unscale m and round if necessary */
897 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
899 *m = (*m / DPLL_SCALE_FACTOR) + carry;
902 * The new rate must be <= the target rate to avoid programming
903 * a rate that is impossible for the hardware to handle
905 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
906 if (*new_rate > target_rate) {
911 /* Guard against m underflow */
912 if (*m < DPLL_MIN_MULTIPLIER) {
913 *m = DPLL_MIN_MULTIPLIER;
915 flags = DPLL_MULT_UNDERFLOW;
919 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
925 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
926 * @clk: struct clk * for a DPLL
927 * @target_rate: desired DPLL clock rate
929 * Given a DPLL, a desired target rate, and a rate tolerance, round
930 * the target rate to a possible, programmable rate for this DPLL.
931 * Rate tolerance is assumed to be set by the caller before this
932 * function is called. Attempts to select the minimum possible n
933 * within the tolerance to reduce power consumption. Stores the
934 * computed (m, n) in the DPLL's dpll_data structure so set_rate()
935 * will not need to call this (expensive) function again. Returns ~0
936 * if the target rate cannot be rounded, either because the rate is
937 * too low or because the rate tolerance is set too tightly; or the
938 * rounded rate upon success.
940 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
942 int m, n, r, e, scaled_max_m;
943 unsigned long scaled_rt_rp, new_rate;
944 int min_e = -1, min_e_m = -1, min_e_n = -1;
946 if (!clk || !clk->dpll_data)
949 pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
950 "%ld\n", clk->name, target_rate);
952 scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR);
953 scaled_max_m = clk->dpll_data->max_multiplier * DPLL_SCALE_FACTOR;
955 clk->dpll_data->last_rounded_rate = 0;
957 for (n = clk->dpll_data->max_divider; n >= DPLL_MIN_DIVIDER; n--) {
959 /* Compute the scaled DPLL multiplier, based on the divider */
960 m = scaled_rt_rp * n;
963 * Since we're counting n down, a m overflow means we can
964 * can immediately skip to the next n
966 if (m > scaled_max_m)
969 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
972 e = target_rate - new_rate;
973 pr_debug("clock: n = %d: m = %d: rate error is %d "
974 "(new_rate = %ld)\n", n, m, e, new_rate);
977 min_e >= (int)(abs(e) - clk->dpll_data->rate_tolerance)) {
982 pr_debug("clock: found new least error %d\n", min_e);
986 * Since we're counting n down, a m underflow means we
987 * can bail out completely (since as n decreases in
988 * the next iteration, there's no way that m can
989 * increase beyond the current m)
991 if (r & DPLL_MULT_UNDERFLOW)
996 pr_debug("clock: error: target rate or tolerance too low\n");
1000 clk->dpll_data->last_rounded_m = min_e_m;
1001 clk->dpll_data->last_rounded_n = min_e_n;
1002 clk->dpll_data->last_rounded_rate =
1003 _dpll_compute_new_rate(clk->parent->rate, min_e_m, min_e_n);
1005 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
1006 min_e, min_e_m, min_e_n);
1007 pr_debug("clock: final rate: %ld (target rate: %ld)\n",
1008 clk->dpll_data->last_rounded_rate, target_rate);
1010 return clk->dpll_data->last_rounded_rate;
1013 /*-------------------------------------------------------------------------
1014 * Omap2 clock reset and init functions
1015 *-------------------------------------------------------------------------*/
1017 #ifdef CONFIG_OMAP_RESET_CLOCKS
1018 void omap2_clk_disable_unused(struct clk *clk)
1022 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
1024 regval32 = __raw_readl(clk->enable_reg);
1025 if ((regval32 & (1 << clk->enable_bit)) == v)
1028 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
1029 _omap2_clk_disable(clk);