2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/list.h>
21 #include <linux/errno.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
24 #include <linux/bitops.h>
27 #include <asm/arch/clock.h>
28 #include <asm/arch/clockdomain.h>
29 #include <asm/arch/sram.h>
30 #include <asm/arch/cpu.h>
31 #include <asm/arch/prcm.h>
32 #include <asm/div64.h>
38 #include "prm-regbits-24xx.h"
40 #include "cm-regbits-24xx.h"
41 #include "cm-regbits-34xx.h"
43 #define MAX_CLOCK_ENABLE_WAIT 100000
45 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
46 #define DPLL_MIN_MULTIPLIER 1
47 #define DPLL_MIN_DIVIDER 1
49 /* Possible error results from _dpll_test_mult */
50 #define DPLL_MULT_UNDERFLOW (1 << 0)
53 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
54 * The higher the scale factor, the greater the risk of arithmetic overflow,
55 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
56 * must be a power of DPLL_SCALE_BASE.
58 #define DPLL_SCALE_FACTOR 64
59 #define DPLL_SCALE_BASE 2
60 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
61 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
65 /*-------------------------------------------------------------------------
66 * OMAP2/3 specific clock functions
67 *-------------------------------------------------------------------------*/
70 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
71 * @clk: OMAP clock struct ptr to use
73 * Convert a clockdomain name stored in a struct clk 'clk' into a
74 * clockdomain pointer, and save it into the struct clk. Intended to be
75 * called during clk_register(). No return value.
77 void omap2_init_clk_clkdm(struct clk *clk)
79 struct clockdomain *clkdm;
84 clkdm = clkdm_lookup(clk->clkdm_name);
86 pr_debug("clock: associated clk %s to clkdm %s\n",
87 clk->name, clk->clkdm_name);
90 pr_debug("clock: could not associate clk %s to "
91 "clkdm %s\n", clk->name, clk->clkdm_name);
96 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
97 * @clk: OMAP clock struct ptr to use
99 * Given a pointer to a source-selectable struct clk, read the hardware
100 * register and determine what its parent is currently set to. Update the
101 * clk->parent field with the appropriate clk ptr.
103 void omap2_init_clksel_parent(struct clk *clk)
105 const struct clksel *clks;
106 const struct clksel_rate *clkr;
112 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
113 r >>= __ffs(clk->clksel_mask);
115 for (clks = clk->clksel; clks->parent && !found; clks++) {
116 for (clkr = clks->rates; clkr->div && !found; clkr++) {
117 if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
118 if (clk->parent != clks->parent) {
119 pr_debug("clock: inited %s parent "
121 clk->name, clks->parent->name,
123 clk->parent->name : "NULL"));
124 clk->parent = clks->parent;
132 printk(KERN_ERR "clock: init parent: could not find "
133 "regval %0x for clock %s\n", r, clk->name);
138 /* Returns the DPLL rate */
139 u32 omap2_get_dpll_rate(struct clk *clk)
142 u32 dpll_mult, dpll_div, dpll;
143 struct dpll_data *dd;
146 /* REVISIT: What do we return on error? */
150 dpll = __raw_readl(dd->mult_div1_reg);
151 dpll_mult = dpll & dd->mult_mask;
152 dpll_mult >>= __ffs(dd->mult_mask);
153 dpll_div = dpll & dd->div1_mask;
154 dpll_div >>= __ffs(dd->div1_mask);
156 dpll_clk = (long long)clk->parent->rate * dpll_mult;
157 do_div(dpll_clk, dpll_div + 1);
163 * Used for clocks that have the same value as the parent clock,
164 * divided by some factor
166 void omap2_fixed_divisor_recalc(struct clk *clk)
168 WARN_ON(!clk->fixed_div);
170 clk->rate = clk->parent->rate / clk->fixed_div;
172 if (clk->flags & RATE_PROPAGATES)
177 * omap2_wait_clock_ready - wait for clock to enable
178 * @reg: physical address of clock IDLEST register
179 * @mask: value to mask against to determine if the clock is active
180 * @name: name of the clock (for printk)
182 * Returns 1 if the clock enabled in time, or 0 if it failed to enable
183 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
185 int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
191 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
192 * 34xx reverses this, just to keep us on our toes
194 if (cpu_mask & (RATE_IN_242X | RATE_IN_243X))
196 else if (cpu_mask & RATE_IN_343X)
200 while (((__raw_readl(reg) & mask) != ena) &&
201 (i++ < MAX_CLOCK_ENABLE_WAIT)) {
205 if (i < MAX_CLOCK_ENABLE_WAIT)
206 pr_debug("Clock %s stable after %d loops\n", name, i);
208 printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
209 name, MAX_CLOCK_ENABLE_WAIT);
212 return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
217 * Note: We don't need special code here for INVERT_ENABLE
218 * for the time being since INVERT_ENABLE only applies to clocks enabled by
221 * REVISIT: This code is ugly and does not belong here.
223 static void omap2_clk_wait_ready(struct clk *clk)
226 unsigned long reg, other_reg, st_reg, prcm_mod, prcm_regid;
228 reg = (unsigned long)clk->enable_reg;
229 prcm_mod = reg & ~0xff;
230 prcm_regid = reg & 0xff;
232 if (prcm_regid >= CM_FCLKEN1 && prcm_regid <= OMAP24XX_CM_FCLKEN2)
233 other_reg = ((reg & ~0xf0) | 0x10); /* CM_ICLKEN* */
234 else if (prcm_regid >= CM_ICLKEN1 && prcm_regid <= OMAP24XX_CM_ICLKEN4)
235 other_reg = ((reg & ~0xf0) | 0x00); /* CM_FCLKEN* */
239 /* 24xx: DSS and CAM have no idlest bits for their target agents */
240 if (cpu_is_omap24xx() &&
241 (prcm_mod == OMAP2420_CM_REGADDR(CORE_MOD, 0) ||
242 prcm_mod == OMAP2430_CM_REGADDR(CORE_MOD, 0)) &&
243 (reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
245 if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
246 clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
247 clk->enable_bit == OMAP24XX_EN_CAM_SHIFT)
252 /* REVISIT: What are the appropriate exclusions for 34XX? */
253 if (cpu_is_omap34xx()) {
256 if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0) &&
257 prcm_mod == OMAP34XX_CM_REGADDR(CORE_MOD, 0) &&
259 clk->enable_bit == OMAP3430_EN_SSI_SHIFT)
263 if (prcm_mod == OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0)) {
265 /* 3430ES1 DSS has no target idlest bits */
266 if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0))
270 * For 3430ES2+ DSS, only wait once (dss1_alwon_fclk,
271 * dss_l3_iclk, dss_l4_iclk) are enabled
273 if (clk->enable_bit != OMAP3430_EN_DSS1_SHIFT)
279 /* Check if both functional and interface clocks
281 bit = 1 << clk->enable_bit;
282 if (!(__raw_readl((void __iomem *)other_reg) & bit))
286 * OMAP3430ES2+ has target idlest bits at unusual offsets for
287 * modules with both initiator and target agents
289 if (cpu_is_omap34xx()) {
292 if (prcm_mod == OMAP34XX_CM_REGADDR(CORE_MOD, 0) &&
294 clk->enable_bit == OMAP3430_EN_SSI_SHIFT)
295 bit = OMAP3430ES2_ST_SSI_IDLE;
298 if (prcm_mod == OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) &&
299 clk->enable_bit == OMAP3430_EN_DSS1_SHIFT)
300 bit = OMAP3430ES2_ST_DSS_IDLE;
304 st_reg = ((other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
306 omap2_wait_clock_ready((void __iomem *)st_reg, bit, clk->name);
309 /* Enables clock without considering parent dependencies or use count
310 * REVISIT: Maybe change this to use clk->enable like on omap1?
312 static int _omap2_clk_enable(struct clk *clk)
316 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
320 return clk->enable(clk);
322 if (!clk->enable_reg) {
323 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
325 return 0; /* REVISIT: -EINVAL */
328 regval32 = __raw_readl(clk->enable_reg);
329 if (clk->flags & INVERT_ENABLE)
330 regval32 &= ~(1 << clk->enable_bit);
332 regval32 |= (1 << clk->enable_bit);
333 __raw_writel(regval32, clk->enable_reg);
336 omap2_clk_wait_ready(clk);
341 /* Disables clock without considering parent dependencies or use count */
342 static void _omap2_clk_disable(struct clk *clk)
346 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
354 if (!clk->enable_reg) {
356 * 'Independent' here refers to a clock which is not
357 * controlled by its parent.
359 printk(KERN_ERR "clock: clk_disable called on independent "
360 "clock %s which has no enable_reg\n", clk->name);
364 regval32 = __raw_readl(clk->enable_reg);
365 if (clk->flags & INVERT_ENABLE)
366 regval32 |= (1 << clk->enable_bit);
368 regval32 &= ~(1 << clk->enable_bit);
369 __raw_writel(regval32, clk->enable_reg);
373 void omap2_clk_disable(struct clk *clk)
375 if (clk->usecount > 0 && !(--clk->usecount)) {
376 _omap2_clk_disable(clk);
378 omap2_clk_disable(clk->parent);
380 omap2_clkdm_clk_disable(clk->clkdm, clk);
385 int omap2_clk_enable(struct clk *clk)
389 if (clk->usecount++ == 0) {
391 ret = omap2_clk_enable(clk->parent);
399 omap2_clkdm_clk_enable(clk->clkdm, clk);
401 ret = _omap2_clk_enable(clk);
405 omap2_clkdm_clk_disable(clk->clkdm, clk);
408 omap2_clk_disable(clk->parent);
418 * Used for clocks that are part of CLKSEL_xyz governed clocks.
419 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
421 void omap2_clksel_recalc(struct clk *clk)
425 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
427 div = omap2_clksel_get_divisor(clk);
431 if (clk->rate == (clk->parent->rate / div))
433 clk->rate = clk->parent->rate / div;
435 pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
437 if (clk->flags & RATE_PROPAGATES)
442 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
443 * @clk: OMAP struct clk ptr to inspect
444 * @src_clk: OMAP struct clk ptr of the parent clk to search for
446 * Scan the struct clksel array associated with the clock to find
447 * the element associated with the supplied parent clock address.
448 * Returns a pointer to the struct clksel on success or NULL on error.
450 static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
453 const struct clksel *clks;
458 for (clks = clk->clksel; clks->parent; clks++) {
459 if (clks->parent == src_clk)
460 break; /* Found the requested parent */
464 printk(KERN_ERR "clock: Could not find parent clock %s in "
465 "clksel array of clock %s\n", src_clk->name,
474 * omap2_clksel_round_rate_div - find divisor for the given clock and rate
475 * @clk: OMAP struct clk to use
476 * @target_rate: desired clock rate
477 * @new_div: ptr to where we should store the divisor
479 * Finds 'best' divider value in an array based on the source and target
480 * rates. The divider array must be sorted with smallest divider first.
481 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
482 * they are only settable as part of virtual_prcm set.
484 * Returns the rounded clock rate or returns 0xffffffff on error.
486 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
489 unsigned long test_rate;
490 const struct clksel *clks;
491 const struct clksel_rate *clkr;
494 printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
495 clk->name, target_rate);
499 clks = omap2_get_clksel_by_parent(clk, clk->parent);
503 for (clkr = clks->rates; clkr->div; clkr++) {
504 if (!(clkr->flags & cpu_mask))
508 if (clkr->div <= last_div)
509 printk(KERN_ERR "clock: clksel_rate table not sorted "
510 "for clock %s", clk->name);
512 last_div = clkr->div;
514 test_rate = clk->parent->rate / clkr->div;
516 if (test_rate <= target_rate)
517 break; /* found it */
521 printk(KERN_ERR "clock: Could not find divisor for target "
522 "rate %ld for clock %s parent %s\n", target_rate,
523 clk->name, clk->parent->name);
527 *new_div = clkr->div;
529 printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
530 (clk->parent->rate / clkr->div));
532 return (clk->parent->rate / clkr->div);
536 * omap2_clksel_round_rate - find rounded rate for the given clock and rate
537 * @clk: OMAP struct clk to use
538 * @target_rate: desired clock rate
540 * Compatibility wrapper for OMAP clock framework
541 * Finds best target rate based on the source clock and possible dividers.
542 * rates. The divider array must be sorted with smallest divider first.
543 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
544 * they are only settable as part of virtual_prcm set.
546 * Returns the rounded clock rate or returns 0xffffffff on error.
548 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
552 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
556 /* Given a clock and a rate apply a clock specific rounding function */
557 long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
560 return clk->round_rate(clk, rate);
562 if (clk->flags & RATE_FIXED)
563 printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
564 "on fixed-rate clock %s\n", clk->name);
570 * omap2_clksel_to_divisor() - turn clksel field value into integer divider
571 * @clk: OMAP struct clk to use
572 * @field_val: register field value to find
574 * Given a struct clk of a rate-selectable clksel clock, and a register field
575 * value to search for, find the corresponding clock divisor. The register
576 * field value should be pre-masked and shifted down so the LSB is at bit 0
577 * before calling. Returns 0 on error
579 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
581 const struct clksel *clks;
582 const struct clksel_rate *clkr;
584 clks = omap2_get_clksel_by_parent(clk, clk->parent);
588 for (clkr = clks->rates; clkr->div; clkr++) {
589 if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
594 printk(KERN_ERR "clock: Could not find fieldval %d for "
595 "clock %s parent %s\n", field_val, clk->name,
604 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
605 * @clk: OMAP struct clk to use
606 * @div: integer divisor to search for
608 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
609 * find the corresponding register field value. The return register value is
610 * the value before left-shifting. Returns 0xffffffff on error
612 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
614 const struct clksel *clks;
615 const struct clksel_rate *clkr;
617 /* should never happen */
620 clks = omap2_get_clksel_by_parent(clk, clk->parent);
624 for (clkr = clks->rates; clkr->div; clkr++) {
625 if ((clkr->flags & cpu_mask) && (clkr->div == div))
630 printk(KERN_ERR "clock: Could not find divisor %d for "
631 "clock %s parent %s\n", div, clk->name,
640 * omap2_get_clksel - find clksel register addr & field mask for a clk
641 * @clk: struct clk to use
642 * @field_mask: ptr to u32 to store the register field mask
644 * Returns the address of the clksel register upon success or NULL on error.
646 static void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
648 if (!clk->clksel_reg || (clk->clksel_mask == 0))
651 *field_mask = clk->clksel_mask;
653 return clk->clksel_reg;
657 * omap2_clksel_get_divisor - get current divider applied to parent clock.
658 * @clk: OMAP struct clk to use.
660 * Returns the integer divisor upon success or 0 on error.
662 u32 omap2_clksel_get_divisor(struct clk *clk)
664 u32 field_mask, field_val;
665 void __iomem *div_addr;
667 div_addr = omap2_get_clksel(clk, &field_mask);
671 field_val = __raw_readl(div_addr) & field_mask;
672 field_val >>= __ffs(field_mask);
674 return omap2_clksel_to_divisor(clk, field_val);
677 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
679 u32 field_mask, field_val, validrate, new_div = 0;
680 void __iomem *div_addr;
683 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
684 if (validrate != rate)
687 div_addr = omap2_get_clksel(clk, &field_mask);
691 field_val = omap2_divisor_to_clksel(clk, new_div);
695 v = __raw_readl(div_addr);
697 v |= field_val << __ffs(field_mask);
698 __raw_writel(v, div_addr);
702 clk->rate = clk->parent->rate / new_div;
704 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
705 prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
706 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
714 /* Set the clock rate for a clock source */
715 int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
719 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
721 /* CONFIG_PARTICIPANT clocks are changed only in sets via the
722 rate table mechanism, driven by mpu_speed */
723 if (clk->flags & CONFIG_PARTICIPANT)
726 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
728 ret = clk->set_rate(clk, rate);
730 if (ret == 0 && (clk->flags & RATE_PROPAGATES))
737 * Converts encoded control register address into a full address
738 * On error, *src_addr will be returned as 0.
740 static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
741 struct clk *src_clk, u32 *field_mask,
742 struct clk *clk, u32 *parent_div)
744 const struct clksel *clks;
745 const struct clksel_rate *clkr;
750 clks = omap2_get_clksel_by_parent(clk, src_clk);
754 for (clkr = clks->rates; clkr->div; clkr++) {
755 if (clkr->flags & (cpu_mask | DEFAULT_RATE))
756 break; /* Found the default rate for this platform */
760 printk(KERN_ERR "clock: Could not find default rate for "
761 "clock %s parent %s\n", clk->name,
762 src_clk->parent->name);
766 /* Should never happen. Add a clksel mask to the struct clk. */
767 WARN_ON(clk->clksel_mask == 0);
769 *field_mask = clk->clksel_mask;
770 *src_addr = clk->clksel_reg;
771 *parent_div = clkr->div;
776 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
778 void __iomem *src_addr;
779 u32 field_val, field_mask, reg_val, parent_div;
781 if (clk->flags & CONFIG_PARTICIPANT)
787 field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
788 &field_mask, clk, &parent_div);
792 if (clk->usecount > 0)
793 _omap2_clk_disable(clk);
795 /* Set new source value (previous dividers if any in effect) */
796 reg_val = __raw_readl(src_addr) & ~field_mask;
797 reg_val |= (field_val << __ffs(field_mask));
798 __raw_writel(reg_val, src_addr);
801 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
802 prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
803 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
807 if (clk->usecount > 0)
808 _omap2_clk_enable(clk);
810 clk->parent = new_parent;
812 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
813 clk->rate = new_parent->rate;
816 clk->rate /= parent_div;
818 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
819 clk->name, clk->parent->name, clk->rate);
821 if (clk->flags & RATE_PROPAGATES)
827 /* DPLL rate rounding code */
830 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
831 * @clk: struct clk * of the DPLL
832 * @tolerance: maximum rate error tolerance
834 * Set the maximum DPLL rate error tolerance for the rate rounding
835 * algorithm. The rate tolerance is an attempt to balance DPLL power
836 * saving (the least divider value "n") vs. rate fidelity (the least
837 * difference between the desired DPLL target rate and the rounded
838 * rate out of the algorithm). So, increasing the tolerance is likely
839 * to decrease DPLL power consumption and increase DPLL rate error.
840 * Returns -EINVAL if provided a null clock ptr or a clk that is not a
841 * DPLL; or 0 upon success.
843 int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
845 if (!clk || !clk->dpll_data)
848 clk->dpll_data->rate_tolerance = tolerance;
853 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
854 unsigned int m, unsigned int n)
856 unsigned long long num;
858 num = (unsigned long long)parent_rate * m;
864 * _dpll_test_mult - test a DPLL multiplier value
865 * @m: pointer to the DPLL m (multiplier) value under test
866 * @n: current DPLL n (divider) value under test
867 * @new_rate: pointer to storage for the resulting rounded rate
868 * @target_rate: the desired DPLL rate
869 * @parent_rate: the DPLL's parent clock rate
871 * This code tests a DPLL multiplier value, ensuring that the
872 * resulting rate will not be higher than the target_rate, and that
873 * the multiplier value itself is valid for the DPLL. Initially, the
874 * integer pointed to by the m argument should be prescaled by
875 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
876 * a non-scaled m upon return. This non-scaled m will result in a
877 * new_rate as close as possible to target_rate (but not greater than
878 * target_rate) given the current (parent_rate, n, prescaled m)
879 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
880 * non-scaled m attempted to underflow, which can allow the calling
881 * function to bail out early; or 0 upon success.
883 static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
884 unsigned long target_rate,
885 unsigned long parent_rate)
887 int flags = 0, carry = 0;
889 /* Unscale m and round if necessary */
890 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
892 *m = (*m / DPLL_SCALE_FACTOR) + carry;
895 * The new rate must be <= the target rate to avoid programming
896 * a rate that is impossible for the hardware to handle
898 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
899 if (*new_rate > target_rate) {
904 /* Guard against m underflow */
905 if (*m < DPLL_MIN_MULTIPLIER) {
906 *m = DPLL_MIN_MULTIPLIER;
908 flags = DPLL_MULT_UNDERFLOW;
912 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
918 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
919 * @clk: struct clk * for a DPLL
920 * @target_rate: desired DPLL clock rate
922 * Given a DPLL, a desired target rate, and a rate tolerance, round
923 * the target rate to a possible, programmable rate for this DPLL.
924 * Rate tolerance is assumed to be set by the caller before this
925 * function is called. Attempts to select the minimum possible n
926 * within the tolerance to reduce power consumption. Stores the
927 * computed (m, n) in the DPLL's dpll_data structure so set_rate()
928 * will not need to call this (expensive) function again. Returns ~0
929 * if the target rate cannot be rounded, either because the rate is
930 * too low or because the rate tolerance is set too tightly; or the
931 * rounded rate upon success.
933 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
935 int m, n, r, e, scaled_max_m;
936 unsigned long scaled_rt_rp, new_rate;
937 int min_e = -1, min_e_m = -1, min_e_n = -1;
939 if (!clk || !clk->dpll_data)
942 pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
943 "%ld\n", clk->name, target_rate);
945 scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR);
946 scaled_max_m = clk->dpll_data->max_multiplier * DPLL_SCALE_FACTOR;
948 clk->dpll_data->last_rounded_rate = 0;
950 for (n = clk->dpll_data->max_divider; n >= DPLL_MIN_DIVIDER; n--) {
952 /* Compute the scaled DPLL multiplier, based on the divider */
953 m = scaled_rt_rp * n;
956 * Since we're counting n down, a m overflow means we can
957 * can immediately skip to the next n
959 if (m > scaled_max_m)
962 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
965 e = target_rate - new_rate;
966 pr_debug("clock: n = %d: m = %d: rate error is %d "
967 "(new_rate = %ld)\n", n, m, e, new_rate);
970 min_e >= (int)(abs(e) - clk->dpll_data->rate_tolerance)) {
975 pr_debug("clock: found new least error %d\n", min_e);
979 * Since we're counting n down, a m underflow means we
980 * can bail out completely (since as n decreases in
981 * the next iteration, there's no way that m can
982 * increase beyond the current m)
984 if (r & DPLL_MULT_UNDERFLOW)
989 pr_debug("clock: error: target rate or tolerance too low\n");
993 clk->dpll_data->last_rounded_m = min_e_m;
994 clk->dpll_data->last_rounded_n = min_e_n;
995 clk->dpll_data->last_rounded_rate =
996 _dpll_compute_new_rate(clk->parent->rate, min_e_m, min_e_n);
998 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
999 min_e, min_e_m, min_e_n);
1000 pr_debug("clock: final rate: %ld (target rate: %ld)\n",
1001 clk->dpll_data->last_rounded_rate, target_rate);
1003 return clk->dpll_data->last_rounded_rate;
1006 /*-------------------------------------------------------------------------
1007 * Omap2 clock reset and init functions
1008 *-------------------------------------------------------------------------*/
1010 #ifdef CONFIG_OMAP_RESET_CLOCKS
1011 void omap2_clk_disable_unused(struct clk *clk)
1015 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
1017 regval32 = __raw_readl(clk->enable_reg);
1018 if ((regval32 & (1 << clk->enable_bit)) == v)
1021 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
1022 _omap2_clk_disable(clk);