arch/arm/mach-omap2/board-n800-flash.c

   1 /*
   2  * linux/arch/arm/mach-omap2/board-n800-flash.c
   3  *
   4  * Copyright (C) 2006 Nokia Corporation
   5  * Author: Juha Yrjola
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/platform_device.h>
  14 #include <asm/mach/flash.h>
  15 #include <linux/mtd/onenand_regs.h>
  16
  17 #include <asm/io.h>
  18 #include <asm/arch/onenand.h>
  19 #include <asm/arch/board.h>
  20 #include <asm/arch/gpmc.h>
  21
  22 static struct mtd_partition n800_partitions[8];
  23
  24 static int n800_onenand_setup(void __iomem *, int freq);
  25
  26 static struct omap_onenand_platform_data n800_onenand_data = {
  27         .cs = 0,
  28         .gpio_irq = 26,
  29         .parts = n800_partitions,
  30         .nr_parts = 0, /* filled later */
  31         .onenand_setup = n800_onenand_setup,
  32 };
  33
  34 static struct platform_device n800_onenand_device = {
  35         .name           = "omap2-onenand",
  36         .id             = -1,
  37         .dev = {
  38                 .platform_data = &n800_onenand_data,
  39         },
  40 };
  41
  42 static unsigned short omap2_onenand_readw(void __iomem *addr)
  43 {
  44         return readw(addr);
  45 }
  46
  47 static void omap2_onenand_writew(unsigned short value, void __iomem *addr)
  48 {
  49         writew(value, addr);
  50 }
  51
  52 static int omap2_onenand_set_sync_mode(int cs, void __iomem *onenand_base,
  53                                        int freq)
  54 {
  55         struct gpmc_timings t;
  56         int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_avdp, t_wpl, t_wea;
  57         int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
  58         int err;
  59         u32 reg;
  60
  61 again:
  62         switch (freq) {
  63         case 83:
  64                 min_gpmc_clk_period = 12; /* 83 MHz */
  65                 t_ces  = 5;
  66                 t_avds = 5;
  67                 t_avdh = 6;
  68                 t_avdp = 12;
  69                 t_wpl  = 40;
  70                 t_wea  = 15;
  71                 break;
  72         case 66:
  73                 min_gpmc_clk_period = 15; /* 66 MHz */
  74                 t_ces  = 6;
  75                 t_avds = 5;
  76                 t_avdh = 6;
  77                 t_avdp = 12;
  78                 t_wpl  = 40;
  79                 t_wea  = 15;
  80                 break;
  81         default:
  82                 min_gpmc_clk_period = 18; /* 54 MHz */
  83                 t_ces  = 7;
  84                 t_avds = 7;
  85                 t_avdh = 7;
  86                 t_avdp = 12;
  87                 t_wpl  = 40;
  88                 t_wea  = 15;
  89                 break;
  90         }
  91
  92         tick_ns = gpmc_ticks_to_ns(1);
  93         div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period);
  94         gpmc_clk_ns = gpmc_ticks_to_ns(div);
  95         if (gpmc_clk_ns >= 25) /* 40 MHz*/
  96                 latency = 3;
  97         else
  98                 latency = 4;
  99
 100         if (div == 1) {
 101                 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
 102                 reg |= (1 << 7);
 103                 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG2, reg);
 104                 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG3);
 105                 reg |= (1 << 7);
 106                 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG3, reg);
 107                 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG4);
 108                 reg |= (1 << 7);
 109                 reg |= (1 << 23);
 110                 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg);
 111         } else {
 112                 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
 113                 reg &= ~(1 << 7);
 114                 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG2, reg);
 115                 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG3);
 116                 reg &= ~(1 << 7);
 117                 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG3, reg);
 118                 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG4);
 119                 reg &= ~(1 << 7);
 120                 reg &= ~(1 << 23);
 121                 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg);
 122         }
 123
 124         /* Set syncronous read timings */
 125         memset(&t, 0, sizeof(t));
 126         t.sync_clk = min_gpmc_clk_period;
 127         t.cs_on = 0;
 128         t.adv_on = 0;
 129         fclk_offset_ns = gpmc_round_ns_to_ticks(max_t(int, t_ces, t_avds));
 130         fclk_offset = gpmc_ns_to_ticks(fclk_offset_ns);
 131         t.page_burst_access = gpmc_clk_ns;
 132
 133         /* Read */
 134         t.adv_rd_off = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_avdh));
 135         t.oe_on = t.adv_rd_off;
 136         t.access = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div);
 137         t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
 138         t.cs_rd_off = t.oe_off;
 139         t.rd_cycle = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div + div);
 140
 141         /* Write */
 142         t.adv_wr_off = t.adv_on + gpmc_round_ns_to_ticks(t_avdp);
 143         t.we_on = t.adv_wr_off + gpmc_round_ns_to_ticks(t_avdh);
 144         t.we_off = t.we_on + gpmc_round_ns_to_ticks(t_wpl);
 145         t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(1);
 146         t.wr_cycle = t.we_off + gpmc_round_ns_to_ticks(t_wea);
 147
 148         /* Configure GPMC for synchronous read */
 149         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
 150                           GPMC_CONFIG1_WRAPBURST_SUPP |
 151                           GPMC_CONFIG1_READMULTIPLE_SUPP |
 152                           GPMC_CONFIG1_READTYPE_SYNC |
 153                           GPMC_CONFIG1_CLKACTIVATIONTIME(fclk_offset) |
 154                           GPMC_CONFIG1_PAGE_LEN(2) |
 155                           GPMC_CONFIG1_WAIT_READ_MON |
 156                           GPMC_CONFIG1_WAIT_PIN_SEL(0) |
 157                           GPMC_CONFIG1_DEVICESIZE_16 |
 158                           GPMC_CONFIG1_DEVICETYPE_NOR |
 159                           GPMC_CONFIG1_MUXADDDATA);
 160
 161         err = gpmc_cs_set_timings(cs, &t);
 162         if (err)
 163                 return err;
 164
 165         if (!freq) {
 166                 /* Very first call freq is not known */
 167                 reg = omap2_onenand_readw(onenand_base + ONENAND_REG_VERSION_ID);
 168                 switch ((reg >> 4) & 0xf) {
 169                 case 0:
 170                         freq = 40;
 171                         break;
 172                 case 1:
 173                         freq = 54;
 174                         break;
 175                 case 2:
 176                         freq = 66;
 177                         break;
 178                 case 3:
 179                         freq = 83;
 180                         break;
 181                 }
 182                 if (freq && freq != 54)
 183                         goto again;
 184         }
 185
 186         /* Configure OneNAND for sync read */
 187         reg = omap2_onenand_readw(onenand_base + ONENAND_REG_SYS_CFG1);
 188         reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) | (0x7 << 9));
 189         reg |=  (latency << ONENAND_SYS_CFG1_BRL_SHIFT) |
 190                 ONENAND_SYS_CFG1_SYNC_READ |
 191                 ONENAND_SYS_CFG1_BL_16;
 192         omap2_onenand_writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
 193
 194         return 0;
 195 }
 196
 197 static int n800_onenand_setup(void __iomem *onenand_base, int freq)
 198 {
 199         struct omap_onenand_platform_data *datap = &n800_onenand_data;
 200         struct device *dev = &n800_onenand_device.dev;
 201
 202         /* Set sync timings in GPMC */
 203         if (omap2_onenand_set_sync_mode(datap->cs, onenand_base, freq) < 0) {
 204                 dev_err(dev, "Unable to set synchronous mode\n");
 205                 return -EINVAL;
 206         }
 207
 208         return 0;
 209 }
 210
 211 void __init n800_flash_init(void)
 212 {
 213         const struct omap_partition_config *part;
 214         int i = 0;
 215
 216         while ((part = omap_get_nr_config(OMAP_TAG_PARTITION,
 217                                 struct omap_partition_config, i)) != NULL) {
 218                 struct mtd_partition *mpart;
 219
 220                 mpart = n800_partitions + i;
 221                 mpart->name = (char *) part->name;
 222                 mpart->size = part->size;
 223                 mpart->offset = part->offset;
 224                 mpart->mask_flags = part->mask_flags;
 225                 i++;
 226                 if (i == ARRAY_SIZE(n800_partitions)) {
 227                         printk(KERN_ERR "Too many partitions supplied\n");
 228                         return;
 229                 }
 230         }
 231         n800_onenand_data.nr_parts = i;
 232         if (platform_device_register(&n800_onenand_device) < 0) {
 233                 printk(KERN_ERR "Unable to register OneNAND device\n");
 234                 return;
 235         }
 236 }