arch/arm/mach-omap2/board-n800-flash.c

   1 /*
   2  * linux/arch/arm/mach-omap2/board-n800-flash.c
   3  *
   4  * Copyright (C) 2006 Nokia Corporation
   5  * Author: Juha Yrjola
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/platform_device.h>
  14 #include <asm/mach/flash.h>
  15 #include <linux/mtd/onenand_regs.h>
  16
  17 #include <asm/io.h>
  18 #include <asm/arch/onenand.h>
  19 #include <asm/arch/board.h>
  20 #include <asm/arch/gpmc.h>
  21
  22 static struct mtd_partition n800_partitions[8];
  23
  24 static int n800_onenand_setup(void __iomem *);
  25
  26 static struct omap_onenand_platform_data n800_onenand_data = {
  27         .cs = 0,
  28         .gpio_irq = 26,
  29         .parts = n800_partitions,
  30         .nr_parts = 0, /* filled later */
  31         .onenand_setup = n800_onenand_setup,
  32 };
  33
  34 static struct platform_device n800_onenand_device = {
  35         .name           = "omap2-onenand",
  36         .id             = -1,
  37         .dev = {
  38                 .platform_data = &n800_onenand_data,
  39         },
  40 };
  41
  42 static unsigned short omap2_onenand_readw(void __iomem *addr)
  43 {
  44         return readw(addr);
  45 }
  46
  47 static void omap2_onenand_writew(unsigned short value, void __iomem *addr)
  48 {
  49         writew(value, addr);
  50 }
  51
  52 static int omap2_onenand_set_sync_mode(int cs, void __iomem *onenand_base)
  53 {
  54         const int min_gpmc_clk_period = 18;
  55         struct gpmc_timings t;
  56         int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
  57         u32 reg;
  58
  59         tick_ns = gpmc_round_ns_to_ticks(1);
  60         div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period);
  61         gpmc_clk_ns = div * tick_ns;
  62         if (gpmc_clk_ns >= 24)
  63                 latency = 3;
  64         else
  65                 latency = 4;
  66
  67         /* Configure OneNAND for sync read */
  68         reg = omap2_onenand_readw(onenand_base + ONENAND_REG_SYS_CFG1);
  69         reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) | (0x7 << 9));
  70         reg |=  (latency << ONENAND_SYS_CFG1_BRL_SHIFT) |
  71                 ONENAND_SYS_CFG1_SYNC_READ |
  72                 ONENAND_SYS_CFG1_BL_16;
  73         omap2_onenand_writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
  74
  75         /* FIXME: Get timings from platform data */
  76         /* Set syncronous read timings */
  77         memset(&t, 0, sizeof(t));
  78         t.sync_clk = min_gpmc_clk_period;
  79         t.cs_on = 0;
  80         t.adv_on = gpmc_round_ns_to_ticks(7);
  81         fclk_offset_ns = t.adv_on + gpmc_round_ns_to_ticks(7);
  82         fclk_offset = fclk_offset_ns / gpmc_round_ns_to_ticks(1);
  83         t.page_burst_access = gpmc_clk_ns;
  84
  85         /* Read */
  86         t.adv_rd_off = fclk_offset_ns + gpmc_round_ns_to_ticks(7);
  87         t.oe_on = t.adv_rd_off;
  88         t.access = fclk_offset_ns + (latency + 1) * gpmc_clk_ns;
  89         t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
  90         t.cs_rd_off = t.oe_off;
  91         t.rd_cycle = t.cs_rd_off + gpmc_round_ns_to_ticks(17);
  92
  93         /* Write */
  94         t.adv_wr_off = t.adv_on + gpmc_round_ns_to_ticks(12);
  95         t.we_on = t.adv_wr_off + gpmc_round_ns_to_ticks(1);
  96         t.we_off = t.we_on + gpmc_round_ns_to_ticks(40);
  97         t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(1);
  98         t.wr_cycle = t.cs_wr_off + gpmc_round_ns_to_ticks(1);
  99
 100         /* Configure GPMC for synchronous read */
 101         fclk_offset %= div;
 102         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
 103                           GPMC_CONFIG1_WRAPBURST_SUPP |
 104                           GPMC_CONFIG1_READMULTIPLE_SUPP |
 105                           GPMC_CONFIG1_READTYPE_SYNC |
 106                           GPMC_CONFIG1_CLKACTIVATIONTIME(fclk_offset) |
 107                           GPMC_CONFIG1_PAGE_LEN(2) |
 108                           GPMC_CONFIG1_WAIT_READ_MON |
 109                           GPMC_CONFIG1_WAIT_PIN_SEL(0) |
 110                           GPMC_CONFIG1_DEVICESIZE_16 |
 111                           GPMC_CONFIG1_DEVICETYPE_NOR |
 112                           GPMC_CONFIG1_MUXADDDATA);
 113
 114         return gpmc_cs_set_timings(cs, &t);
 115 }
 116
 117 static int n800_onenand_setup(void __iomem *onenand_base)
 118 {
 119         struct omap_onenand_platform_data *datap = &n800_onenand_data;
 120         struct device *dev = &n800_onenand_device.dev;
 121
 122         /* Set sync timings in GPMC */
 123         if (omap2_onenand_set_sync_mode(datap->cs, onenand_base) < 0) {
 124                 dev_err(dev, "Unable to set synchronous mode\n");
 125                 return -EINVAL;
 126         }
 127
 128         return 0;
 129 }
 130
 131 void __init n800_flash_init(void)
 132 {
 133         const struct omap_partition_config *part;
 134         int i = 0;
 135
 136         while ((part = omap_get_nr_config(OMAP_TAG_PARTITION,
 137                                 struct omap_partition_config, i)) != NULL) {
 138                 struct mtd_partition *mpart;
 139
 140                 mpart = n800_partitions + i;
 141                 mpart->name = (char *) part->name;
 142                 mpart->size = part->size;
 143                 mpart->offset = part->offset;
 144                 mpart->mask_flags = part->mask_flags;
 145                 i++;
 146                 if (i == ARRAY_SIZE(n800_partitions)) {
 147                         printk(KERN_ERR "Too many partitions supplied\n");
 148                         return;
 149                 }
 150         }
 151         n800_onenand_data.nr_parts = i;
 152         if (platform_device_register(&n800_onenand_device) < 0) {
 153                 printk(KERN_ERR "Unable to register OneNAND device\n");
 154                 return;
 155         }
 156 }