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1 /*
2  * linux/arch/arm/mach-omap2/board-3430sdp-usb.c
3  *
4  * This file will contain the board specific details for the
5  * MENTOR USB OTG and Synopsys EHCI host controllers on OMAP3430
6  *
7  * Copyright (C) 2007 Texas Instruments
8  * Author: Vikram Pandita
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software Foundation.
13  */
14
15 #include <linux/types.h>
16 #include <linux/errno.h>
17 #include <linux/delay.h>
18 #include <linux/platform_device.h>
19 #include <asm/io.h>
20 #include <asm/arch/mux.h>
21 #include <linux/usb/musb.h>
22
23 #include <asm/arch/hardware.h>
24 #include <asm/arch/usb.h>
25
26 #ifdef CONFIG_USB_MUSB_SOC
27 static struct resource musb_resources[] = {
28         [0] = {
29                 .start  = OMAP34XX_HSUSB_OTG_BASE,
30                 .end    = OMAP34XX_HSUSB_OTG_BASE + SZ_8K,
31                 .flags  = IORESOURCE_MEM,
32         },
33         [1] = { /* general IRQ */
34                 .start  = INT_243X_HS_USB_MC,
35                 .flags  = IORESOURCE_IRQ,
36         },
37         [2] = { /* DMA IRQ */
38                 .start  = INT_243X_HS_USB_DMA,
39                 .flags  = IORESOURCE_IRQ,
40         },
41 };
42
43 static struct musb_hdrc_platform_data musb_plat = {
44 #ifdef CONFIG_USB_MUSB_OTG
45         .mode           = MUSB_OTG,
46 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
47         .mode           = MUSB_HOST,
48 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
49         .mode           = MUSB_PERIPHERAL,
50 #endif
51         .multipoint     = 1,
52         .clock          = NULL,
53         .set_clock      = NULL,
54 };
55
56 static u64 musb_dmamask = ~(u32)0;
57
58 static struct platform_device musb_device = {
59         .name           = "musb_hdrc",
60         .id             = 0,
61         .dev = {
62                 .dma_mask               = &musb_dmamask,
63                 .coherent_dma_mask      = 0xffffffff,
64                 .platform_data          = &musb_plat,
65         },
66         .num_resources  = ARRAY_SIZE(musb_resources),
67         .resource       = musb_resources,
68 };
69 #endif
70
71
72 /* EHCI platform specific data */
73
74 #if     defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
75 static struct resource ehci_resources[] = {
76         [0] = {
77                 .start   = OMAP34XX_HSUSB_HOST_BASE + 0x800,
78                 .end     = OMAP34XX_HSUSB_HOST_BASE + 0x800 + SZ_1K,
79                 .flags   = IORESOURCE_MEM,
80         },
81         [1] = {         /* general IRQ */
82                 .start   = INT_34XX_EHCI_IRQ,
83                 .flags   = IORESOURCE_IRQ,
84         }
85 };
86
87 static u64 ehci_dmamask = ~(u32)0;
88 static struct platform_device ehci_device = {
89         .name           = "ehci-omap",
90         .id             = 0,
91         .dev = {
92                 .dma_mask               = &ehci_dmamask,
93                 .coherent_dma_mask      = 0xffffffff,
94                 .platform_data          = 0x0,
95         },
96         .num_resources  = ARRAY_SIZE(ehci_resources),
97         .resource       = ehci_resources,
98 };
99
100
101 /* MUX settings for EHCI pins */
102 /*
103  * setup_ehci_io_mux - initialize IO pad mux for USBHOST
104  */
105 static void setup_ehci_io_mux(void)
106 {
107 #ifdef CONFIG_OMAP_EHCI_PHY_MODE
108         /* PHY mode of operation for board: 750-2083-001
109          * ISP1504 connected to Port1 and Port2
110          * Do Func Mux setting for 12-pin ULPI PHY mode
111          */
112
113         /* Port1 */
114         omap_cfg_reg(Y9_3430_USB1HS_PHY_STP);
115         omap_cfg_reg(Y8_3430_USB1HS_PHY_CLK);
116         omap_cfg_reg(AA14_3430_USB1HS_PHY_DIR);
117         omap_cfg_reg(AA11_3430_USB1HS_PHY_NXT);
118         omap_cfg_reg(W13_3430_USB1HS_PHY_DATA0);
119         omap_cfg_reg(W12_3430_USB1HS_PHY_DATA1);
120         omap_cfg_reg(W11_3430_USB1HS_PHY_DATA2);
121         omap_cfg_reg(Y11_3430_USB1HS_PHY_DATA3);
122         omap_cfg_reg(W9_3430_USB1HS_PHY_DATA4);
123         omap_cfg_reg(Y12_3430_USB1HS_PHY_DATA5);
124         omap_cfg_reg(W8_3430_USB1HS_PHY_DATA6);
125         omap_cfg_reg(Y13_3430_USB1HS_PHY_DATA7);
126
127         /* Port2 */
128         omap_cfg_reg(AA10_3430_USB2HS_PHY_STP);
129         omap_cfg_reg(AA8_3430_USB2HS_PHY_CLK);
130         omap_cfg_reg(AA9_3430_USB2HS_PHY_DIR);
131         omap_cfg_reg(AB11_3430_USB2HS_PHY_NXT);
132         omap_cfg_reg(AB10_3430_USB2HS_PHY_DATA0);
133         omap_cfg_reg(AB9_3430_USB2HS_PHY_DATA1);
134         omap_cfg_reg(W3_3430_USB2HS_PHY_DATA2);
135         omap_cfg_reg(T4_3430_USB2HS_PHY_DATA3);
136         omap_cfg_reg(T3_3430_USB2HS_PHY_DATA4);
137         omap_cfg_reg(R3_3430_USB2HS_PHY_DATA5);
138         omap_cfg_reg(R4_3430_USB2HS_PHY_DATA6);
139         omap_cfg_reg(T2_3430_USB2HS_PHY_DATA7);
140
141 #else
142         /* Set Func mux for :
143          * TLL mode of operation
144          * 12-pin ULPI SDR TLL mode for Port1/2/3
145          */
146
147         /* Port1 */
148         omap_cfg_reg(Y9_3430_USB1HS_TLL_STP);
149         omap_cfg_reg(Y8_3430_USB1HS_TLL_CLK);
150         omap_cfg_reg(AA14_3430_USB1HS_TLL_DIR);
151         omap_cfg_reg(AA11_3430_USB1HS_TLL_NXT);
152         omap_cfg_reg(W13_3430_USB1HS_TLL_DATA0);
153         omap_cfg_reg(W12_3430_USB1HS_TLL_DATA1);
154         omap_cfg_reg(W11_3430_USB1HS_TLL_DATA2);
155         omap_cfg_reg(Y11_3430_USB1HS_TLL_DATA3);
156         omap_cfg_reg(W9_3430_USB1HS_TLL_DATA4);
157         omap_cfg_reg(Y12_3430_USB1HS_TLL_DATA5);
158         omap_cfg_reg(W8_3430_USB1HS_TLL_DATA6);
159         omap_cfg_reg(Y13_3430_USB1HS_TLL_DATA7);
160
161         /* Port2 */
162         omap_cfg_reg(AA10_3430_USB2HS_TLL_STP);
163         omap_cfg_reg(AA8_3430_USB2HS_TLL_CLK);
164         omap_cfg_reg(AA9_3430_USB2HS_TLL_DIR);
165         omap_cfg_reg(AB11_3430_USB2HS_TLL_NXT);
166         omap_cfg_reg(AB10_3430_USB2HS_TLL_DATA0);
167         omap_cfg_reg(AB9_3430_USB2HS_TLL_DATA1);
168         omap_cfg_reg(W3_3430_USB2HS_TLL_DATA2);
169         omap_cfg_reg(T4_3430_USB2HS_TLL_DATA3);
170         omap_cfg_reg(T3_3430_USB2HS_TLL_DATA4);
171         omap_cfg_reg(R3_3430_USB2HS_TLL_DATA5);
172         omap_cfg_reg(R4_3430_USB2HS_TLL_DATA6);
173         omap_cfg_reg(T2_3430_USB2HS_TLL_DATA7);
174
175         /* Port3 */
176         omap_cfg_reg(AB3_3430_USB3HS_TLL_STP);
177         omap_cfg_reg(AA6_3430_USB3HS_TLL_CLK);
178         omap_cfg_reg(AA3_3430_USB3HS_TLL_DIR);
179         omap_cfg_reg(Y3_3430_USB3HS_TLL_NXT);
180         omap_cfg_reg(AA5_3430_USB3HS_TLL_DATA0);
181         omap_cfg_reg(Y4_3430_USB3HS_TLL_DATA1);
182         omap_cfg_reg(Y5_3430_USB3HS_TLL_DATA2);
183         omap_cfg_reg(W5_3430_USB3HS_TLL_DATA3);
184         omap_cfg_reg(AB12_3430_USB3HS_TLL_DATA4);
185         omap_cfg_reg(AB13_3430_USB3HS_TLL_DATA5);
186         omap_cfg_reg(AA13_3430_USB3HS_TLL_DATA6);
187         omap_cfg_reg(AA12_3430_USB3HS_TLL_DATA7);
188 #endif /* CONFIG_OMAP_EHCI_PHY_MODE */
189
190         return;
191 }
192
193 #endif /* EHCI specific data */
194
195 void __init sdp3430_usb_init(void)
196 {
197 #ifdef CONFIG_USB_MUSB_SOC
198         if (platform_device_register(&musb_device) < 0) {
199                 printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n");
200                 return;
201         }
202 #endif
203
204 #if     defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
205
206         /* Setup Pin IO MUX for EHCI */
207         setup_ehci_io_mux();
208
209         if (platform_device_register(&ehci_device) < 0) {
210                 printk(KERN_ERR "Unable to register HS-USB (EHCI) device\n");
211                 return;
212         }
213 #endif
214
215 }
216