1 //kernel/linux-omap-fsample/arch/arm/mach-omap1/pm.c#3 - integrate change 4545 (text)
3 * linux/arch/arm/mach-omap1/pm.c
5 * OMAP Power Management Routines
7 * Original code for the SA11x0:
8 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
10 * Modified for the PXA250 by Nicolas Pitre:
11 * Copyright (c) 2002 Monta Vista Software, Inc.
13 * Modified for the OMAP1510 by David Singleton:
14 * Copyright (c) 2002 Monta Vista Software, Inc.
16 * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
18 * This program is free software; you can redistribute it and/or modify it
19 * under the terms of the GNU General Public License as published by the
20 * Free Software Foundation; either version 2 of the License, or (at your
21 * option) any later version.
23 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 * You should have received a copy of the GNU General Public License along
35 * with this program; if not, write to the Free Software Foundation, Inc.,
36 * 675 Mass Ave, Cambridge, MA 02139, USA.
40 #include <linux/sched.h>
41 #include <linux/proc_fs.h>
43 #include <linux/interrupt.h>
44 #include <linux/sysfs.h>
45 #include <linux/module.h>
49 #include <asm/atomic.h>
50 #include <asm/mach/time.h>
51 #include <asm/mach/irq.h>
52 #include <asm/mach-types.h>
54 #include <asm/arch/cpu.h>
55 #include <asm/arch/irqs.h>
56 #include <asm/arch/clock.h>
57 #include <asm/arch/sram.h>
58 #include <asm/arch/tc.h>
59 #include <asm/arch/pm.h>
60 #include <asm/arch/mux.h>
61 #include <asm/arch/tps65010.h>
62 #include <asm/arch/dma.h>
63 #include <asm/arch/dsp_common.h>
64 #include <asm/arch/dmtimer.h>
66 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
67 static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
68 static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
69 static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE];
70 static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
71 static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
73 static unsigned short enable_dyn_sleep = 1;
75 static ssize_t omap_pm_sleep_while_idle_show(struct subsystem * subsys, char *buf)
77 return sprintf(buf, "%hu\n", enable_dyn_sleep);
80 static ssize_t omap_pm_sleep_while_idle_store(struct subsystem * subsys,
85 if (sscanf(buf, "%hu", &value) != 1 ||
86 (value != 0 && value != 1)) {
87 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
90 enable_dyn_sleep = value;
94 static struct subsys_attribute sleep_while_idle_attr = {
96 .name = __stringify(sleep_while_idle),
99 .show = omap_pm_sleep_while_idle_show,
100 .store = omap_pm_sleep_while_idle_store,
103 extern struct subsystem power_subsys;
104 static void (*omap_sram_idle)(void) = NULL;
105 static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
108 * Let's power down on idle, but only if we are really
109 * idle, because once we start down the path of
110 * going idle we continue to do idle even if we get
111 * a clock tick interrupt . .
113 void omap_pm_idle(void)
115 extern __u32 arm_idlect1_mask;
116 __u32 use_idlect1 = arm_idlect1_mask;
117 #ifndef CONFIG_OMAP_MPU_TIMER
123 if (need_resched()) {
130 * Since an interrupt may set up a timer, we don't want to
131 * reprogram the hardware timer with interrupts enabled.
132 * Re-enable interrupts only after returning from idle.
134 timer_dyn_reprogram();
136 #ifdef CONFIG_OMAP_MPU_TIMER
137 #warning Enable 32kHz OS timer in order to allow sleep states in idle
138 use_idlect1 = use_idlect1 & ~(1 << 9);
142 while (enable_dyn_sleep) {
144 #ifdef CONFIG_CBUS_TAHVO_USB
145 extern int vbus_active;
146 /* Clock requirements? */
154 #ifdef CONFIG_OMAP_DM_TIMER
155 use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
158 if (omap_dma_running())
159 use_idlect1 &= ~(1 << 6);
161 /* We should be able to remove the do_sleep variable and multiple
162 * tests above as soon as drivers, timer and DMA code have been fixed.
163 * Even the sleep block count should become obsolete. */
164 if ((use_idlect1 != ~0) || !do_sleep) {
166 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
167 if (cpu_is_omap15xx())
168 use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST;
170 use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL;
171 omap_writel(use_idlect1, ARM_IDLECT1);
172 __asm__ volatile ("mcr p15, 0, r0, c7, c0, 4");
173 omap_writel(saved_idlect1, ARM_IDLECT1);
179 omap_sram_suspend(omap_readl(ARM_IDLECT1),
180 omap_readl(ARM_IDLECT2));
188 * Configuration of the wakeup event is board specific. For the
189 * moment we put it into this helper function. Later it may move
190 * to board specific files.
192 static void omap_pm_wakeup_setup(void)
195 u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
198 * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
199 * and the L2 wakeup interrupts: keypad and UART2. Note that the
200 * drivers must still separately call omap_set_gpio_wakeup() to
201 * wake up to a GPIO interrupt.
203 if (cpu_is_omap730())
204 level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) |
205 OMAP_IRQ_BIT(INT_730_IH2_IRQ);
206 else if (cpu_is_omap15xx())
207 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
208 OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
209 else if (cpu_is_omap16xx())
210 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
211 OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
213 omap_writel(~level1_wake, OMAP_IH1_MIR);
215 if (cpu_is_omap730()) {
216 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
217 omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) |
218 OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)),
220 } else if (cpu_is_omap15xx()) {
221 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
222 omap_writel(~level2_wake, OMAP_IH2_MIR);
223 } else if (cpu_is_omap16xx()) {
224 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
225 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
227 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
228 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ),
230 omap_writel(~0x0, OMAP_IH2_2_MIR);
231 omap_writel(~0x0, OMAP_IH2_3_MIR);
234 /* New IRQ agreement, recalculate in cascade order */
235 omap_writel(1, OMAP_IH2_CONTROL);
236 omap_writel(1, OMAP_IH1_CONTROL);
239 #define EN_DSPCK 13 /* ARM_CKCTL */
240 #define EN_APICK 6 /* ARM_IDLECT2 */
241 #define DSP_EN 1 /* ARM_RSTCT1 */
243 void omap_pm_suspend(void)
245 unsigned long arg0 = 0, arg1 = 0;
247 printk("PM: OMAP%x is trying to enter deep sleep...\n", system_rev);
249 omap_serial_wake_trigger(1);
251 if (machine_is_omap_osk()) {
252 /* Stop LED1 (D9) blink */
253 tps65010_set_led(LED1, OFF);
256 if (!cpu_is_omap15xx())
257 omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
260 * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
267 * Step 2: save registers
269 * The omap is a strange/beautiful device. The caches, memory
270 * and register state are preserved across power saves.
271 * We have to save and restore very little register state to
274 * Save interrupt, MPUI, ARM and UPLD control registers.
277 if (cpu_is_omap730()) {
278 MPUI730_SAVE(OMAP_IH1_MIR);
279 MPUI730_SAVE(OMAP_IH2_0_MIR);
280 MPUI730_SAVE(OMAP_IH2_1_MIR);
281 MPUI730_SAVE(MPUI_CTRL);
282 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
283 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
284 MPUI730_SAVE(EMIFS_CONFIG);
285 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
287 } else if (cpu_is_omap15xx()) {
288 MPUI1510_SAVE(OMAP_IH1_MIR);
289 MPUI1510_SAVE(OMAP_IH2_MIR);
290 MPUI1510_SAVE(MPUI_CTRL);
291 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
292 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
293 MPUI1510_SAVE(EMIFS_CONFIG);
294 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
295 } else if (cpu_is_omap16xx()) {
296 MPUI1610_SAVE(OMAP_IH1_MIR);
297 MPUI1610_SAVE(OMAP_IH2_0_MIR);
298 MPUI1610_SAVE(OMAP_IH2_1_MIR);
299 MPUI1610_SAVE(OMAP_IH2_2_MIR);
300 MPUI1610_SAVE(OMAP_IH2_3_MIR);
301 MPUI1610_SAVE(MPUI_CTRL);
302 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
303 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
304 MPUI1610_SAVE(EMIFS_CONFIG);
305 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
309 ARM_SAVE(ARM_IDLECT1);
310 ARM_SAVE(ARM_IDLECT2);
311 if (!(cpu_is_omap15xx()))
312 ARM_SAVE(ARM_IDLECT3);
313 ARM_SAVE(ARM_EWUPCT);
314 ARM_SAVE(ARM_RSTCT1);
315 ARM_SAVE(ARM_RSTCT2);
317 ULPD_SAVE(ULPD_CLOCK_CTRL);
318 ULPD_SAVE(ULPD_STATUS_REQ);
320 /* (Step 3 removed - we now allow deep sleep by default) */
323 * Step 4: OMAP DSP Shutdown
327 omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
329 /* shut down dsp_ck */
330 if (!cpu_is_omap730())
331 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
333 /* temporarily enabling api_ck to access DSP registers */
334 omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
336 /* save DSP registers */
337 DSP_SAVE(DSP_IDLECT2);
339 /* Stop all DSP domain clocks */
340 __raw_writew(0, DSP_IDLECT2);
343 * Step 5: Wakeup Event Setup
346 omap_pm_wakeup_setup();
349 * Step 6: ARM and Traffic controller shutdown
352 /* disable ARM watchdog */
353 omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
354 omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
357 * Step 6b: ARM and Traffic controller shutdown
359 * Step 6 continues here. Prepare jump to power management
360 * assembly code in internal SRAM.
362 * Since the omap_cpu_suspend routine has been copied to
363 * SRAM, we'll do an indirect procedure call to it and pass the
364 * contents of arm_idlect1 and arm_idlect2 so it can restore
365 * them when it wakes up and it will return.
368 arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
369 arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
372 * Step 6c: ARM and Traffic controller shutdown
374 * Jump to assembly code. The processor will stay there
377 omap_sram_suspend(arg0, arg1);
380 * If we are here, processor is woken up!
387 /* again temporarily enabling api_ck to access DSP registers */
388 omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
390 /* Restore DSP domain clocks */
391 DSP_RESTORE(DSP_IDLECT2);
394 * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
397 if (!(cpu_is_omap15xx()))
398 ARM_RESTORE(ARM_IDLECT3);
399 ARM_RESTORE(ARM_CKCTL);
400 ARM_RESTORE(ARM_EWUPCT);
401 ARM_RESTORE(ARM_RSTCT1);
402 ARM_RESTORE(ARM_RSTCT2);
403 ARM_RESTORE(ARM_SYSST);
404 ULPD_RESTORE(ULPD_CLOCK_CTRL);
405 ULPD_RESTORE(ULPD_STATUS_REQ);
407 if (cpu_is_omap730()) {
408 MPUI730_RESTORE(EMIFS_CONFIG);
409 MPUI730_RESTORE(EMIFF_SDRAM_CONFIG);
410 MPUI730_RESTORE(OMAP_IH1_MIR);
411 MPUI730_RESTORE(OMAP_IH2_0_MIR);
412 MPUI730_RESTORE(OMAP_IH2_1_MIR);
413 } else if (cpu_is_omap15xx()) {
414 MPUI1510_RESTORE(MPUI_CTRL);
415 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
416 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
417 MPUI1510_RESTORE(EMIFS_CONFIG);
418 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
419 MPUI1510_RESTORE(OMAP_IH1_MIR);
420 MPUI1510_RESTORE(OMAP_IH2_MIR);
421 } else if (cpu_is_omap16xx()) {
422 MPUI1610_RESTORE(MPUI_CTRL);
423 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
424 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
425 MPUI1610_RESTORE(EMIFS_CONFIG);
426 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
428 MPUI1610_RESTORE(OMAP_IH1_MIR);
429 MPUI1610_RESTORE(OMAP_IH2_0_MIR);
430 MPUI1610_RESTORE(OMAP_IH2_1_MIR);
431 MPUI1610_RESTORE(OMAP_IH2_2_MIR);
432 MPUI1610_RESTORE(OMAP_IH2_3_MIR);
435 if (!cpu_is_omap15xx())
436 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
439 * Reenable interrupts
445 omap_serial_wake_trigger(0);
447 printk("PM: OMAP%x is re-starting from deep sleep...\n", system_rev);
449 if (machine_is_omap_osk()) {
450 /* Let LED1 (D9) blink again */
451 tps65010_set_led(LED1, BLINK);
455 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
456 static int g_read_completed;
459 * Read system PM registers for debugging
461 static int omap_pm_read_proc(
463 char **my_first_byte,
469 int my_buffer_offset = 0;
470 char * const my_base = page_buffer;
473 ARM_SAVE(ARM_IDLECT1);
474 ARM_SAVE(ARM_IDLECT2);
475 if (!(cpu_is_omap15xx()))
476 ARM_SAVE(ARM_IDLECT3);
477 ARM_SAVE(ARM_EWUPCT);
478 ARM_SAVE(ARM_RSTCT1);
479 ARM_SAVE(ARM_RSTCT2);
482 ULPD_SAVE(ULPD_IT_STATUS);
483 ULPD_SAVE(ULPD_CLOCK_CTRL);
484 ULPD_SAVE(ULPD_SOFT_REQ);
485 ULPD_SAVE(ULPD_STATUS_REQ);
486 ULPD_SAVE(ULPD_DPLL_CTRL);
487 ULPD_SAVE(ULPD_POWER_CTRL);
489 if (cpu_is_omap730()) {
490 MPUI730_SAVE(MPUI_CTRL);
491 MPUI730_SAVE(MPUI_DSP_STATUS);
492 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
493 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
494 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
495 MPUI730_SAVE(EMIFS_CONFIG);
496 } else if (cpu_is_omap15xx()) {
497 MPUI1510_SAVE(MPUI_CTRL);
498 MPUI1510_SAVE(MPUI_DSP_STATUS);
499 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
500 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
501 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
502 MPUI1510_SAVE(EMIFS_CONFIG);
503 } else if (cpu_is_omap16xx()) {
504 MPUI1610_SAVE(MPUI_CTRL);
505 MPUI1610_SAVE(MPUI_DSP_STATUS);
506 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
507 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
508 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
509 MPUI1610_SAVE(EMIFS_CONFIG);
512 if (virtual_start == 0) {
513 g_read_completed = 0;
515 my_buffer_offset += sprintf(my_base + my_buffer_offset,
516 "ARM_CKCTL_REG: 0x%-8x \n"
517 "ARM_IDLECT1_REG: 0x%-8x \n"
518 "ARM_IDLECT2_REG: 0x%-8x \n"
519 "ARM_IDLECT3_REG: 0x%-8x \n"
520 "ARM_EWUPCT_REG: 0x%-8x \n"
521 "ARM_RSTCT1_REG: 0x%-8x \n"
522 "ARM_RSTCT2_REG: 0x%-8x \n"
523 "ARM_SYSST_REG: 0x%-8x \n"
524 "ULPD_IT_STATUS_REG: 0x%-4x \n"
525 "ULPD_CLOCK_CTRL_REG: 0x%-4x \n"
526 "ULPD_SOFT_REQ_REG: 0x%-4x \n"
527 "ULPD_DPLL_CTRL_REG: 0x%-4x \n"
528 "ULPD_STATUS_REQ_REG: 0x%-4x \n"
529 "ULPD_POWER_CTRL_REG: 0x%-4x \n",
531 ARM_SHOW(ARM_IDLECT1),
532 ARM_SHOW(ARM_IDLECT2),
533 ARM_SHOW(ARM_IDLECT3),
534 ARM_SHOW(ARM_EWUPCT),
535 ARM_SHOW(ARM_RSTCT1),
536 ARM_SHOW(ARM_RSTCT2),
538 ULPD_SHOW(ULPD_IT_STATUS),
539 ULPD_SHOW(ULPD_CLOCK_CTRL),
540 ULPD_SHOW(ULPD_SOFT_REQ),
541 ULPD_SHOW(ULPD_DPLL_CTRL),
542 ULPD_SHOW(ULPD_STATUS_REQ),
543 ULPD_SHOW(ULPD_POWER_CTRL));
545 if (cpu_is_omap730()) {
546 my_buffer_offset += sprintf(my_base + my_buffer_offset,
547 "MPUI730_CTRL_REG 0x%-8x \n"
548 "MPUI730_DSP_STATUS_REG: 0x%-8x \n"
549 "MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
550 "MPUI730_DSP_API_CONFIG_REG: 0x%-8x \n"
551 "MPUI730_SDRAM_CONFIG_REG: 0x%-8x \n"
552 "MPUI730_EMIFS_CONFIG_REG: 0x%-8x \n",
553 MPUI730_SHOW(MPUI_CTRL),
554 MPUI730_SHOW(MPUI_DSP_STATUS),
555 MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG),
556 MPUI730_SHOW(MPUI_DSP_API_CONFIG),
557 MPUI730_SHOW(EMIFF_SDRAM_CONFIG),
558 MPUI730_SHOW(EMIFS_CONFIG));
559 } else if (cpu_is_omap15xx()) {
560 my_buffer_offset += sprintf(my_base + my_buffer_offset,
561 "MPUI1510_CTRL_REG 0x%-8x \n"
562 "MPUI1510_DSP_STATUS_REG: 0x%-8x \n"
563 "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
564 "MPUI1510_DSP_API_CONFIG_REG: 0x%-8x \n"
565 "MPUI1510_SDRAM_CONFIG_REG: 0x%-8x \n"
566 "MPUI1510_EMIFS_CONFIG_REG: 0x%-8x \n",
567 MPUI1510_SHOW(MPUI_CTRL),
568 MPUI1510_SHOW(MPUI_DSP_STATUS),
569 MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
570 MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
571 MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
572 MPUI1510_SHOW(EMIFS_CONFIG));
573 } else if (cpu_is_omap16xx()) {
574 my_buffer_offset += sprintf(my_base + my_buffer_offset,
575 "MPUI1610_CTRL_REG 0x%-8x \n"
576 "MPUI1610_DSP_STATUS_REG: 0x%-8x \n"
577 "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
578 "MPUI1610_DSP_API_CONFIG_REG: 0x%-8x \n"
579 "MPUI1610_SDRAM_CONFIG_REG: 0x%-8x \n"
580 "MPUI1610_EMIFS_CONFIG_REG: 0x%-8x \n",
581 MPUI1610_SHOW(MPUI_CTRL),
582 MPUI1610_SHOW(MPUI_DSP_STATUS),
583 MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
584 MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
585 MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
586 MPUI1610_SHOW(EMIFS_CONFIG));
590 } else if (g_read_completed >= 1) {
596 *my_first_byte = page_buffer;
597 return my_buffer_offset;
600 static void omap_pm_init_proc(void)
602 struct proc_dir_entry *entry;
604 entry = create_proc_read_entry("driver/omap_pm",
605 S_IWUSR | S_IRUGO, NULL,
606 omap_pm_read_proc, NULL);
609 #endif /* DEBUG && CONFIG_PROC_FS */
611 static void (*saved_idle)(void) = NULL;
614 * omap_pm_prepare - Do preliminary suspend work.
615 * @state: suspend state we're entering.
618 static int omap_pm_prepare(suspend_state_t state)
622 /* We cannot sleep in idle until we have resumed */
623 saved_idle = pm_idle;
628 case PM_SUSPEND_STANDBY:
632 case PM_SUSPEND_DISK:
644 * omap_pm_enter - Actually enter a sleep state.
645 * @state: State we're entering.
649 static int omap_pm_enter(suspend_state_t state)
653 case PM_SUSPEND_STANDBY:
658 case PM_SUSPEND_DISK:
670 * omap_pm_finish - Finish up suspend sequence.
671 * @state: State we're coming out of.
673 * This is called after we wake back up (or if entering the sleep state
677 static int omap_pm_finish(suspend_state_t state)
679 pm_idle = saved_idle;
684 static irqreturn_t omap_wakeup_interrupt(int irq, void *dev)
689 static struct irqaction omap_wakeup_irq = {
690 .name = "peripheral wakeup",
691 .flags = IRQF_DISABLED,
692 .handler = omap_wakeup_interrupt
697 static struct pm_ops omap_pm_ops ={
699 .prepare = omap_pm_prepare,
700 .enter = omap_pm_enter,
701 .finish = omap_pm_finish,
704 static int __init omap_pm_init(void)
708 printk("Power Management for TI OMAP.\n");
711 * We copy the assembler sleep/wakeup routines to SRAM.
712 * These routines need to be in SRAM as that's the only
713 * memory the MPU can see when it wakes up.
715 if (cpu_is_omap730()) {
716 omap_sram_idle = omap_sram_push(omap730_idle_loop_suspend,
717 omap730_idle_loop_suspend_sz);
718 omap_sram_suspend = omap_sram_push(omap730_cpu_suspend,
719 omap730_cpu_suspend_sz);
720 } else if (cpu_is_omap15xx()) {
721 omap_sram_idle = omap_sram_push(omap1510_idle_loop_suspend,
722 omap1510_idle_loop_suspend_sz);
723 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
724 omap1510_cpu_suspend_sz);
725 } else if (cpu_is_omap16xx()) {
726 omap_sram_idle = omap_sram_push(omap1610_idle_loop_suspend,
727 omap1610_idle_loop_suspend_sz);
728 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
729 omap1610_cpu_suspend_sz);
732 if (omap_sram_idle == NULL || omap_sram_suspend == NULL) {
733 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
737 pm_idle = omap_pm_idle;
739 if (cpu_is_omap730())
740 setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq);
741 else if (cpu_is_omap16xx())
742 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
744 /* Program new power ramp-up time
745 * (0 for most boards since we don't lower voltage when in deep sleep)
747 omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
749 /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
750 omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
752 /* Configure IDLECT3 */
753 if (cpu_is_omap730())
754 omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3);
755 else if (cpu_is_omap16xx())
756 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
758 pm_set_ops(&omap_pm_ops);
760 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
764 error = subsys_create_file(&power_subsys, &sleep_while_idle_attr);
766 printk(KERN_ERR "subsys_create_file failed: %d\n", error);
768 if (cpu_is_omap16xx()) {
769 /* configure LOW_PWR pin */
770 omap_cfg_reg(T20_1610_LOW_PWR);
775 __initcall(omap_pm_init);