arch/arm/mach-omap1/pm.c

   1 /*
   2  * linux/arch/arm/plat-omap/pm.c
   3  *
   4  * OMAP Power Management Routines
   5  *
   6  * Original code for the SA11x0:
   7  * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
   8  *
   9  * Modified for the PXA250 by Nicolas Pitre:
  10  * Copyright (c) 2002 Monta Vista Software, Inc.
  11  *
  12  * Modified for the OMAP1510 by David Singleton:
  13  * Copyright (c) 2002 Monta Vista Software, Inc.
  14  *
  15  * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
  16  *
  17  * This program is free software; you can redistribute it and/or modify it
  18  * under the terms of the GNU General Public License as published by the
  19  * Free Software Foundation; either version 2 of the License, or (at your
  20  * option) any later version.
  21  *
  22  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  25  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  29  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * You should have received a copy of the GNU General Public License along
  34  * with this program; if not, write to the Free Software Foundation, Inc.,
  35  * 675 Mass Ave, Cambridge, MA 02139, USA.
  36  */
  37
  38 #include <linux/pm.h>
  39 #include <linux/sched.h>
  40 #include <linux/proc_fs.h>
  41 #include <linux/pm.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/sysfs.h>
  44 #include <linux/module.h>
  45
  46 #include <asm/io.h>
  47 #include <asm/irq.h>
  48 #include <asm/atomic.h>
  49 #include <asm/mach/time.h>
  50 #include <asm/mach/irq.h>
  51 #include <asm/mach-types.h>
  52
  53 #include <asm/arch/irqs.h>
  54 #include <asm/arch/clock.h>
  55 #include <asm/arch/sram.h>
  56 #include <asm/arch/tc.h>
  57 #include <asm/arch/pm.h>
  58 #include <asm/arch/mux.h>
  59 #include <asm/arch/tps65010.h>
  60 #include <asm/arch/dma.h>
  61 #include <asm/arch/dsp_common.h>
  62 #include <asm/arch/dmtimer.h>
  63
  64 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
  65 static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
  66 static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE];
  67 static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
  68 static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
  69
  70 static unsigned short enable_dyn_sleep = 1;
  71
  72 static ssize_t omap_pm_sleep_while_idle_show(struct subsystem * subsys, char *buf)
  73 {
  74         return sprintf(buf, "%hu\n", enable_dyn_sleep);
  75 }
  76
  77 static ssize_t omap_pm_sleep_while_idle_store(struct subsystem * subsys,
  78                                               const char * buf,
  79                                               size_t n)
  80 {
  81         unsigned short value;
  82         if (sscanf(buf, "%hu", &value) != 1 ||
  83             (value != 0 && value != 1)) {
  84                 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
  85                 return -EINVAL;
  86         }
  87         enable_dyn_sleep = value;
  88         return n;
  89 }
  90
  91 static struct subsys_attribute sleep_while_idle_attr = {
  92         .attr   = {
  93                 .name = __stringify(sleep_while_idle),
  94                 .mode = 0644,
  95         },
  96         .show   = omap_pm_sleep_while_idle_show,
  97         .store  = omap_pm_sleep_while_idle_store,
  98 };
  99
 100 extern struct subsystem power_subsys;
 101 static void (*omap_sram_idle)(void) = NULL;
 102 static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
 103
 104 /*
 105  * Let's power down on idle, but only if we are really
 106  * idle, because once we start down the path of
 107  * going idle we continue to do idle even if we get
 108  * a clock tick interrupt . .
 109  */
 110 void omap_pm_idle(void)
 111 {
 112         extern __u32 arm_idlect1_mask;
 113         __u32 use_idlect1 = arm_idlect1_mask;
 114         int do_sleep;
 115
 116         local_irq_disable();
 117         local_fiq_disable();
 118         if (need_resched()) {
 119                 local_fiq_enable();
 120                 local_irq_enable();
 121                 return;
 122         }
 123
 124         /*
 125          * Since an interrupt may set up a timer, we don't want to
 126          * reprogram the hardware timer with interrupts enabled.
 127          * Re-enable interrupts only after returning from idle.
 128          */
 129         timer_dyn_reprogram();
 130
 131 #ifdef CONFIG_OMAP_MPU_TIMER
 132 #warning Enable 32kHz OS timer in order to allow sleep states in idle
 133         use_idlect1 = use_idlect1 & ~(1 << 9);
 134 #else
 135
 136         do_sleep = 0;
 137         while (enable_dyn_sleep) {
 138                 extern int vbus_active;
 139
 140 #ifdef CONFIG_CBUS_TAHVO_USB
 141                 /* Clock requirements? */
 142                 if (vbus_active)
 143                         break;
 144 #endif
 145                 do_sleep = 1;
 146                 break;
 147         }
 148
 149 #ifdef CONFIG_OMAP_DM_TIMER
 150         use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
 151 #endif
 152
 153         if (omap_dma_running()) {
 154                 use_idlect1 &= ~(1 << 6);
 155                 if (omap_lcd_dma_ext_running())
 156                         use_idlect1 &= ~(1 << 12);
 157         }
 158
 159         /* We should be able to remove the do_sleep variable and multiple
 160          * tests above as soon as drivers, timer and DMA code have been fixed.
 161          * Even the sleep block count should become obsolete. */
 162         if ((use_idlect1 != ~0) || !do_sleep) {
 163
 164                 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
 165                 if (cpu_is_omap1510())
 166                         use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST;
 167                 else
 168                         use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL;
 169                 omap_writel(use_idlect1, ARM_IDLECT1);
 170                 __asm__ volatile ("mcr  p15, 0, r0, c7, c0, 4");
 171                 omap_writel(saved_idlect1, ARM_IDLECT1);
 172
 173                 local_fiq_enable();
 174                 local_irq_enable();
 175                 return;
 176         }
 177         omap_sram_suspend(omap_readl(ARM_IDLECT1),
 178                           omap_readl(ARM_IDLECT2));
 179 #endif
 180
 181         local_fiq_enable();
 182         local_irq_enable();
 183 }
 184
 185 /*
 186  * Configuration of the wakeup event is board specific. For the
 187  * moment we put it into this helper function. Later it may move
 188  * to board specific files.
 189  */
 190 static void omap_pm_wakeup_setup(void)
 191 {
 192         u32 level1_wake = 0;
 193         u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
 194
 195         /*
 196          * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
 197          * and the L2 wakeup interrupts: keypad and UART2. Note that the
 198          * drivers must still separately call omap_set_gpio_wakeup() to
 199          * wake up to a GPIO interrupt.
 200          */
 201         if (cpu_is_omap730())
 202                 level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) |
 203                         OMAP_IRQ_BIT(INT_730_IH2_IRQ);
 204         else if (cpu_is_omap1510())
 205                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
 206                         OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
 207         else if (cpu_is_omap16xx())
 208                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
 209                         OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
 210
 211         omap_writel(~level1_wake, OMAP_IH1_MIR);
 212
 213         if (cpu_is_omap730()) {
 214                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
 215                 omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) |
 216                                 OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)),
 217                                 OMAP_IH2_1_MIR);
 218         } else if (cpu_is_omap1510()) {
 219                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
 220                 omap_writel(~level2_wake,  OMAP_IH2_MIR);
 221         } else if (cpu_is_omap16xx()) {
 222                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
 223                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
 224
 225                 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
 226                 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ),
 227                             OMAP_IH2_1_MIR);
 228                 omap_writel(~0x0, OMAP_IH2_2_MIR);
 229                 omap_writel(~0x0, OMAP_IH2_3_MIR);
 230         }
 231
 232         /*  New IRQ agreement, recalculate in cascade order */
 233         omap_writel(1, OMAP_IH2_CONTROL);
 234         omap_writel(1, OMAP_IH1_CONTROL);
 235 }
 236
 237 void omap_pm_suspend(void)
 238 {
 239         unsigned long arg0 = 0, arg1 = 0;
 240
 241         printk("PM: OMAP%x is trying to enter deep sleep...\n", system_rev);
 242
 243         omap_serial_wake_trigger(1);
 244
 245         if (machine_is_omap_osk()) {
 246                 /* Stop LED1 (D9) blink */
 247                 tps65010_set_led(LED1, OFF);
 248         }
 249
 250         omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
 251
 252         /*
 253          * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
 254          */
 255
 256         local_irq_disable();
 257         local_fiq_disable();
 258
 259         /*
 260          * Step 2: save registers
 261          *
 262          * The omap is a strange/beautiful device. The caches, memory
 263          * and register state are preserved across power saves.
 264          * We have to save and restore very little register state to
 265          * idle the omap.
 266          *
 267          * Save interrupt, MPUI, ARM and UPLD control registers.
 268          */
 269
 270         if (cpu_is_omap730()) {
 271                 MPUI730_SAVE(OMAP_IH1_MIR);
 272                 MPUI730_SAVE(OMAP_IH2_0_MIR);
 273                 MPUI730_SAVE(OMAP_IH2_1_MIR);
 274                 MPUI730_SAVE(MPUI_CTRL);
 275                 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
 276                 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
 277                 MPUI730_SAVE(EMIFS_CONFIG);
 278                 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
 279
 280         } else if (cpu_is_omap1510()) {
 281                 MPUI1510_SAVE(OMAP_IH1_MIR);
 282                 MPUI1510_SAVE(OMAP_IH2_MIR);
 283                 MPUI1510_SAVE(MPUI_CTRL);
 284                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
 285                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
 286                 MPUI1510_SAVE(EMIFS_CONFIG);
 287                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
 288         } else if (cpu_is_omap16xx()) {
 289                 MPUI1610_SAVE(OMAP_IH1_MIR);
 290                 MPUI1610_SAVE(OMAP_IH2_0_MIR);
 291                 MPUI1610_SAVE(OMAP_IH2_1_MIR);
 292                 MPUI1610_SAVE(OMAP_IH2_2_MIR);
 293                 MPUI1610_SAVE(OMAP_IH2_3_MIR);
 294                 MPUI1610_SAVE(MPUI_CTRL);
 295                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
 296                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
 297                 MPUI1610_SAVE(EMIFS_CONFIG);
 298                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
 299         }
 300
 301         ARM_SAVE(ARM_CKCTL);
 302         ARM_SAVE(ARM_IDLECT1);
 303         ARM_SAVE(ARM_IDLECT2);
 304         if (!(cpu_is_omap1510()))
 305                 ARM_SAVE(ARM_IDLECT3);
 306         ARM_SAVE(ARM_EWUPCT);
 307         ARM_SAVE(ARM_RSTCT1);
 308         ARM_SAVE(ARM_RSTCT2);
 309         ARM_SAVE(ARM_SYSST);
 310         ULPD_SAVE(ULPD_CLOCK_CTRL);
 311         ULPD_SAVE(ULPD_STATUS_REQ);
 312
 313         /* (Step 3 removed - we now allow deep sleep by default) */
 314
 315         /*
 316          * Step 4: OMAP DSP Shutdown
 317          */
 318
 319         omap_dsp_pm_suspend();
 320
 321         /*
 322          * Step 5: Wakeup Event Setup
 323          */
 324
 325         omap_pm_wakeup_setup();
 326
 327         /*
 328          * Step 6: ARM and Traffic controller shutdown
 329          */
 330
 331         /* disable ARM watchdog */
 332         omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
 333         omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
 334
 335         /*
 336          * Step 6b: ARM and Traffic controller shutdown
 337          *
 338          * Step 6 continues here. Prepare jump to power management
 339          * assembly code in internal SRAM.
 340          *
 341          * Since the omap_cpu_suspend routine has been copied to
 342          * SRAM, we'll do an indirect procedure call to it and pass the
 343          * contents of arm_idlect1 and arm_idlect2 so it can restore
 344          * them when it wakes up and it will return.
 345          */
 346
 347         arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
 348         arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
 349
 350         /*
 351          * Step 6c: ARM and Traffic controller shutdown
 352          *
 353          * Jump to assembly code. The processor will stay there
 354          * until wake up.
 355          */
 356         omap_sram_suspend(arg0, arg1);
 357
 358         /*
 359          * If we are here, processor is woken up!
 360          */
 361
 362         /* Restore DSP clocks */
 363         omap_dsp_pm_resume();
 364
 365         /*
 366          * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
 367          */
 368
 369         if (!(cpu_is_omap1510()))
 370                 ARM_RESTORE(ARM_IDLECT3);
 371         ARM_RESTORE(ARM_CKCTL);
 372         ARM_RESTORE(ARM_EWUPCT);
 373         ARM_RESTORE(ARM_RSTCT1);
 374         ARM_RESTORE(ARM_RSTCT2);
 375         ARM_RESTORE(ARM_SYSST);
 376         ULPD_RESTORE(ULPD_CLOCK_CTRL);
 377         ULPD_RESTORE(ULPD_STATUS_REQ);
 378
 379         if (cpu_is_omap730()) {
 380                 MPUI730_RESTORE(EMIFS_CONFIG);
 381                 MPUI730_RESTORE(EMIFF_SDRAM_CONFIG);
 382                 MPUI730_RESTORE(OMAP_IH1_MIR);
 383                 MPUI730_RESTORE(OMAP_IH2_0_MIR);
 384                 MPUI730_RESTORE(OMAP_IH2_1_MIR);
 385         } else if (cpu_is_omap1510()) {
 386                 MPUI1510_RESTORE(MPUI_CTRL);
 387                 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
 388                 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
 389                 MPUI1510_RESTORE(EMIFS_CONFIG);
 390                 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
 391                 MPUI1510_RESTORE(OMAP_IH1_MIR);
 392                 MPUI1510_RESTORE(OMAP_IH2_MIR);
 393         } else if (cpu_is_omap16xx()) {
 394                 MPUI1610_RESTORE(MPUI_CTRL);
 395                 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
 396                 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
 397                 MPUI1610_RESTORE(EMIFS_CONFIG);
 398                 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
 399
 400                 MPUI1610_RESTORE(OMAP_IH1_MIR);
 401                 MPUI1610_RESTORE(OMAP_IH2_0_MIR);
 402                 MPUI1610_RESTORE(OMAP_IH2_1_MIR);
 403                 MPUI1610_RESTORE(OMAP_IH2_2_MIR);
 404                 MPUI1610_RESTORE(OMAP_IH2_3_MIR);
 405         }
 406
 407         omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
 408
 409         /*
 410          * Reenable interrupts
 411          */
 412
 413         local_irq_enable();
 414         local_fiq_enable();
 415
 416         omap_serial_wake_trigger(0);
 417
 418         printk("PM: OMAP%x is re-starting from deep sleep...\n", system_rev);
 419
 420         if (machine_is_omap_osk()) {
 421                 /* Let LED1 (D9) blink again */
 422                 tps65010_set_led(LED1, BLINK);
 423         }
 424 }
 425
 426 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
 427 static int g_read_completed;
 428
 429 /*
 430  * Read system PM registers for debugging
 431  */
 432 static int omap_pm_read_proc(
 433         char *page_buffer,
 434         char **my_first_byte,
 435         off_t virtual_start,
 436         int length,
 437         int *eof,
 438         void *data)
 439 {
 440         int my_buffer_offset = 0;
 441         char * const my_base = page_buffer;
 442
 443         ARM_SAVE(ARM_CKCTL);
 444         ARM_SAVE(ARM_IDLECT1);
 445         ARM_SAVE(ARM_IDLECT2);
 446         if (!(cpu_is_omap1510()))
 447                 ARM_SAVE(ARM_IDLECT3);
 448         ARM_SAVE(ARM_EWUPCT);
 449         ARM_SAVE(ARM_RSTCT1);
 450         ARM_SAVE(ARM_RSTCT2);
 451         ARM_SAVE(ARM_SYSST);
 452
 453         ULPD_SAVE(ULPD_IT_STATUS);
 454         ULPD_SAVE(ULPD_CLOCK_CTRL);
 455         ULPD_SAVE(ULPD_SOFT_REQ);
 456         ULPD_SAVE(ULPD_STATUS_REQ);
 457         ULPD_SAVE(ULPD_DPLL_CTRL);
 458         ULPD_SAVE(ULPD_POWER_CTRL);
 459
 460         if (cpu_is_omap730()) {
 461                 MPUI730_SAVE(MPUI_CTRL);
 462                 MPUI730_SAVE(MPUI_DSP_STATUS);
 463                 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
 464                 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
 465                 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
 466                 MPUI730_SAVE(EMIFS_CONFIG);
 467         } else if (cpu_is_omap1510()) {
 468                 MPUI1510_SAVE(MPUI_CTRL);
 469                 MPUI1510_SAVE(MPUI_DSP_STATUS);
 470                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
 471                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
 472                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
 473                 MPUI1510_SAVE(EMIFS_CONFIG);
 474         } else if (cpu_is_omap16xx()) {
 475                 MPUI1610_SAVE(MPUI_CTRL);
 476                 MPUI1610_SAVE(MPUI_DSP_STATUS);
 477                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
 478                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
 479                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
 480                 MPUI1610_SAVE(EMIFS_CONFIG);
 481         }
 482
 483         if (virtual_start == 0) {
 484                 g_read_completed = 0;
 485
 486                 my_buffer_offset += sprintf(my_base + my_buffer_offset,
 487                    "ARM_CKCTL_REG:            0x%-8x     \n"
 488                    "ARM_IDLECT1_REG:          0x%-8x     \n"
 489                    "ARM_IDLECT2_REG:          0x%-8x     \n"
 490                    "ARM_IDLECT3_REG:          0x%-8x     \n"
 491                    "ARM_EWUPCT_REG:           0x%-8x     \n"
 492                    "ARM_RSTCT1_REG:           0x%-8x     \n"
 493                    "ARM_RSTCT2_REG:           0x%-8x     \n"
 494                    "ARM_SYSST_REG:            0x%-8x     \n"
 495                    "ULPD_IT_STATUS_REG:       0x%-4x     \n"
 496                    "ULPD_CLOCK_CTRL_REG:      0x%-4x     \n"
 497                    "ULPD_SOFT_REQ_REG:        0x%-4x     \n"
 498                    "ULPD_DPLL_CTRL_REG:       0x%-4x     \n"
 499                    "ULPD_STATUS_REQ_REG:      0x%-4x     \n"
 500                    "ULPD_POWER_CTRL_REG:      0x%-4x     \n",
 501                    ARM_SHOW(ARM_CKCTL),
 502                    ARM_SHOW(ARM_IDLECT1),
 503                    ARM_SHOW(ARM_IDLECT2),
 504                    ARM_SHOW(ARM_IDLECT3),
 505                    ARM_SHOW(ARM_EWUPCT),
 506                    ARM_SHOW(ARM_RSTCT1),
 507                    ARM_SHOW(ARM_RSTCT2),
 508                    ARM_SHOW(ARM_SYSST),
 509                    ULPD_SHOW(ULPD_IT_STATUS),
 510                    ULPD_SHOW(ULPD_CLOCK_CTRL),
 511                    ULPD_SHOW(ULPD_SOFT_REQ),
 512                    ULPD_SHOW(ULPD_DPLL_CTRL),
 513                    ULPD_SHOW(ULPD_STATUS_REQ),
 514                    ULPD_SHOW(ULPD_POWER_CTRL));
 515
 516                 if (cpu_is_omap730()) {
 517                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 518                            "MPUI730_CTRL_REG         0x%-8x \n"
 519                            "MPUI730_DSP_STATUS_REG:      0x%-8x \n"
 520                            "MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 521                            "MPUI730_DSP_API_CONFIG_REG:  0x%-8x \n"
 522                            "MPUI730_SDRAM_CONFIG_REG:    0x%-8x \n"
 523                            "MPUI730_EMIFS_CONFIG_REG:    0x%-8x \n",
 524                            MPUI730_SHOW(MPUI_CTRL),
 525                            MPUI730_SHOW(MPUI_DSP_STATUS),
 526                            MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG),
 527                            MPUI730_SHOW(MPUI_DSP_API_CONFIG),
 528                            MPUI730_SHOW(EMIFF_SDRAM_CONFIG),
 529                            MPUI730_SHOW(EMIFS_CONFIG));
 530                 } else if (cpu_is_omap1510()) {
 531                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 532                            "MPUI1510_CTRL_REG             0x%-8x \n"
 533                            "MPUI1510_DSP_STATUS_REG:      0x%-8x \n"
 534                            "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 535                            "MPUI1510_DSP_API_CONFIG_REG:  0x%-8x \n"
 536                            "MPUI1510_SDRAM_CONFIG_REG:    0x%-8x \n"
 537                            "MPUI1510_EMIFS_CONFIG_REG:    0x%-8x \n",
 538                            MPUI1510_SHOW(MPUI_CTRL),
 539                            MPUI1510_SHOW(MPUI_DSP_STATUS),
 540                            MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
 541                            MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
 542                            MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
 543                            MPUI1510_SHOW(EMIFS_CONFIG));
 544                 } else if (cpu_is_omap16xx()) {
 545                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 546                            "MPUI1610_CTRL_REG             0x%-8x \n"
 547                            "MPUI1610_DSP_STATUS_REG:      0x%-8x \n"
 548                            "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 549                            "MPUI1610_DSP_API_CONFIG_REG:  0x%-8x \n"
 550                            "MPUI1610_SDRAM_CONFIG_REG:    0x%-8x \n"
 551                            "MPUI1610_EMIFS_CONFIG_REG:    0x%-8x \n",
 552                            MPUI1610_SHOW(MPUI_CTRL),
 553                            MPUI1610_SHOW(MPUI_DSP_STATUS),
 554                            MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
 555                            MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
 556                            MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
 557                            MPUI1610_SHOW(EMIFS_CONFIG));
 558                 }
 559
 560                 g_read_completed++;
 561         } else if (g_read_completed >= 1) {
 562                  *eof = 1;
 563                  return 0;
 564         }
 565         g_read_completed++;
 566
 567         *my_first_byte = page_buffer;
 568         return  my_buffer_offset;
 569 }
 570
 571 static void omap_pm_init_proc(void)
 572 {
 573         struct proc_dir_entry *entry;
 574
 575         entry = create_proc_read_entry("driver/omap_pm",
 576                                        S_IWUSR | S_IRUGO, NULL,
 577                                        omap_pm_read_proc, NULL);
 578 }
 579
 580 #endif /* DEBUG && CONFIG_PROC_FS */
 581
 582 static void (*saved_idle)(void) = NULL;
 583
 584 /*
 585  *      omap_pm_prepare - Do preliminary suspend work.
 586  *      @state:         suspend state we're entering.
 587  *
 588  */
 589 static int omap_pm_prepare(suspend_state_t state)
 590 {
 591         int error = 0;
 592
 593         /* We cannot sleep in idle until we have resumed */
 594         saved_idle = pm_idle;
 595         pm_idle = NULL;
 596
 597         switch (state)
 598         {
 599         case PM_SUSPEND_STANDBY:
 600         case PM_SUSPEND_MEM:
 601                 break;
 602
 603         case PM_SUSPEND_DISK:
 604                 return -ENOTSUPP;
 605
 606         default:
 607                 return -EINVAL;
 608         }
 609
 610         return error;
 611 }
 612
 613
 614 /*
 615  *      omap_pm_enter - Actually enter a sleep state.
 616  *      @state:         State we're entering.
 617  *
 618  */
 619
 620 static int omap_pm_enter(suspend_state_t state)
 621 {
 622         switch (state)
 623         {
 624         case PM_SUSPEND_STANDBY:
 625         case PM_SUSPEND_MEM:
 626                 omap_pm_suspend();
 627                 break;
 628
 629         case PM_SUSPEND_DISK:
 630                 return -ENOTSUPP;
 631
 632         default:
 633                 return -EINVAL;
 634         }
 635
 636         return 0;
 637 }
 638
 639
 640 /**
 641  *      omap_pm_finish - Finish up suspend sequence.
 642  *      @state:         State we're coming out of.
 643  *
 644  *      This is called after we wake back up (or if entering the sleep state
 645  *      failed).
 646  */
 647
 648 static int omap_pm_finish(suspend_state_t state)
 649 {
 650         pm_idle = saved_idle;
 651         return 0;
 652 }
 653
 654
 655 static irqreturn_t  omap_wakeup_interrupt(int  irq, void *  dev,
 656                                      struct pt_regs *  regs)
 657 {
 658         return IRQ_HANDLED;
 659 }
 660
 661 static struct irqaction omap_wakeup_irq = {
 662         .name           = "peripheral wakeup",
 663         .flags          = SA_INTERRUPT,
 664         .handler        = omap_wakeup_interrupt
 665 };
 666
 667
 668
 669 static struct pm_ops omap_pm_ops ={
 670         .pm_disk_mode = 0,
 671         .prepare        = omap_pm_prepare,
 672         .enter          = omap_pm_enter,
 673         .finish         = omap_pm_finish,
 674 };
 675
 676 static int __init omap_pm_init(void)
 677 {
 678         printk("Power Management for TI OMAP.\n");
 679
 680         /*
 681          * We copy the assembler sleep/wakeup routines to SRAM.
 682          * These routines need to be in SRAM as that's the only
 683          * memory the MPU can see when it wakes up.
 684          */
 685         if (cpu_is_omap730()) {
 686                 omap_sram_idle = omap_sram_push(omap730_idle_loop_suspend,
 687                                                 omap730_idle_loop_suspend_sz);
 688                 omap_sram_suspend = omap_sram_push(omap730_cpu_suspend,
 689                                                    omap730_cpu_suspend_sz);
 690         } else if (cpu_is_omap1510()) {
 691                 omap_sram_idle = omap_sram_push(omap1510_idle_loop_suspend,
 692                                                 omap1510_idle_loop_suspend_sz);
 693                 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
 694                                                    omap1510_cpu_suspend_sz);
 695         } else if (cpu_is_omap16xx()) {
 696                 omap_sram_idle = omap_sram_push(omap1610_idle_loop_suspend,
 697                                                 omap1610_idle_loop_suspend_sz);
 698                 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
 699                                                    omap1610_cpu_suspend_sz);
 700         }
 701
 702         if (omap_sram_idle == NULL || omap_sram_suspend == NULL) {
 703                 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
 704                 return -ENODEV;
 705         }
 706
 707         pm_idle = omap_pm_idle;
 708
 709         if (cpu_is_omap730())
 710                 setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq);
 711         else if (cpu_is_omap16xx())
 712                 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
 713
 714 #if 0
 715         /* --- BEGIN BOARD-DEPENDENT CODE --- */
 716         /* Sleepx mask direction */
 717         omap_writew((omap_readw(0xfffb5008) & ~2), 0xfffb5008);
 718         /* Unmask sleepx signal */
 719         omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);
 720         /* --- END BOARD-DEPENDENT CODE --- */
 721 #endif
 722
 723         /* Program new power ramp-up time
 724          * (0 for most boards since we don't lower voltage when in deep sleep)
 725          */
 726         omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
 727
 728         /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
 729         omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
 730
 731         /* Configure IDLECT3 */
 732         if (cpu_is_omap730())
 733                 omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3);
 734         else if (cpu_is_omap16xx())
 735                 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
 736
 737         pm_set_ops(&omap_pm_ops);
 738
 739 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
 740         omap_pm_init_proc();
 741 #endif
 742
 743         subsys_create_file(&power_subsys, &sleep_while_idle_attr);
 744
 745         if (cpu_is_omap16xx()) {
 746                 /* configure LOW_PWR pin */
 747                 omap_cfg_reg(T20_1610_LOW_PWR);
 748         }
 749
 750         return 0;
 751 }
 752 __initcall(omap_pm_init);