arch/arm/mach-omap1/pm.c

   1 /*
   2  * linux/arch/arm/mach-omap1/pm.c
   3  *
   4  * OMAP Power Management Routines
   5  *
   6  * Original code for the SA11x0:
   7  * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
   8  *
   9  * Modified for the PXA250 by Nicolas Pitre:
  10  * Copyright (c) 2002 Monta Vista Software, Inc.
  11  *
  12  * Modified for the OMAP1510 by David Singleton:
  13  * Copyright (c) 2002 Monta Vista Software, Inc.
  14  *
  15  * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
  16  *
  17  * This program is free software; you can redistribute it and/or modify it
  18  * under the terms of the GNU General Public License as published by the
  19  * Free Software Foundation; either version 2 of the License, or (at your
  20  * option) any later version.
  21  *
  22  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  25  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  29  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * You should have received a copy of the GNU General Public License along
  34  * with this program; if not, write to the Free Software Foundation, Inc.,
  35  * 675 Mass Ave, Cambridge, MA 02139, USA.
  36  */
  37
  38 #include <linux/suspend.h>
  39 #include <linux/sched.h>
  40 #include <linux/proc_fs.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/sysfs.h>
  43 #include <linux/module.h>
  44
  45 #include <asm/io.h>
  46 #include <asm/irq.h>
  47 #include <asm/atomic.h>
  48 #include <asm/mach/time.h>
  49 #include <asm/mach/irq.h>
  50 #include <asm/mach-types.h>
  51
  52 #include <asm/arch/cpu.h>
  53 #include <asm/arch/irqs.h>
  54 #include <asm/arch/clock.h>
  55 #include <asm/arch/sram.h>
  56 #include <asm/arch/tc.h>
  57 #include <asm/arch/pm.h>
  58 #include <asm/arch/mux.h>
  59 #include <asm/arch/dma.h>
  60 #include <asm/arch/dmtimer.h>
  61
  62 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
  63 static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
  64 static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
  65 static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE];
  66 static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
  67 static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
  68
  69 static unsigned short enable_dyn_sleep = 1;
  70
  71 static ssize_t omap_pm_sleep_while_idle_show(struct kset *kset, char *buf)
  72 {
  73         return sprintf(buf, "%hu\n", enable_dyn_sleep);
  74 }
  75
  76 static ssize_t omap_pm_sleep_while_idle_store(struct kset *kset,
  77                                               const char * buf,
  78                                               size_t n)
  79 {
  80         unsigned short value;
  81         if (sscanf(buf, "%hu", &value) != 1 ||
  82             (value != 0 && value != 1)) {
  83                 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
  84                 return -EINVAL;
  85         }
  86         enable_dyn_sleep = value;
  87         return n;
  88 }
  89
  90 static struct subsys_attribute sleep_while_idle_attr = {
  91         .attr   = {
  92                 .name = __stringify(sleep_while_idle),
  93                 .mode = 0644,
  94         },
  95         .show   = omap_pm_sleep_while_idle_show,
  96         .store  = omap_pm_sleep_while_idle_store,
  97 };
  98
  99 static void (*omap_sram_idle)(void) = NULL;
 100 static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
 101
 102 /*
 103  * Let's power down on idle, but only if we are really
 104  * idle, because once we start down the path of
 105  * going idle we continue to do idle even if we get
 106  * a clock tick interrupt . .
 107  */
 108 void omap_pm_idle(void)
 109 {
 110         extern __u32 arm_idlect1_mask;
 111         __u32 use_idlect1 = arm_idlect1_mask;
 112 #ifndef CONFIG_OMAP_MPU_TIMER
 113         int do_sleep;
 114 #endif
 115
 116         local_irq_disable();
 117         local_fiq_disable();
 118         if (need_resched()) {
 119                 local_fiq_enable();
 120                 local_irq_enable();
 121                 return;
 122         }
 123
 124         /*
 125          * Since an interrupt may set up a timer, we don't want to
 126          * reprogram the hardware timer with interrupts enabled.
 127          * Re-enable interrupts only after returning from idle.
 128          */
 129         timer_dyn_reprogram();
 130
 131 #ifdef CONFIG_OMAP_MPU_TIMER
 132 #warning Enable 32kHz OS timer in order to allow sleep states in idle
 133         use_idlect1 = use_idlect1 & ~(1 << 9);
 134 #else
 135
 136         do_sleep = 0;
 137         while (enable_dyn_sleep) {
 138
 139 #ifdef CONFIG_CBUS_TAHVO_USB
 140                 extern int vbus_active;
 141                 /* Clock requirements? */
 142                 if (vbus_active)
 143                         break;
 144 #endif
 145                 do_sleep = 1;
 146                 break;
 147         }
 148
 149 #ifdef CONFIG_OMAP_DM_TIMER
 150         use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
 151 #endif
 152
 153         if (omap_dma_running())
 154                 use_idlect1 &= ~(1 << 6);
 155
 156         /* We should be able to remove the do_sleep variable and multiple
 157          * tests above as soon as drivers, timer and DMA code have been fixed.
 158          * Even the sleep block count should become obsolete. */
 159         if ((use_idlect1 != ~0) || !do_sleep) {
 160
 161                 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
 162                 if (cpu_is_omap15xx())
 163                         use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST;
 164                 else
 165                         use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL;
 166                 omap_writel(use_idlect1, ARM_IDLECT1);
 167                 __asm__ volatile ("mcr  p15, 0, r0, c7, c0, 4");
 168                 omap_writel(saved_idlect1, ARM_IDLECT1);
 169
 170                 local_fiq_enable();
 171                 local_irq_enable();
 172                 return;
 173         }
 174         omap_sram_suspend(omap_readl(ARM_IDLECT1),
 175                           omap_readl(ARM_IDLECT2));
 176 #endif
 177
 178         local_fiq_enable();
 179         local_irq_enable();
 180 }
 181
 182 /*
 183  * Configuration of the wakeup event is board specific. For the
 184  * moment we put it into this helper function. Later it may move
 185  * to board specific files.
 186  */
 187 static void omap_pm_wakeup_setup(void)
 188 {
 189         u32 level1_wake = 0;
 190         u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
 191
 192         /*
 193          * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
 194          * and the L2 wakeup interrupts: keypad and UART2. Note that the
 195          * drivers must still separately call omap_set_gpio_wakeup() to
 196          * wake up to a GPIO interrupt.
 197          */
 198         if (cpu_is_omap730())
 199                 level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) |
 200                         OMAP_IRQ_BIT(INT_730_IH2_IRQ);
 201         else if (cpu_is_omap15xx())
 202                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
 203                         OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
 204         else if (cpu_is_omap16xx())
 205                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
 206                         OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
 207
 208         omap_writel(~level1_wake, OMAP_IH1_MIR);
 209
 210         if (cpu_is_omap730()) {
 211                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
 212                 omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) |
 213                                 OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)),
 214                                 OMAP_IH2_1_MIR);
 215         } else if (cpu_is_omap15xx()) {
 216                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
 217                 omap_writel(~level2_wake,  OMAP_IH2_MIR);
 218         } else if (cpu_is_omap16xx()) {
 219                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
 220                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
 221
 222                 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
 223                 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ),
 224                             OMAP_IH2_1_MIR);
 225                 omap_writel(~0x0, OMAP_IH2_2_MIR);
 226                 omap_writel(~0x0, OMAP_IH2_3_MIR);
 227         }
 228
 229         /*  New IRQ agreement, recalculate in cascade order */
 230         omap_writel(1, OMAP_IH2_CONTROL);
 231         omap_writel(1, OMAP_IH1_CONTROL);
 232 }
 233
 234 #define EN_DSPCK        13      /* ARM_CKCTL */
 235 #define EN_APICK        6       /* ARM_IDLECT2 */
 236 #define DSP_EN          1       /* ARM_RSTCT1 */
 237
 238 void omap_pm_suspend(void)
 239 {
 240         unsigned long arg0 = 0, arg1 = 0;
 241
 242         printk("PM: OMAP%x is trying to enter deep sleep...\n", system_rev);
 243
 244         omap_serial_wake_trigger(1);
 245
 246         if (!cpu_is_omap15xx())
 247                 omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
 248
 249         /*
 250          * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
 251          */
 252
 253         local_irq_disable();
 254         local_fiq_disable();
 255
 256         /*
 257          * Step 2: save registers
 258          *
 259          * The omap is a strange/beautiful device. The caches, memory
 260          * and register state are preserved across power saves.
 261          * We have to save and restore very little register state to
 262          * idle the omap.
 263          *
 264          * Save interrupt, MPUI, ARM and UPLD control registers.
 265          */
 266
 267         if (cpu_is_omap730()) {
 268                 MPUI730_SAVE(OMAP_IH1_MIR);
 269                 MPUI730_SAVE(OMAP_IH2_0_MIR);
 270                 MPUI730_SAVE(OMAP_IH2_1_MIR);
 271                 MPUI730_SAVE(MPUI_CTRL);
 272                 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
 273                 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
 274                 MPUI730_SAVE(EMIFS_CONFIG);
 275                 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
 276
 277         } else if (cpu_is_omap15xx()) {
 278                 MPUI1510_SAVE(OMAP_IH1_MIR);
 279                 MPUI1510_SAVE(OMAP_IH2_MIR);
 280                 MPUI1510_SAVE(MPUI_CTRL);
 281                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
 282                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
 283                 MPUI1510_SAVE(EMIFS_CONFIG);
 284                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
 285         } else if (cpu_is_omap16xx()) {
 286                 MPUI1610_SAVE(OMAP_IH1_MIR);
 287                 MPUI1610_SAVE(OMAP_IH2_0_MIR);
 288                 MPUI1610_SAVE(OMAP_IH2_1_MIR);
 289                 MPUI1610_SAVE(OMAP_IH2_2_MIR);
 290                 MPUI1610_SAVE(OMAP_IH2_3_MIR);
 291                 MPUI1610_SAVE(MPUI_CTRL);
 292                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
 293                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
 294                 MPUI1610_SAVE(EMIFS_CONFIG);
 295                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
 296         }
 297
 298         ARM_SAVE(ARM_CKCTL);
 299         ARM_SAVE(ARM_IDLECT1);
 300         ARM_SAVE(ARM_IDLECT2);
 301         if (!(cpu_is_omap15xx()))
 302                 ARM_SAVE(ARM_IDLECT3);
 303         ARM_SAVE(ARM_EWUPCT);
 304         ARM_SAVE(ARM_RSTCT1);
 305         ARM_SAVE(ARM_RSTCT2);
 306         ARM_SAVE(ARM_SYSST);
 307         ULPD_SAVE(ULPD_CLOCK_CTRL);
 308         ULPD_SAVE(ULPD_STATUS_REQ);
 309
 310         /* (Step 3 removed - we now allow deep sleep by default) */
 311
 312         /*
 313          * Step 4: OMAP DSP Shutdown
 314          */
 315
 316         /* stop DSP */
 317         omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
 318
 319                 /* shut down dsp_ck */
 320         if (!cpu_is_omap730())
 321                 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
 322
 323         /* temporarily enabling api_ck to access DSP registers */
 324         omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
 325
 326         /* save DSP registers */
 327         DSP_SAVE(DSP_IDLECT2);
 328
 329         /* Stop all DSP domain clocks */
 330         __raw_writew(0, DSP_IDLECT2);
 331
 332         /*
 333          * Step 5: Wakeup Event Setup
 334          */
 335
 336         omap_pm_wakeup_setup();
 337
 338         /*
 339          * Step 6: ARM and Traffic controller shutdown
 340          */
 341
 342         /* disable ARM watchdog */
 343         omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
 344         omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
 345
 346         /*
 347          * Step 6b: ARM and Traffic controller shutdown
 348          *
 349          * Step 6 continues here. Prepare jump to power management
 350          * assembly code in internal SRAM.
 351          *
 352          * Since the omap_cpu_suspend routine has been copied to
 353          * SRAM, we'll do an indirect procedure call to it and pass the
 354          * contents of arm_idlect1 and arm_idlect2 so it can restore
 355          * them when it wakes up and it will return.
 356          */
 357
 358         arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
 359         arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
 360
 361         /*
 362          * Step 6c: ARM and Traffic controller shutdown
 363          *
 364          * Jump to assembly code. The processor will stay there
 365          * until wake up.
 366          */
 367         omap_sram_suspend(arg0, arg1);
 368
 369         /*
 370          * If we are here, processor is woken up!
 371          */
 372
 373         /*
 374          * Restore DSP clocks
 375          */
 376
 377         /* again temporarily enabling api_ck to access DSP registers */
 378         omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
 379
 380         /* Restore DSP domain clocks */
 381         DSP_RESTORE(DSP_IDLECT2);
 382
 383         /*
 384          * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
 385          */
 386
 387         if (!(cpu_is_omap15xx()))
 388                 ARM_RESTORE(ARM_IDLECT3);
 389         ARM_RESTORE(ARM_CKCTL);
 390         ARM_RESTORE(ARM_EWUPCT);
 391         ARM_RESTORE(ARM_RSTCT1);
 392         ARM_RESTORE(ARM_RSTCT2);
 393         ARM_RESTORE(ARM_SYSST);
 394         ULPD_RESTORE(ULPD_CLOCK_CTRL);
 395         ULPD_RESTORE(ULPD_STATUS_REQ);
 396
 397         if (cpu_is_omap730()) {
 398                 MPUI730_RESTORE(EMIFS_CONFIG);
 399                 MPUI730_RESTORE(EMIFF_SDRAM_CONFIG);
 400                 MPUI730_RESTORE(OMAP_IH1_MIR);
 401                 MPUI730_RESTORE(OMAP_IH2_0_MIR);
 402                 MPUI730_RESTORE(OMAP_IH2_1_MIR);
 403         } else if (cpu_is_omap15xx()) {
 404                 MPUI1510_RESTORE(MPUI_CTRL);
 405                 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
 406                 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
 407                 MPUI1510_RESTORE(EMIFS_CONFIG);
 408                 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
 409                 MPUI1510_RESTORE(OMAP_IH1_MIR);
 410                 MPUI1510_RESTORE(OMAP_IH2_MIR);
 411         } else if (cpu_is_omap16xx()) {
 412                 MPUI1610_RESTORE(MPUI_CTRL);
 413                 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
 414                 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
 415                 MPUI1610_RESTORE(EMIFS_CONFIG);
 416                 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
 417
 418                 MPUI1610_RESTORE(OMAP_IH1_MIR);
 419                 MPUI1610_RESTORE(OMAP_IH2_0_MIR);
 420                 MPUI1610_RESTORE(OMAP_IH2_1_MIR);
 421                 MPUI1610_RESTORE(OMAP_IH2_2_MIR);
 422                 MPUI1610_RESTORE(OMAP_IH2_3_MIR);
 423         }
 424
 425         if (!cpu_is_omap15xx())
 426                 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
 427
 428         /*
 429          * Re-enable interrupts
 430          */
 431
 432         local_irq_enable();
 433         local_fiq_enable();
 434
 435         omap_serial_wake_trigger(0);
 436
 437         printk("PM: OMAP%x is re-starting from deep sleep...\n", system_rev);
 438 }
 439
 440 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
 441 static int g_read_completed;
 442
 443 /*
 444  * Read system PM registers for debugging
 445  */
 446 static int omap_pm_read_proc(
 447         char *page_buffer,
 448         char **my_first_byte,
 449         off_t virtual_start,
 450         int length,
 451         int *eof,
 452         void *data)
 453 {
 454         int my_buffer_offset = 0;
 455         char * const my_base = page_buffer;
 456
 457         ARM_SAVE(ARM_CKCTL);
 458         ARM_SAVE(ARM_IDLECT1);
 459         ARM_SAVE(ARM_IDLECT2);
 460         if (!(cpu_is_omap15xx()))
 461                 ARM_SAVE(ARM_IDLECT3);
 462         ARM_SAVE(ARM_EWUPCT);
 463         ARM_SAVE(ARM_RSTCT1);
 464         ARM_SAVE(ARM_RSTCT2);
 465         ARM_SAVE(ARM_SYSST);
 466
 467         ULPD_SAVE(ULPD_IT_STATUS);
 468         ULPD_SAVE(ULPD_CLOCK_CTRL);
 469         ULPD_SAVE(ULPD_SOFT_REQ);
 470         ULPD_SAVE(ULPD_STATUS_REQ);
 471         ULPD_SAVE(ULPD_DPLL_CTRL);
 472         ULPD_SAVE(ULPD_POWER_CTRL);
 473
 474         if (cpu_is_omap730()) {
 475                 MPUI730_SAVE(MPUI_CTRL);
 476                 MPUI730_SAVE(MPUI_DSP_STATUS);
 477                 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
 478                 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
 479                 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
 480                 MPUI730_SAVE(EMIFS_CONFIG);
 481         } else if (cpu_is_omap15xx()) {
 482                 MPUI1510_SAVE(MPUI_CTRL);
 483                 MPUI1510_SAVE(MPUI_DSP_STATUS);
 484                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
 485                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
 486                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
 487                 MPUI1510_SAVE(EMIFS_CONFIG);
 488         } else if (cpu_is_omap16xx()) {
 489                 MPUI1610_SAVE(MPUI_CTRL);
 490                 MPUI1610_SAVE(MPUI_DSP_STATUS);
 491                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
 492                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
 493                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
 494                 MPUI1610_SAVE(EMIFS_CONFIG);
 495         }
 496
 497         if (virtual_start == 0) {
 498                 g_read_completed = 0;
 499
 500                 my_buffer_offset += sprintf(my_base + my_buffer_offset,
 501                    "ARM_CKCTL_REG:            0x%-8x     \n"
 502                    "ARM_IDLECT1_REG:          0x%-8x     \n"
 503                    "ARM_IDLECT2_REG:          0x%-8x     \n"
 504                    "ARM_IDLECT3_REG:          0x%-8x     \n"
 505                    "ARM_EWUPCT_REG:           0x%-8x     \n"
 506                    "ARM_RSTCT1_REG:           0x%-8x     \n"
 507                    "ARM_RSTCT2_REG:           0x%-8x     \n"
 508                    "ARM_SYSST_REG:            0x%-8x     \n"
 509                    "ULPD_IT_STATUS_REG:       0x%-4x     \n"
 510                    "ULPD_CLOCK_CTRL_REG:      0x%-4x     \n"
 511                    "ULPD_SOFT_REQ_REG:        0x%-4x     \n"
 512                    "ULPD_DPLL_CTRL_REG:       0x%-4x     \n"
 513                    "ULPD_STATUS_REQ_REG:      0x%-4x     \n"
 514                    "ULPD_POWER_CTRL_REG:      0x%-4x     \n",
 515                    ARM_SHOW(ARM_CKCTL),
 516                    ARM_SHOW(ARM_IDLECT1),
 517                    ARM_SHOW(ARM_IDLECT2),
 518                    ARM_SHOW(ARM_IDLECT3),
 519                    ARM_SHOW(ARM_EWUPCT),
 520                    ARM_SHOW(ARM_RSTCT1),
 521                    ARM_SHOW(ARM_RSTCT2),
 522                    ARM_SHOW(ARM_SYSST),
 523                    ULPD_SHOW(ULPD_IT_STATUS),
 524                    ULPD_SHOW(ULPD_CLOCK_CTRL),
 525                    ULPD_SHOW(ULPD_SOFT_REQ),
 526                    ULPD_SHOW(ULPD_DPLL_CTRL),
 527                    ULPD_SHOW(ULPD_STATUS_REQ),
 528                    ULPD_SHOW(ULPD_POWER_CTRL));
 529
 530                 if (cpu_is_omap730()) {
 531                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 532                            "MPUI730_CTRL_REG         0x%-8x \n"
 533                            "MPUI730_DSP_STATUS_REG:      0x%-8x \n"
 534                            "MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 535                            "MPUI730_DSP_API_CONFIG_REG:  0x%-8x \n"
 536                            "MPUI730_SDRAM_CONFIG_REG:    0x%-8x \n"
 537                            "MPUI730_EMIFS_CONFIG_REG:    0x%-8x \n",
 538                            MPUI730_SHOW(MPUI_CTRL),
 539                            MPUI730_SHOW(MPUI_DSP_STATUS),
 540                            MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG),
 541                            MPUI730_SHOW(MPUI_DSP_API_CONFIG),
 542                            MPUI730_SHOW(EMIFF_SDRAM_CONFIG),
 543                            MPUI730_SHOW(EMIFS_CONFIG));
 544                 } else if (cpu_is_omap15xx()) {
 545                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 546                            "MPUI1510_CTRL_REG             0x%-8x \n"
 547                            "MPUI1510_DSP_STATUS_REG:      0x%-8x \n"
 548                            "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 549                            "MPUI1510_DSP_API_CONFIG_REG:  0x%-8x \n"
 550                            "MPUI1510_SDRAM_CONFIG_REG:    0x%-8x \n"
 551                            "MPUI1510_EMIFS_CONFIG_REG:    0x%-8x \n",
 552                            MPUI1510_SHOW(MPUI_CTRL),
 553                            MPUI1510_SHOW(MPUI_DSP_STATUS),
 554                            MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
 555                            MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
 556                            MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
 557                            MPUI1510_SHOW(EMIFS_CONFIG));
 558                 } else if (cpu_is_omap16xx()) {
 559                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 560                            "MPUI1610_CTRL_REG             0x%-8x \n"
 561                            "MPUI1610_DSP_STATUS_REG:      0x%-8x \n"
 562                            "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 563                            "MPUI1610_DSP_API_CONFIG_REG:  0x%-8x \n"
 564                            "MPUI1610_SDRAM_CONFIG_REG:    0x%-8x \n"
 565                            "MPUI1610_EMIFS_CONFIG_REG:    0x%-8x \n",
 566                            MPUI1610_SHOW(MPUI_CTRL),
 567                            MPUI1610_SHOW(MPUI_DSP_STATUS),
 568                            MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
 569                            MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
 570                            MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
 571                            MPUI1610_SHOW(EMIFS_CONFIG));
 572                 }
 573
 574                 g_read_completed++;
 575         } else if (g_read_completed >= 1) {
 576                  *eof = 1;
 577                  return 0;
 578         }
 579         g_read_completed++;
 580
 581         *my_first_byte = page_buffer;
 582         return  my_buffer_offset;
 583 }
 584
 585 static void omap_pm_init_proc(void)
 586 {
 587         struct proc_dir_entry *entry;
 588
 589         entry = create_proc_read_entry("driver/omap_pm",
 590                                        S_IWUSR | S_IRUGO, NULL,
 591                                        omap_pm_read_proc, NULL);
 592 }
 593
 594 #endif /* DEBUG && CONFIG_PROC_FS */
 595
 596 static void (*saved_idle)(void) = NULL;
 597
 598 /*
 599  *      omap_pm_prepare - Do preliminary suspend work.
 600  *
 601  */
 602 static int omap_pm_prepare(void)
 603 {
 604         /* We cannot sleep in idle until we have resumed */
 605         saved_idle = pm_idle;
 606         pm_idle = NULL;
 607
 608         return 0;
 609 }
 610
 611
 612 /*
 613  *      omap_pm_enter - Actually enter a sleep state.
 614  *      @state:         State we're entering.
 615  *
 616  */
 617
 618 static int omap_pm_enter(suspend_state_t state)
 619 {
 620         switch (state)
 621         {
 622         case PM_SUSPEND_STANDBY:
 623         case PM_SUSPEND_MEM:
 624                 omap_pm_suspend();
 625                 break;
 626         default:
 627                 return -EINVAL;
 628         }
 629
 630         return 0;
 631 }
 632
 633
 634 /**
 635  *      omap_pm_finish - Finish up suspend sequence.
 636  *
 637  *      This is called after we wake back up (or if entering the sleep state
 638  *      failed).
 639  */
 640
 641 static void omap_pm_finish(void)
 642 {
 643         pm_idle = saved_idle;
 644 }
 645
 646
 647 static irqreturn_t  omap_wakeup_interrupt(int irq, void *dev)
 648 {
 649         return IRQ_HANDLED;
 650 }
 651
 652 static struct irqaction omap_wakeup_irq = {
 653         .name           = "peripheral wakeup",
 654         .flags          = IRQF_DISABLED,
 655         .handler        = omap_wakeup_interrupt
 656 };
 657
 658
 659
 660 static struct platform_suspend_ops omap_pm_ops ={
 661         .prepare        = omap_pm_prepare,
 662         .enter          = omap_pm_enter,
 663         .finish         = omap_pm_finish,
 664         .valid          = suspend_valid_only_mem,
 665 };
 666
 667 static int __init omap_pm_init(void)
 668 {
 669         int error;
 670
 671         printk("Power Management for TI OMAP.\n");
 672
 673         /*
 674          * We copy the assembler sleep/wakeup routines to SRAM.
 675          * These routines need to be in SRAM as that's the only
 676          * memory the MPU can see when it wakes up.
 677          */
 678         if (cpu_is_omap730()) {
 679                 omap_sram_idle = omap_sram_push(omap730_idle_loop_suspend,
 680                                                 omap730_idle_loop_suspend_sz);
 681                 omap_sram_suspend = omap_sram_push(omap730_cpu_suspend,
 682                                                    omap730_cpu_suspend_sz);
 683         } else if (cpu_is_omap15xx()) {
 684                 omap_sram_idle = omap_sram_push(omap1510_idle_loop_suspend,
 685                                                 omap1510_idle_loop_suspend_sz);
 686                 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
 687                                                    omap1510_cpu_suspend_sz);
 688         } else if (cpu_is_omap16xx()) {
 689                 omap_sram_idle = omap_sram_push(omap1610_idle_loop_suspend,
 690                                                 omap1610_idle_loop_suspend_sz);
 691                 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
 692                                                    omap1610_cpu_suspend_sz);
 693         }
 694
 695         if (omap_sram_idle == NULL || omap_sram_suspend == NULL) {
 696                 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
 697                 return -ENODEV;
 698         }
 699
 700         pm_idle = omap_pm_idle;
 701
 702         if (cpu_is_omap730())
 703                 setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq);
 704         else if (cpu_is_omap16xx())
 705                 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
 706
 707         /* Program new power ramp-up time
 708          * (0 for most boards since we don't lower voltage when in deep sleep)
 709          */
 710         omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
 711
 712         /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
 713         omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
 714
 715         /* Configure IDLECT3 */
 716         if (cpu_is_omap730())
 717                 omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3);
 718         else if (cpu_is_omap16xx())
 719                 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
 720
 721         suspend_set_ops(&omap_pm_ops);
 722
 723 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
 724         omap_pm_init_proc();
 725 #endif
 726
 727         error = subsys_create_file(&power_subsys, &sleep_while_idle_attr);
 728         if (error)
 729                 printk(KERN_ERR "subsys_create_file failed: %d\n", error);
 730
 731         if (cpu_is_omap16xx()) {
 732                 /* configure LOW_PWR pin */
 733                 omap_cfg_reg(T20_1610_LOW_PWR);
 734         }
 735
 736         return 0;
 737 }
 738 __initcall(omap_pm_init);