arch/arm/mach-omap1/pm.c

   1 /*
   2  * linux/arch/arm/mach-omap1/pm.c
   3  *
   4  * OMAP Power Management Routines
   5  *
   6  * Original code for the SA11x0:
   7  * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
   8  *
   9  * Modified for the PXA250 by Nicolas Pitre:
  10  * Copyright (c) 2002 Monta Vista Software, Inc.
  11  *
  12  * Modified for the OMAP1510 by David Singleton:
  13  * Copyright (c) 2002 Monta Vista Software, Inc.
  14  *
  15  * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
  16  *
  17  * This program is free software; you can redistribute it and/or modify it
  18  * under the terms of the GNU General Public License as published by the
  19  * Free Software Foundation; either version 2 of the License, or (at your
  20  * option) any later version.
  21  *
  22  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  25  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  29  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * You should have received a copy of the GNU General Public License along
  34  * with this program; if not, write to the Free Software Foundation, Inc.,
  35  * 675 Mass Ave, Cambridge, MA 02139, USA.
  36  */
  37
  38 #include <linux/suspend.h>
  39 #include <linux/sched.h>
  40 #include <linux/proc_fs.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/sysfs.h>
  43 #include <linux/module.h>
  44
  45 #include <asm/io.h>
  46 #include <asm/irq.h>
  47 #include <asm/atomic.h>
  48 #include <asm/mach/time.h>
  49 #include <asm/mach/irq.h>
  50 #include <asm/mach-types.h>
  51
  52 #include <asm/arch/cpu.h>
  53 #include <asm/arch/irqs.h>
  54 #include <asm/arch/clock.h>
  55 #include <asm/arch/sram.h>
  56 #include <asm/arch/tc.h>
  57 #include <asm/arch/pm.h>
  58 #include <asm/arch/mux.h>
  59 #include <asm/arch/dma.h>
  60 #include <asm/arch/dsp_common.h>
  61 #include <asm/arch/dmtimer.h>
  62
  63 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
  64 static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
  65 static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
  66 static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE];
  67 static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
  68 static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
  69
  70 #ifdef CONFIG_OMAP_32K_TIMER
  71
  72 static unsigned short enable_dyn_sleep = 1;
  73
  74 static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
  75                          char *buf)
  76 {
  77         return sprintf(buf, "%hu\n", enable_dyn_sleep);
  78 }
  79
  80 static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
  81                           const char * buf, size_t n)
  82 {
  83         unsigned short value;
  84         if (sscanf(buf, "%hu", &value) != 1 ||
  85             (value != 0 && value != 1)) {
  86                 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
  87                 return -EINVAL;
  88         }
  89         enable_dyn_sleep = value;
  90         return n;
  91 }
  92
  93 static struct kobj_attribute sleep_while_idle_attr =
  94         __ATTR(sleep_while_idle, 0644, idle_show, idle_store);
  95
  96 #endif
  97
  98 static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
  99
 100 /*
 101  * Let's power down on idle, but only if we are really
 102  * idle, because once we start down the path of
 103  * going idle we continue to do idle even if we get
 104  * a clock tick interrupt . .
 105  */
 106 void omap_pm_idle(void)
 107 {
 108         extern __u32 arm_idlect1_mask;
 109         __u32 use_idlect1 = arm_idlect1_mask;
 110         int do_sleep = 0;
 111
 112         local_irq_disable();
 113         local_fiq_disable();
 114         if (need_resched()) {
 115                 local_fiq_enable();
 116                 local_irq_enable();
 117                 return;
 118         }
 119
 120         /*
 121          * Since an interrupt may set up a timer, we don't want to
 122          * reprogram the hardware timer with interrupts enabled.
 123          * Re-enable interrupts only after returning from idle.
 124          */
 125         timer_dyn_reprogram();
 126
 127 #ifdef CONFIG_OMAP_MPU_TIMER
 128 #warning Enable 32kHz OS timer in order to allow sleep states in idle
 129         use_idlect1 = use_idlect1 & ~(1 << 9);
 130 #else
 131
 132         while (enable_dyn_sleep) {
 133
 134 #ifdef CONFIG_CBUS_TAHVO_USB
 135                 extern int vbus_active;
 136                 /* Clock requirements? */
 137                 if (vbus_active)
 138                         break;
 139 #endif
 140                 do_sleep = 1;
 141                 break;
 142         }
 143
 144 #endif
 145
 146 #ifdef CONFIG_OMAP_DM_TIMER
 147         use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
 148 #endif
 149
 150         if (omap_dma_running())
 151                 use_idlect1 &= ~(1 << 6);
 152
 153         /* We should be able to remove the do_sleep variable and multiple
 154          * tests above as soon as drivers, timer and DMA code have been fixed.
 155          * Even the sleep block count should become obsolete. */
 156         if ((use_idlect1 != ~0) || !do_sleep) {
 157
 158                 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
 159                 if (cpu_is_omap15xx())
 160                         use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST;
 161                 else
 162                         use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL;
 163                 omap_writel(use_idlect1, ARM_IDLECT1);
 164                 __asm__ volatile ("mcr  p15, 0, r0, c7, c0, 4");
 165                 omap_writel(saved_idlect1, ARM_IDLECT1);
 166
 167                 local_fiq_enable();
 168                 local_irq_enable();
 169                 return;
 170         }
 171         omap_sram_suspend(omap_readl(ARM_IDLECT1),
 172                           omap_readl(ARM_IDLECT2));
 173
 174         local_fiq_enable();
 175         local_irq_enable();
 176 }
 177
 178 /*
 179  * Configuration of the wakeup event is board specific. For the
 180  * moment we put it into this helper function. Later it may move
 181  * to board specific files.
 182  */
 183 static void omap_pm_wakeup_setup(void)
 184 {
 185         u32 level1_wake = 0;
 186         u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
 187
 188         /*
 189          * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
 190          * and the L2 wakeup interrupts: keypad and UART2. Note that the
 191          * drivers must still separately call omap_set_gpio_wakeup() to
 192          * wake up to a GPIO interrupt.
 193          */
 194         if (cpu_is_omap730())
 195                 level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) |
 196                         OMAP_IRQ_BIT(INT_730_IH2_IRQ);
 197         else if (cpu_is_omap15xx())
 198                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
 199                         OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
 200         else if (cpu_is_omap16xx())
 201                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
 202                         OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
 203
 204         omap_writel(~level1_wake, OMAP_IH1_MIR);
 205
 206         if (cpu_is_omap730()) {
 207                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
 208                 omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) |
 209                                 OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)),
 210                                 OMAP_IH2_1_MIR);
 211         } else if (cpu_is_omap15xx()) {
 212                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
 213                 omap_writel(~level2_wake,  OMAP_IH2_MIR);
 214         } else if (cpu_is_omap16xx()) {
 215                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
 216                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
 217
 218                 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
 219                 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ),
 220                             OMAP_IH2_1_MIR);
 221                 omap_writel(~0x0, OMAP_IH2_2_MIR);
 222                 omap_writel(~0x0, OMAP_IH2_3_MIR);
 223         }
 224
 225         /*  New IRQ agreement, recalculate in cascade order */
 226         omap_writel(1, OMAP_IH2_CONTROL);
 227         omap_writel(1, OMAP_IH1_CONTROL);
 228 }
 229
 230 #define EN_DSPCK        13      /* ARM_CKCTL */
 231 #define EN_APICK        6       /* ARM_IDLECT2 */
 232 #define DSP_EN          1       /* ARM_RSTCT1 */
 233
 234 void omap_pm_suspend(void)
 235 {
 236         unsigned long arg0 = 0, arg1 = 0;
 237
 238         printk("PM: OMAP%x is trying to enter deep sleep...\n", system_rev);
 239
 240         omap_serial_wake_trigger(1);
 241
 242         if (!cpu_is_omap15xx())
 243                 omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
 244
 245         /*
 246          * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
 247          */
 248
 249         local_irq_disable();
 250         local_fiq_disable();
 251
 252         /*
 253          * Step 2: save registers
 254          *
 255          * The omap is a strange/beautiful device. The caches, memory
 256          * and register state are preserved across power saves.
 257          * We have to save and restore very little register state to
 258          * idle the omap.
 259          *
 260          * Save interrupt, MPUI, ARM and UPLD control registers.
 261          */
 262
 263         if (cpu_is_omap730()) {
 264                 MPUI730_SAVE(OMAP_IH1_MIR);
 265                 MPUI730_SAVE(OMAP_IH2_0_MIR);
 266                 MPUI730_SAVE(OMAP_IH2_1_MIR);
 267                 MPUI730_SAVE(MPUI_CTRL);
 268                 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
 269                 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
 270                 MPUI730_SAVE(EMIFS_CONFIG);
 271                 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
 272
 273         } else if (cpu_is_omap15xx()) {
 274                 MPUI1510_SAVE(OMAP_IH1_MIR);
 275                 MPUI1510_SAVE(OMAP_IH2_MIR);
 276                 MPUI1510_SAVE(MPUI_CTRL);
 277                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
 278                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
 279                 MPUI1510_SAVE(EMIFS_CONFIG);
 280                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
 281         } else if (cpu_is_omap16xx()) {
 282                 MPUI1610_SAVE(OMAP_IH1_MIR);
 283                 MPUI1610_SAVE(OMAP_IH2_0_MIR);
 284                 MPUI1610_SAVE(OMAP_IH2_1_MIR);
 285                 MPUI1610_SAVE(OMAP_IH2_2_MIR);
 286                 MPUI1610_SAVE(OMAP_IH2_3_MIR);
 287                 MPUI1610_SAVE(MPUI_CTRL);
 288                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
 289                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
 290                 MPUI1610_SAVE(EMIFS_CONFIG);
 291                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
 292         }
 293
 294         ARM_SAVE(ARM_CKCTL);
 295         ARM_SAVE(ARM_IDLECT1);
 296         ARM_SAVE(ARM_IDLECT2);
 297         if (!(cpu_is_omap15xx()))
 298                 ARM_SAVE(ARM_IDLECT3);
 299         ARM_SAVE(ARM_EWUPCT);
 300         ARM_SAVE(ARM_RSTCT1);
 301         ARM_SAVE(ARM_RSTCT2);
 302         ARM_SAVE(ARM_SYSST);
 303         ULPD_SAVE(ULPD_CLOCK_CTRL);
 304         ULPD_SAVE(ULPD_STATUS_REQ);
 305
 306         /* (Step 3 removed - we now allow deep sleep by default) */
 307
 308         /*
 309          * Step 4: OMAP DSP Shutdown
 310          */
 311
 312         /* stop DSP */
 313         omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
 314
 315                 /* shut down dsp_ck */
 316         if (!cpu_is_omap730())
 317                 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
 318
 319         /* temporarily enabling api_ck to access DSP registers */
 320         omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
 321
 322         /* save DSP registers */
 323         DSP_SAVE(DSP_IDLECT2);
 324
 325         /* Stop all DSP domain clocks */
 326         __raw_writew(0, DSP_IDLECT2);
 327
 328         /*
 329          * Step 5: Wakeup Event Setup
 330          */
 331
 332         omap_pm_wakeup_setup();
 333
 334         /*
 335          * Step 6: ARM and Traffic controller shutdown
 336          */
 337
 338         /* disable ARM watchdog */
 339         omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
 340         omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
 341
 342         /*
 343          * Step 6b: ARM and Traffic controller shutdown
 344          *
 345          * Step 6 continues here. Prepare jump to power management
 346          * assembly code in internal SRAM.
 347          *
 348          * Since the omap_cpu_suspend routine has been copied to
 349          * SRAM, we'll do an indirect procedure call to it and pass the
 350          * contents of arm_idlect1 and arm_idlect2 so it can restore
 351          * them when it wakes up and it will return.
 352          */
 353
 354         arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
 355         arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
 356
 357         /*
 358          * Step 6c: ARM and Traffic controller shutdown
 359          *
 360          * Jump to assembly code. The processor will stay there
 361          * until wake up.
 362          */
 363         omap_sram_suspend(arg0, arg1);
 364
 365         /*
 366          * If we are here, processor is woken up!
 367          */
 368
 369         /*
 370          * Restore DSP clocks
 371          */
 372
 373         /* again temporarily enabling api_ck to access DSP registers */
 374         omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
 375
 376         /* Restore DSP domain clocks */
 377         DSP_RESTORE(DSP_IDLECT2);
 378
 379         /*
 380          * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
 381          */
 382
 383         if (!(cpu_is_omap15xx()))
 384                 ARM_RESTORE(ARM_IDLECT3);
 385         ARM_RESTORE(ARM_CKCTL);
 386         ARM_RESTORE(ARM_EWUPCT);
 387         ARM_RESTORE(ARM_RSTCT1);
 388         ARM_RESTORE(ARM_RSTCT2);
 389         ARM_RESTORE(ARM_SYSST);
 390         ULPD_RESTORE(ULPD_CLOCK_CTRL);
 391         ULPD_RESTORE(ULPD_STATUS_REQ);
 392
 393         if (cpu_is_omap730()) {
 394                 MPUI730_RESTORE(EMIFS_CONFIG);
 395                 MPUI730_RESTORE(EMIFF_SDRAM_CONFIG);
 396                 MPUI730_RESTORE(OMAP_IH1_MIR);
 397                 MPUI730_RESTORE(OMAP_IH2_0_MIR);
 398                 MPUI730_RESTORE(OMAP_IH2_1_MIR);
 399         } else if (cpu_is_omap15xx()) {
 400                 MPUI1510_RESTORE(MPUI_CTRL);
 401                 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
 402                 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
 403                 MPUI1510_RESTORE(EMIFS_CONFIG);
 404                 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
 405                 MPUI1510_RESTORE(OMAP_IH1_MIR);
 406                 MPUI1510_RESTORE(OMAP_IH2_MIR);
 407         } else if (cpu_is_omap16xx()) {
 408                 MPUI1610_RESTORE(MPUI_CTRL);
 409                 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
 410                 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
 411                 MPUI1610_RESTORE(EMIFS_CONFIG);
 412                 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
 413
 414                 MPUI1610_RESTORE(OMAP_IH1_MIR);
 415                 MPUI1610_RESTORE(OMAP_IH2_0_MIR);
 416                 MPUI1610_RESTORE(OMAP_IH2_1_MIR);
 417                 MPUI1610_RESTORE(OMAP_IH2_2_MIR);
 418                 MPUI1610_RESTORE(OMAP_IH2_3_MIR);
 419         }
 420
 421         if (!cpu_is_omap15xx())
 422                 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
 423
 424         /*
 425          * Re-enable interrupts
 426          */
 427
 428         local_irq_enable();
 429         local_fiq_enable();
 430
 431         omap_serial_wake_trigger(0);
 432
 433         printk("PM: OMAP%x is re-starting from deep sleep...\n", system_rev);
 434 }
 435
 436 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
 437 static int g_read_completed;
 438
 439 /*
 440  * Read system PM registers for debugging
 441  */
 442 static int omap_pm_read_proc(
 443         char *page_buffer,
 444         char **my_first_byte,
 445         off_t virtual_start,
 446         int length,
 447         int *eof,
 448         void *data)
 449 {
 450         int my_buffer_offset = 0;
 451         char * const my_base = page_buffer;
 452
 453         ARM_SAVE(ARM_CKCTL);
 454         ARM_SAVE(ARM_IDLECT1);
 455         ARM_SAVE(ARM_IDLECT2);
 456         if (!(cpu_is_omap15xx()))
 457                 ARM_SAVE(ARM_IDLECT3);
 458         ARM_SAVE(ARM_EWUPCT);
 459         ARM_SAVE(ARM_RSTCT1);
 460         ARM_SAVE(ARM_RSTCT2);
 461         ARM_SAVE(ARM_SYSST);
 462
 463         ULPD_SAVE(ULPD_IT_STATUS);
 464         ULPD_SAVE(ULPD_CLOCK_CTRL);
 465         ULPD_SAVE(ULPD_SOFT_REQ);
 466         ULPD_SAVE(ULPD_STATUS_REQ);
 467         ULPD_SAVE(ULPD_DPLL_CTRL);
 468         ULPD_SAVE(ULPD_POWER_CTRL);
 469
 470         if (cpu_is_omap730()) {
 471                 MPUI730_SAVE(MPUI_CTRL);
 472                 MPUI730_SAVE(MPUI_DSP_STATUS);
 473                 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
 474                 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
 475                 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
 476                 MPUI730_SAVE(EMIFS_CONFIG);
 477         } else if (cpu_is_omap15xx()) {
 478                 MPUI1510_SAVE(MPUI_CTRL);
 479                 MPUI1510_SAVE(MPUI_DSP_STATUS);
 480                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
 481                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
 482                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
 483                 MPUI1510_SAVE(EMIFS_CONFIG);
 484         } else if (cpu_is_omap16xx()) {
 485                 MPUI1610_SAVE(MPUI_CTRL);
 486                 MPUI1610_SAVE(MPUI_DSP_STATUS);
 487                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
 488                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
 489                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
 490                 MPUI1610_SAVE(EMIFS_CONFIG);
 491         }
 492
 493         if (virtual_start == 0) {
 494                 g_read_completed = 0;
 495
 496                 my_buffer_offset += sprintf(my_base + my_buffer_offset,
 497                    "ARM_CKCTL_REG:            0x%-8x     \n"
 498                    "ARM_IDLECT1_REG:          0x%-8x     \n"
 499                    "ARM_IDLECT2_REG:          0x%-8x     \n"
 500                    "ARM_IDLECT3_REG:          0x%-8x     \n"
 501                    "ARM_EWUPCT_REG:           0x%-8x     \n"
 502                    "ARM_RSTCT1_REG:           0x%-8x     \n"
 503                    "ARM_RSTCT2_REG:           0x%-8x     \n"
 504                    "ARM_SYSST_REG:            0x%-8x     \n"
 505                    "ULPD_IT_STATUS_REG:       0x%-4x     \n"
 506                    "ULPD_CLOCK_CTRL_REG:      0x%-4x     \n"
 507                    "ULPD_SOFT_REQ_REG:        0x%-4x     \n"
 508                    "ULPD_DPLL_CTRL_REG:       0x%-4x     \n"
 509                    "ULPD_STATUS_REQ_REG:      0x%-4x     \n"
 510                    "ULPD_POWER_CTRL_REG:      0x%-4x     \n",
 511                    ARM_SHOW(ARM_CKCTL),
 512                    ARM_SHOW(ARM_IDLECT1),
 513                    ARM_SHOW(ARM_IDLECT2),
 514                    ARM_SHOW(ARM_IDLECT3),
 515                    ARM_SHOW(ARM_EWUPCT),
 516                    ARM_SHOW(ARM_RSTCT1),
 517                    ARM_SHOW(ARM_RSTCT2),
 518                    ARM_SHOW(ARM_SYSST),
 519                    ULPD_SHOW(ULPD_IT_STATUS),
 520                    ULPD_SHOW(ULPD_CLOCK_CTRL),
 521                    ULPD_SHOW(ULPD_SOFT_REQ),
 522                    ULPD_SHOW(ULPD_DPLL_CTRL),
 523                    ULPD_SHOW(ULPD_STATUS_REQ),
 524                    ULPD_SHOW(ULPD_POWER_CTRL));
 525
 526                 if (cpu_is_omap730()) {
 527                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 528                            "MPUI730_CTRL_REG         0x%-8x \n"
 529                            "MPUI730_DSP_STATUS_REG:      0x%-8x \n"
 530                            "MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 531                            "MPUI730_DSP_API_CONFIG_REG:  0x%-8x \n"
 532                            "MPUI730_SDRAM_CONFIG_REG:    0x%-8x \n"
 533                            "MPUI730_EMIFS_CONFIG_REG:    0x%-8x \n",
 534                            MPUI730_SHOW(MPUI_CTRL),
 535                            MPUI730_SHOW(MPUI_DSP_STATUS),
 536                            MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG),
 537                            MPUI730_SHOW(MPUI_DSP_API_CONFIG),
 538                            MPUI730_SHOW(EMIFF_SDRAM_CONFIG),
 539                            MPUI730_SHOW(EMIFS_CONFIG));
 540                 } else if (cpu_is_omap15xx()) {
 541                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 542                            "MPUI1510_CTRL_REG             0x%-8x \n"
 543                            "MPUI1510_DSP_STATUS_REG:      0x%-8x \n"
 544                            "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 545                            "MPUI1510_DSP_API_CONFIG_REG:  0x%-8x \n"
 546                            "MPUI1510_SDRAM_CONFIG_REG:    0x%-8x \n"
 547                            "MPUI1510_EMIFS_CONFIG_REG:    0x%-8x \n",
 548                            MPUI1510_SHOW(MPUI_CTRL),
 549                            MPUI1510_SHOW(MPUI_DSP_STATUS),
 550                            MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
 551                            MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
 552                            MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
 553                            MPUI1510_SHOW(EMIFS_CONFIG));
 554                 } else if (cpu_is_omap16xx()) {
 555                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 556                            "MPUI1610_CTRL_REG             0x%-8x \n"
 557                            "MPUI1610_DSP_STATUS_REG:      0x%-8x \n"
 558                            "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 559                            "MPUI1610_DSP_API_CONFIG_REG:  0x%-8x \n"
 560                            "MPUI1610_SDRAM_CONFIG_REG:    0x%-8x \n"
 561                            "MPUI1610_EMIFS_CONFIG_REG:    0x%-8x \n",
 562                            MPUI1610_SHOW(MPUI_CTRL),
 563                            MPUI1610_SHOW(MPUI_DSP_STATUS),
 564                            MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
 565                            MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
 566                            MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
 567                            MPUI1610_SHOW(EMIFS_CONFIG));
 568                 }
 569
 570                 g_read_completed++;
 571         } else if (g_read_completed >= 1) {
 572                  *eof = 1;
 573                  return 0;
 574         }
 575         g_read_completed++;
 576
 577         *my_first_byte = page_buffer;
 578         return  my_buffer_offset;
 579 }
 580
 581 static void omap_pm_init_proc(void)
 582 {
 583         struct proc_dir_entry *entry;
 584
 585         entry = create_proc_read_entry("driver/omap_pm",
 586                                        S_IWUSR | S_IRUGO, NULL,
 587                                        omap_pm_read_proc, NULL);
 588 }
 589
 590 #endif /* DEBUG && CONFIG_PROC_FS */
 591
 592 static void (*saved_idle)(void) = NULL;
 593
 594 /*
 595  *      omap_pm_prepare - Do preliminary suspend work.
 596  *
 597  */
 598 static int omap_pm_prepare(void)
 599 {
 600         /* We cannot sleep in idle until we have resumed */
 601         saved_idle = pm_idle;
 602         pm_idle = NULL;
 603
 604         return 0;
 605 }
 606
 607
 608 /*
 609  *      omap_pm_enter - Actually enter a sleep state.
 610  *      @state:         State we're entering.
 611  *
 612  */
 613
 614 static int omap_pm_enter(suspend_state_t state)
 615 {
 616         switch (state)
 617         {
 618         case PM_SUSPEND_STANDBY:
 619         case PM_SUSPEND_MEM:
 620                 omap_pm_suspend();
 621                 break;
 622         default:
 623                 return -EINVAL;
 624         }
 625
 626         return 0;
 627 }
 628
 629
 630 /**
 631  *      omap_pm_finish - Finish up suspend sequence.
 632  *
 633  *      This is called after we wake back up (or if entering the sleep state
 634  *      failed).
 635  */
 636
 637 static void omap_pm_finish(void)
 638 {
 639         pm_idle = saved_idle;
 640 }
 641
 642
 643 static irqreturn_t omap_wakeup_interrupt(int irq, void *dev)
 644 {
 645         return IRQ_HANDLED;
 646 }
 647
 648 static struct irqaction omap_wakeup_irq = {
 649         .name           = "peripheral wakeup",
 650         .flags          = IRQF_DISABLED,
 651         .handler        = omap_wakeup_interrupt
 652 };
 653
 654
 655
 656 static struct platform_suspend_ops omap_pm_ops ={
 657         .prepare        = omap_pm_prepare,
 658         .enter          = omap_pm_enter,
 659         .finish         = omap_pm_finish,
 660         .valid          = suspend_valid_only_mem,
 661 };
 662
 663 static int __init omap_pm_init(void)
 664 {
 665
 666 #ifdef CONFIG_OMAP_32K_TIMER
 667         int error;
 668 #endif
 669
 670         printk("Power Management for TI OMAP.\n");
 671
 672         /*
 673          * We copy the assembler sleep/wakeup routines to SRAM.
 674          * These routines need to be in SRAM as that's the only
 675          * memory the MPU can see when it wakes up.
 676          */
 677         if (cpu_is_omap730()) {
 678                 omap_sram_suspend = omap_sram_push(omap730_cpu_suspend,
 679                                                    omap730_cpu_suspend_sz);
 680         } else if (cpu_is_omap15xx()) {
 681                 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
 682                                                    omap1510_cpu_suspend_sz);
 683         } else if (cpu_is_omap16xx()) {
 684                 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
 685                                                    omap1610_cpu_suspend_sz);
 686         }
 687
 688         if (omap_sram_suspend == NULL) {
 689                 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
 690                 return -ENODEV;
 691         }
 692
 693         pm_idle = omap_pm_idle;
 694
 695         if (cpu_is_omap730())
 696                 setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq);
 697         else if (cpu_is_omap16xx())
 698                 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
 699
 700         /* Program new power ramp-up time
 701          * (0 for most boards since we don't lower voltage when in deep sleep)
 702          */
 703         omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
 704
 705         /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
 706         omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
 707
 708         /* Configure IDLECT3 */
 709         if (cpu_is_omap730())
 710                 omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3);
 711         else if (cpu_is_omap16xx())
 712                 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
 713
 714         suspend_set_ops(&omap_pm_ops);
 715
 716 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
 717         omap_pm_init_proc();
 718 #endif
 719
 720 #ifdef CONFIG_OMAP_32K_TIMER
 721         error = sysfs_create_file(power_kobj, &sleep_while_idle_attr);
 722         if (error)
 723                 printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
 724 #endif
 725
 726         if (cpu_is_omap16xx()) {
 727                 /* configure LOW_PWR pin */
 728                 omap_cfg_reg(T20_1610_LOW_PWR);
 729         }
 730
 731         return 0;
 732 }
 733 __initcall(omap_pm_init);