2 * linux/arch/arm/mach-omap2/mmu.c
4 * Support for non-MPU OMAP1 MMUs.
6 * Copyright (C) 2002-2005 Nokia Corporation
8 * Written by Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
9 * and Paul Mundt <paul.mundt@nokia.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/types.h>
26 #include <linux/init.h>
27 #include <linux/rwsem.h>
28 #include <linux/device.h>
29 #include <linux/kernel.h>
31 #include <linux/err.h>
33 #include <asm/tlbflush.h>
35 static void *dspvect_page;
36 #define DSP_INIT_PAGE 0xfff000
38 static unsigned int get_cam_l_va_mask(u16 pgsz)
41 case OMAP_MMU_CAM_PAGESIZE_1MB:
42 return OMAP_MMU_CAM_L_VA_TAG_L1_MASK |
43 OMAP_MMU_CAM_L_VA_TAG_L2_MASK_1MB;
44 case OMAP_MMU_CAM_PAGESIZE_64KB:
45 return OMAP_MMU_CAM_L_VA_TAG_L1_MASK |
46 OMAP_MMU_CAM_L_VA_TAG_L2_MASK_64KB;
47 case OMAP_MMU_CAM_PAGESIZE_4KB:
48 return OMAP_MMU_CAM_L_VA_TAG_L1_MASK |
49 OMAP_MMU_CAM_L_VA_TAG_L2_MASK_4KB;
50 case OMAP_MMU_CAM_PAGESIZE_1KB:
51 return OMAP_MMU_CAM_L_VA_TAG_L1_MASK |
52 OMAP_MMU_CAM_L_VA_TAG_L2_MASK_1KB;
57 #define get_cam_va_mask(pgsz) \
58 ((u32)OMAP_MMU_CAM_H_VA_TAG_H_MASK << 22 | \
59 (u32)get_cam_l_va_mask(pgsz) << 6)
61 static int intmem_usecount;
64 void dsp_mem_usecount_clear(void)
66 if (intmem_usecount != 0) {
68 "MMU: unbalanced memory request/release detected.\n"
69 " intmem_usecount is not zero at where "
70 "it should be! ... fixed to be zero.\n");
72 omap_dsp_release_mem();
75 EXPORT_SYMBOL_GPL(dsp_mem_usecount_clear);
77 static int omap1_mmu_mem_enable(struct omap_mmu *mmu, void *addr)
81 if (omap_mmu_internal_memory(mmu, addr)) {
82 if (intmem_usecount++ == 0)
83 ret = omap_dsp_request_mem();
90 static int omap1_mmu_mem_disable(struct omap_mmu *mmu, void *addr)
94 if (omap_mmu_internal_memory(mmu, addr)) {
95 if (--intmem_usecount == 0)
96 omap_dsp_release_mem();
104 omap1_mmu_read_tlb(struct omap_mmu *mmu, struct cam_ram_regset *cr)
106 /* read a TLB entry */
107 omap_mmu_write_reg(mmu, OMAP_MMU_LD_TLB_RD, OMAP_MMU_LD_TLB);
109 cr->cam_h = omap_mmu_read_reg(mmu, OMAP_MMU_READ_CAM_H);
110 cr->cam_l = omap_mmu_read_reg(mmu, OMAP_MMU_READ_CAM_L);
111 cr->ram_h = omap_mmu_read_reg(mmu, OMAP_MMU_READ_RAM_H);
112 cr->ram_l = omap_mmu_read_reg(mmu, OMAP_MMU_READ_RAM_L);
116 omap1_mmu_load_tlb(struct omap_mmu *mmu, struct cam_ram_regset *cr)
118 /* Set the CAM and RAM entries */
119 omap_mmu_write_reg(mmu, cr->cam_h, OMAP_MMU_CAM_H);
120 omap_mmu_write_reg(mmu, cr->cam_l, OMAP_MMU_CAM_L);
121 omap_mmu_write_reg(mmu, cr->ram_h, OMAP_MMU_RAM_H);
122 omap_mmu_write_reg(mmu, cr->ram_l, OMAP_MMU_RAM_L);
125 static ssize_t omap1_mmu_show(struct omap_mmu *mmu, char *buf,
126 struct omap_mmu_tlb_lock *tlb_lock)
130 len = sprintf(buf, "P: preserved, V: valid\n"
131 "ety P V size cam_va ram_pa ap\n");
132 /* 00: P V 4KB 0x300000 0x10171800 FA */
134 for (i = 0; i < mmu->nr_tlb_entries; i++) {
135 struct omap_mmu_tlb_entry ent;
136 struct cam_ram_regset cr;
137 struct omap_mmu_tlb_lock entry_lock;
138 char *pgsz_str, *ap_str;
140 /* read a TLB entry */
141 entry_lock.base = tlb_lock->base;
142 entry_lock.victim = i;
143 omap_mmu_read_tlb(mmu, &entry_lock, &cr);
145 ent.pgsz = cr.cam_l & OMAP_MMU_CAM_PAGESIZE_MASK;
146 ent.prsvd = cr.cam_l & OMAP_MMU_CAM_P;
147 ent.valid = cr.cam_l & OMAP_MMU_CAM_V;
148 ent.ap = cr.ram_l & OMAP_MMU_RAM_L_AP_MASK;
149 ent.va = (u32)(cr.cam_h & OMAP_MMU_CAM_H_VA_TAG_H_MASK) << 22 |
150 (u32)(cr.cam_l & get_cam_l_va_mask(ent.pgsz)) << 6;
151 ent.pa = (unsigned long)cr.ram_h << 16 |
152 (cr.ram_l & OMAP_MMU_RAM_L_RAM_LSB_MASK);
154 pgsz_str = (ent.pgsz == OMAP_MMU_CAM_PAGESIZE_1MB) ? " 1MB":
155 (ent.pgsz == OMAP_MMU_CAM_PAGESIZE_64KB) ? "64KB":
156 (ent.pgsz == OMAP_MMU_CAM_PAGESIZE_4KB) ? " 4KB":
157 (ent.pgsz == OMAP_MMU_CAM_PAGESIZE_1KB) ? " 1KB":
159 ap_str = (ent.ap == OMAP_MMU_RAM_L_AP_RO) ? "RO":
160 (ent.ap == OMAP_MMU_RAM_L_AP_FA) ? "FA":
161 (ent.ap == OMAP_MMU_RAM_L_AP_NA) ? "NA":
164 if (i == tlb_lock->base)
165 len += sprintf(buf + len, "lock base = %d\n",
167 if (i == tlb_lock->victim)
168 len += sprintf(buf + len, "victim = %d\n",
170 len += sprintf(buf + len,
171 /* 00: P V 4KB 0x300000 0x10171800 FA */
172 "%02d: %c %c %s 0x%06lx 0x%08lx %s\n",
174 ent.prsvd ? 'P' : ' ',
175 ent.valid ? 'V' : ' ',
176 pgsz_str, ent.va, ent.pa, ap_str);
182 static int exmap_setup_preserved_entries(struct omap_mmu *mmu)
186 exmap_setup_preserved_mem_page(mmu, dspvect_page, DSP_INIT_PAGE, n++);
191 static void exmap_clear_preserved_entries(struct omap_mmu *mmu)
193 exmap_clear_mem_page(mmu, DSP_INIT_PAGE);
196 static int omap1_mmu_startup(struct omap_mmu *mmu)
198 dspvect_page = (void *)__get_dma_pages(GFP_KERNEL, 0);
199 if (dspvect_page == NULL) {
200 printk(KERN_ERR "MMU: failed to allocate memory "
201 "for dsp vector table\n");
205 mmu->nr_exmap_preserved = exmap_setup_preserved_entries(mmu);
210 static void omap1_mmu_shutdown(struct omap_mmu *mmu)
212 exmap_clear_preserved_entries(mmu);
214 if (dspvect_page != NULL) {
217 down_read(&mmu->exmap_sem);
219 virt = (unsigned long)omap_mmu_to_virt(mmu, DSP_INIT_PAGE);
220 flush_tlb_kernel_range(virt, virt + PAGE_SIZE);
221 free_page((unsigned long)dspvect_page);
224 up_read(&mmu->exmap_sem);
228 static inline unsigned long omap1_mmu_cam_va(struct cam_ram_regset *cr)
230 unsigned int page_size = cr->cam_l & OMAP_MMU_CAM_PAGESIZE_MASK;
232 return (u32)(cr->cam_h & OMAP_MMU_CAM_H_VA_TAG_H_MASK) << 22 |
233 (u32)(cr->cam_l & get_cam_l_va_mask(page_size)) << 6;
236 static struct cam_ram_regset *
237 omap1_mmu_cam_ram_alloc(struct omap_mmu_tlb_entry *entry)
239 struct cam_ram_regset *cr;
241 if (entry->va & ~(get_cam_va_mask(entry->pgsz))) {
242 printk(KERN_ERR "MMU: mapping vadr (0x%06lx) is not on an "
243 "aligned boundary\n", entry->va);
244 return ERR_PTR(-EINVAL);
247 cr = kmalloc(sizeof(struct cam_ram_regset), GFP_KERNEL);
249 cr->cam_h = entry->va >> 22;
250 cr->cam_l = (entry->va >> 6 & get_cam_l_va_mask(entry->pgsz)) |
251 entry->prsvd | entry->pgsz;
252 cr->ram_h = entry->pa >> 16;
253 cr->ram_l = (entry->pa & OMAP_MMU_RAM_L_RAM_LSB_MASK) | entry->ap;
258 static inline int omap1_mmu_cam_ram_valid(struct cam_ram_regset *cr)
260 return cr->cam_l & OMAP_MMU_CAM_V;
263 static void omap1_mmu_interrupt(struct omap_mmu *mmu)
265 unsigned long status;
266 unsigned long adh, adl;
270 status = omap_mmu_read_reg(mmu, MMU_FAULT_ST);
271 adh = omap_mmu_read_reg(mmu, MMU_FAULT_AD_H);
272 adl = omap_mmu_read_reg(mmu, MMU_FAULT_AD_L);
273 dp = adh & MMU_FAULT_AD_H_DP;
274 va = MK32(adh & MMU_FAULT_AD_H_ADR_MASK, adl);
276 /* if the fault is masked, nothing to do */
277 if ((status & MMUFAULT_MASK) == 0) {
278 pr_debug( "MMU interrupt, but ignoring.\n");
281 * when CACHE + DMA domain gets out of idle in DSP,
282 * MMU interrupt occurs but MMU_FAULT_ST is not set.
283 * in this case, we just ignore the interrupt.
286 pr_debug( "%s%s%s%s\n",
287 (status & MMU_FAULT_ST_PREF)?
288 " (prefetch err)" : "",
289 (status & MMU_FAULT_ST_PERM)?
290 " (permission fault)" : "",
291 (status & MMU_FAULT_ST_TLB_MISS)?
293 (status & MMU_FAULT_ST_TRANS) ?
294 " (translation fault)": "");
295 pr_debug( "fault address = %#08x\n", va);
297 enable_irq(mmu->irq);
301 pr_info("%s%s%s%s\n",
302 (status & MMU_FAULT_ST_PREF)?
303 (MMUFAULT_MASK & MMU_FAULT_ST_PREF)?
307 (status & MMU_FAULT_ST_PERM)?
308 (MMUFAULT_MASK & MMU_FAULT_ST_PERM)?
310 " (permission fault)":
312 (status & MMU_FAULT_ST_TLB_MISS)?
313 (MMUFAULT_MASK & MMU_FAULT_ST_TLB_MISS)?
317 (status & MMU_FAULT_ST_TRANS)?
318 (MMUFAULT_MASK & MMU_FAULT_ST_TRANS)?
319 " translation fault":
320 " (translation fault)":
322 pr_info("fault address = %#08x\n", va);
324 mmu->fault_address = va;
325 schedule_work(&mmu->irq_work);
328 struct omap_mmu_ops omap1_mmu_ops = {
329 .startup = omap1_mmu_startup,
330 .shutdown = omap1_mmu_shutdown,
331 .mem_enable = omap1_mmu_mem_enable,
332 .mem_disable = omap1_mmu_mem_disable,
333 .read_tlb = omap1_mmu_read_tlb,
334 .load_tlb = omap1_mmu_load_tlb,
335 .show = omap1_mmu_show,
336 .cam_va = omap1_mmu_cam_va,
337 .cam_ram_alloc = omap1_mmu_cam_ram_alloc,
338 .cam_ram_valid = omap1_mmu_cam_ram_valid,
339 .interrupt = omap1_mmu_interrupt,
341 EXPORT_SYMBOL_GPL(omap1_mmu_ops);