arch/arm/mach-omap1/clock.h

   1 /*
   2  *  linux/arch/arm/mach-omap1/clock.h
   3  *
   4  *  Copyright (C) 2004 - 2005 Nokia corporation
   5  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
  14 #define __ARCH_ARM_MACH_OMAP1_CLOCK_H
  15
  16 static void omap1_ckctl_recalc(struct clk * clk);
  17 static void omap1_watchdog_recalc(struct clk * clk);
  18 static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
  19 static void omap1_sossi_recalc(struct clk *clk);
  20 static void omap1_ckctl_recalc_dsp_domain(struct clk * clk);
  21 static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate);
  22 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate);
  23 static void omap1_uart_recalc(struct clk * clk);
  24 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate);
  25 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate);
  26 static void omap1_init_ext_clk(struct clk * clk);
  27 static int omap1_select_table_rate(struct clk * clk, unsigned long rate);
  28 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate);
  29
  30 struct mpu_rate {
  31         unsigned long           rate;
  32         unsigned long           xtal;
  33         unsigned long           pll_rate;
  34         __u16                   ckctl_val;
  35         __u16                   dpllctl_val;
  36 };
  37
  38 struct uart_clk {
  39         struct clk      clk;
  40         unsigned long   sysc_addr;
  41 };
  42
  43 /* Provide a method for preventing idling some ARM IDLECT clocks */
  44 struct arm_idlect1_clk {
  45         struct clk      clk;
  46         unsigned long   no_idle_count;
  47         __u8            idlect_shift;
  48 };
  49
  50 /* ARM_CKCTL bit shifts */
  51 #define CKCTL_PERDIV_OFFSET     0
  52 #define CKCTL_LCDDIV_OFFSET     2
  53 #define CKCTL_ARMDIV_OFFSET     4
  54 #define CKCTL_DSPDIV_OFFSET     6
  55 #define CKCTL_TCDIV_OFFSET      8
  56 #define CKCTL_DSPMMUDIV_OFFSET  10
  57 /*#define ARM_TIMXO             12*/
  58 #define EN_DSPCK                13
  59 /*#define ARM_INTHCK_SEL        14*/ /* Divide-by-2 for mpu inth_ck */
  60 /* DSP_CKCTL bit shifts */
  61 #define CKCTL_DSPPERDIV_OFFSET  0
  62
  63 /* ARM_IDLECT2 bit shifts */
  64 #define EN_WDTCK        0
  65 #define EN_XORPCK       1
  66 #define EN_PERCK        2
  67 #define EN_LCDCK        3
  68 #define EN_LBCK         4 /* Not on 1610/1710 */
  69 /*#define EN_HSABCK     5*/
  70 #define EN_APICK        6
  71 #define EN_TIMCK        7
  72 #define DMACK_REQ       8
  73 #define EN_GPIOCK       9 /* Not on 1610/1710 */
  74 /*#define EN_LBFREECK   10*/
  75 #define EN_CKOUT_ARM    11
  76
  77 /* ARM_IDLECT3 bit shifts */
  78 #define EN_OCPI_CK      0
  79 #define EN_TC1_CK       2
  80 #define EN_TC2_CK       4
  81
  82 /* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */
  83 #define EN_DSPTIMCK     5
  84
  85 /* Various register defines for clock controls scattered around OMAP chip */
  86 #define SDW_MCLK_INV_BIT        2       /* In ULPD_CLKC_CTRL */
  87 #define USB_MCLK_EN_BIT         4       /* In ULPD_CLKC_CTRL */
  88 #define USB_HOST_HHC_UHOST_EN   9       /* In MOD_CONF_CTRL_0 */
  89 #define SWD_ULPD_PLL_CLK_REQ    1       /* In SWD_CLK_DIV_CTRL_SEL */
  90 #define COM_ULPD_PLL_CLK_REQ    1       /* In COM_CLK_DIV_CTRL_SEL */
  91 #define SWD_CLK_DIV_CTRL_SEL    0xfffe0874
  92 #define COM_CLK_DIV_CTRL_SEL    0xfffe0878
  93 #define SOFT_REQ_REG            0xfffe0834
  94 #define SOFT_REQ_REG2           0xfffe0880
  95
  96 /*-------------------------------------------------------------------------
  97  * Omap1 MPU rate table
  98  *-------------------------------------------------------------------------*/
  99 static struct mpu_rate rate_table[] = {
 100         /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
 101          * NOTE: Comment order here is different from bits in CKCTL value:
 102          * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
 103          */
 104 #if defined(CONFIG_OMAP_ARM_216MHZ)
 105         { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
 106 #endif
 107 #if defined(CONFIG_OMAP_ARM_195MHZ)
 108         { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
 109 #endif
 110 #if defined(CONFIG_OMAP_ARM_192MHZ)
 111         { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
 112         { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
 113         {  96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
 114         {  48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
 115         {  24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
 116 #endif
 117 #if defined(CONFIG_OMAP_ARM_182MHZ)
 118         { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
 119 #endif
 120 #if defined(CONFIG_OMAP_ARM_168MHZ)
 121         { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
 122 #endif
 123 #if defined(CONFIG_OMAP_ARM_150MHZ)
 124         { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
 125 #endif
 126 #if defined(CONFIG_OMAP_ARM_120MHZ)
 127         { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
 128 #endif
 129 #if defined(CONFIG_OMAP_ARM_96MHZ)
 130         {  96000000, 12000000,  96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
 131 #endif
 132 #if defined(CONFIG_OMAP_ARM_60MHZ)
 133         {  60000000, 12000000,  60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
 134 #endif
 135 #if defined(CONFIG_OMAP_ARM_30MHZ)
 136         {  30000000, 12000000,  60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
 137 #endif
 138         { 0, 0, 0, 0, 0 },
 139 };
 140
 141 /*-------------------------------------------------------------------------
 142  * Omap1 clocks
 143  *-------------------------------------------------------------------------*/
 144
 145 static struct clk ck_ref = {
 146         .name           = "ck_ref",
 147         .ops            = &clkops_generic,
 148         .rate           = 12000000,
 149         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 150                           CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
 151 };
 152
 153 static struct clk ck_dpll1 = {
 154         .name           = "ck_dpll1",
 155         .ops            = &clkops_generic,
 156         .parent         = &ck_ref,
 157         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 158                           CLOCK_IN_OMAP310 | RATE_PROPAGATES | ALWAYS_ENABLED,
 159 };
 160
 161 static struct arm_idlect1_clk ck_dpll1out = {
 162         .clk = {
 163                 .name           = "ck_dpll1out",
 164                 .ops            = &clkops_generic,
 165                 .parent         = &ck_dpll1,
 166                 .flags          = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL |
 167                                   ENABLE_REG_32BIT | RATE_PROPAGATES,
 168                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 169                 .enable_bit     = EN_CKOUT_ARM,
 170                 .recalc         = &followparent_recalc,
 171         },
 172         .idlect_shift   = 12,
 173 };
 174
 175 static struct clk sossi_ck = {
 176         .name           = "ck_sossi",
 177         .ops            = &clkops_generic,
 178         .parent         = &ck_dpll1out.clk,
 179         .flags          = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT |
 180                           ENABLE_REG_32BIT,
 181         .enable_reg     = (void __iomem *)MOD_CONF_CTRL_1,
 182         .enable_bit     = 16,
 183         .recalc         = &omap1_sossi_recalc,
 184         .set_rate       = &omap1_set_sossi_rate,
 185 };
 186
 187 static struct clk arm_ck = {
 188         .name           = "arm_ck",
 189         .ops            = &clkops_generic,
 190         .parent         = &ck_dpll1,
 191         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 192                           CLOCK_IN_OMAP310 | RATE_CKCTL | RATE_PROPAGATES |
 193                           ALWAYS_ENABLED,
 194         .rate_offset    = CKCTL_ARMDIV_OFFSET,
 195         .recalc         = &omap1_ckctl_recalc,
 196 };
 197
 198 static struct arm_idlect1_clk armper_ck = {
 199         .clk = {
 200                 .name           = "armper_ck",
 201                 .ops            = &clkops_generic,
 202                 .parent         = &ck_dpll1,
 203                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 204                                   CLOCK_IN_OMAP310 | RATE_CKCTL |
 205                                   CLOCK_IDLE_CONTROL,
 206                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 207                 .enable_bit     = EN_PERCK,
 208                 .rate_offset    = CKCTL_PERDIV_OFFSET,
 209                 .recalc         = &omap1_ckctl_recalc,
 210         },
 211         .idlect_shift   = 2,
 212 };
 213
 214 static struct clk arm_gpio_ck = {
 215         .name           = "arm_gpio_ck",
 216         .ops            = &clkops_generic,
 217         .parent         = &ck_dpll1,
 218         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
 219         .enable_reg     = (void __iomem *)ARM_IDLECT2,
 220         .enable_bit     = EN_GPIOCK,
 221         .recalc         = &followparent_recalc,
 222 };
 223
 224 static struct arm_idlect1_clk armxor_ck = {
 225         .clk = {
 226                 .name           = "armxor_ck",
 227                 .ops            = &clkops_generic,
 228                 .parent         = &ck_ref,
 229                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 230                                   CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
 231                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 232                 .enable_bit     = EN_XORPCK,
 233                 .recalc         = &followparent_recalc,
 234         },
 235         .idlect_shift   = 1,
 236 };
 237
 238 static struct arm_idlect1_clk armtim_ck = {
 239         .clk = {
 240                 .name           = "armtim_ck",
 241                 .ops            = &clkops_generic,
 242                 .parent         = &ck_ref,
 243                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 244                                   CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
 245                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 246                 .enable_bit     = EN_TIMCK,
 247                 .recalc         = &followparent_recalc,
 248         },
 249         .idlect_shift   = 9,
 250 };
 251
 252 static struct arm_idlect1_clk armwdt_ck = {
 253         .clk = {
 254                 .name           = "armwdt_ck",
 255                 .ops            = &clkops_generic,
 256                 .parent         = &ck_ref,
 257                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 258                                   CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
 259                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 260                 .enable_bit     = EN_WDTCK,
 261                 .recalc         = &omap1_watchdog_recalc,
 262         },
 263         .idlect_shift   = 0,
 264 };
 265
 266 static struct clk arminth_ck16xx = {
 267         .name           = "arminth_ck",
 268         .ops            = &clkops_generic,
 269         .parent         = &arm_ck,
 270         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 271         .recalc         = &followparent_recalc,
 272         /* Note: On 16xx the frequency can be divided by 2 by programming
 273          * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
 274          *
 275          * 1510 version is in TC clocks.
 276          */
 277 };
 278
 279 static struct clk dsp_ck = {
 280         .name           = "dsp_ck",
 281         .ops            = &clkops_generic,
 282         .parent         = &ck_dpll1,
 283         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 284                           RATE_CKCTL,
 285         .enable_reg     = (void __iomem *)ARM_CKCTL,
 286         .enable_bit     = EN_DSPCK,
 287         .rate_offset    = CKCTL_DSPDIV_OFFSET,
 288         .recalc         = &omap1_ckctl_recalc,
 289 };
 290
 291 static struct clk dspmmu_ck = {
 292         .name           = "dspmmu_ck",
 293         .ops            = &clkops_generic,
 294         .parent         = &ck_dpll1,
 295         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 296                           RATE_CKCTL | ALWAYS_ENABLED,
 297         .rate_offset    = CKCTL_DSPMMUDIV_OFFSET,
 298         .recalc         = &omap1_ckctl_recalc,
 299 };
 300
 301 static struct clk dspper_ck = {
 302         .name           = "dspper_ck",
 303         .ops            = &clkops_dspck,
 304         .parent         = &ck_dpll1,
 305         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 306                           RATE_CKCTL | VIRTUAL_IO_ADDRESS,
 307         .enable_reg     = DSP_IDLECT2,
 308         .enable_bit     = EN_PERCK,
 309         .rate_offset    = CKCTL_PERDIV_OFFSET,
 310         .recalc         = &omap1_ckctl_recalc_dsp_domain,
 311         .set_rate       = &omap1_clk_set_rate_dsp_domain,
 312 };
 313
 314 static struct clk dspxor_ck = {
 315         .name           = "dspxor_ck",
 316         .ops            = &clkops_dspck,
 317         .parent         = &ck_ref,
 318         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 319                           VIRTUAL_IO_ADDRESS,
 320         .enable_reg     = DSP_IDLECT2,
 321         .enable_bit     = EN_XORPCK,
 322         .recalc         = &followparent_recalc,
 323 };
 324
 325 static struct clk dsptim_ck = {
 326         .name           = "dsptim_ck",
 327         .ops            = &clkops_dspck,
 328         .parent         = &ck_ref,
 329         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 330                           VIRTUAL_IO_ADDRESS,
 331         .enable_reg     = DSP_IDLECT2,
 332         .enable_bit     = EN_DSPTIMCK,
 333         .recalc         = &followparent_recalc,
 334 };
 335
 336 /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
 337 static struct arm_idlect1_clk tc_ck = {
 338         .clk = {
 339                 .name           = "tc_ck",
 340                 .ops            = &clkops_generic,
 341                 .parent         = &ck_dpll1,
 342                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 343                                   CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 |
 344                                   RATE_CKCTL | RATE_PROPAGATES |
 345                                   ALWAYS_ENABLED | CLOCK_IDLE_CONTROL,
 346                 .rate_offset    = CKCTL_TCDIV_OFFSET,
 347                 .recalc         = &omap1_ckctl_recalc,
 348         },
 349         .idlect_shift   = 6,
 350 };
 351
 352 static struct clk arminth_ck1510 = {
 353         .name           = "arminth_ck",
 354         .ops            = &clkops_generic,
 355         .parent         = &tc_ck.clk,
 356         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 357                           ALWAYS_ENABLED,
 358         .recalc         = &followparent_recalc,
 359         /* Note: On 1510 the frequency follows TC_CK
 360          *
 361          * 16xx version is in MPU clocks.
 362          */
 363 };
 364
 365 static struct clk tipb_ck = {
 366         /* No-idle controlled by "tc_ck" */
 367         .name           = "tipb_ck",
 368         .ops            = &clkops_generic,
 369         .parent         = &tc_ck.clk,
 370         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 371                           ALWAYS_ENABLED,
 372         .recalc         = &followparent_recalc,
 373 };
 374
 375 static struct clk l3_ocpi_ck = {
 376         /* No-idle controlled by "tc_ck" */
 377         .name           = "l3_ocpi_ck",
 378         .ops            = &clkops_generic,
 379         .parent         = &tc_ck.clk,
 380         .flags          = CLOCK_IN_OMAP16XX,
 381         .enable_reg     = (void __iomem *)ARM_IDLECT3,
 382         .enable_bit     = EN_OCPI_CK,
 383         .recalc         = &followparent_recalc,
 384 };
 385
 386 static struct clk tc1_ck = {
 387         .name           = "tc1_ck",
 388         .ops            = &clkops_generic,
 389         .parent         = &tc_ck.clk,
 390         .flags          = CLOCK_IN_OMAP16XX,
 391         .enable_reg     = (void __iomem *)ARM_IDLECT3,
 392         .enable_bit     = EN_TC1_CK,
 393         .recalc         = &followparent_recalc,
 394 };
 395
 396 static struct clk tc2_ck = {
 397         .name           = "tc2_ck",
 398         .ops            = &clkops_generic,
 399         .parent         = &tc_ck.clk,
 400         .flags          = CLOCK_IN_OMAP16XX,
 401         .enable_reg     = (void __iomem *)ARM_IDLECT3,
 402         .enable_bit     = EN_TC2_CK,
 403         .recalc         = &followparent_recalc,
 404 };
 405
 406 static struct clk dma_ck = {
 407         /* No-idle controlled by "tc_ck" */
 408         .name           = "dma_ck",
 409         .ops            = &clkops_generic,
 410         .parent         = &tc_ck.clk,
 411         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 412                           CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
 413         .recalc         = &followparent_recalc,
 414 };
 415
 416 static struct clk dma_lcdfree_ck = {
 417         .name           = "dma_lcdfree_ck",
 418         .ops            = &clkops_generic,
 419         .parent         = &tc_ck.clk,
 420         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 421         .recalc         = &followparent_recalc,
 422 };
 423
 424 static struct arm_idlect1_clk api_ck = {
 425         .clk = {
 426                 .name           = "api_ck",
 427                 .ops            = &clkops_generic,
 428                 .parent         = &tc_ck.clk,
 429                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 430                                   CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
 431                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 432                 .enable_bit     = EN_APICK,
 433                 .recalc         = &followparent_recalc,
 434         },
 435         .idlect_shift   = 8,
 436 };
 437
 438 static struct arm_idlect1_clk lb_ck = {
 439         .clk = {
 440                 .name           = "lb_ck",
 441                 .ops            = &clkops_generic,
 442                 .parent         = &tc_ck.clk,
 443                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 444                                   CLOCK_IDLE_CONTROL,
 445                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 446                 .enable_bit     = EN_LBCK,
 447                 .recalc         = &followparent_recalc,
 448         },
 449         .idlect_shift   = 4,
 450 };
 451
 452 static struct clk rhea1_ck = {
 453         .name           = "rhea1_ck",
 454         .ops            = &clkops_generic,
 455         .parent         = &tc_ck.clk,
 456         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 457         .recalc         = &followparent_recalc,
 458 };
 459
 460 static struct clk rhea2_ck = {
 461         .name           = "rhea2_ck",
 462         .ops            = &clkops_generic,
 463         .parent         = &tc_ck.clk,
 464         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 465         .recalc         = &followparent_recalc,
 466 };
 467
 468 static struct clk lcd_ck_16xx = {
 469         .name           = "lcd_ck",
 470         .ops            = &clkops_generic,
 471         .parent         = &ck_dpll1,
 472         .flags          = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 | RATE_CKCTL,
 473         .enable_reg     = (void __iomem *)ARM_IDLECT2,
 474         .enable_bit     = EN_LCDCK,
 475         .rate_offset    = CKCTL_LCDDIV_OFFSET,
 476         .recalc         = &omap1_ckctl_recalc,
 477 };
 478
 479 static struct arm_idlect1_clk lcd_ck_1510 = {
 480         .clk = {
 481                 .name           = "lcd_ck",
 482                 .ops            = &clkops_generic,
 483                 .parent         = &ck_dpll1,
 484                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 485                                   RATE_CKCTL | CLOCK_IDLE_CONTROL,
 486                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 487                 .enable_bit     = EN_LCDCK,
 488                 .rate_offset    = CKCTL_LCDDIV_OFFSET,
 489                 .recalc         = &omap1_ckctl_recalc,
 490         },
 491         .idlect_shift   = 3,
 492 };
 493
 494 static struct clk uart1_1510 = {
 495         .name           = "uart1_ck",
 496         .ops            = &clkops_generic,
 497         /* Direct from ULPD, no real parent */
 498         .parent         = &armper_ck.clk,
 499         .rate           = 12000000,
 500         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 501                           ENABLE_REG_32BIT | ALWAYS_ENABLED |
 502                           CLOCK_NO_IDLE_PARENT,
 503         .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 504         .enable_bit     = 29,   /* Chooses between 12MHz and 48MHz */
 505         .set_rate       = &omap1_set_uart_rate,
 506         .recalc         = &omap1_uart_recalc,
 507 };
 508
 509 static struct uart_clk uart1_16xx = {
 510         .clk    = {
 511                 .name           = "uart1_ck",
 512                 .ops            = &clkops_uart,
 513                 /* Direct from ULPD, no real parent */
 514                 .parent         = &armper_ck.clk,
 515                 .rate           = 48000000,
 516                 .flags          = CLOCK_IN_OMAP16XX | RATE_FIXED |
 517                                   ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 518                 .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 519                 .enable_bit     = 29,
 520         },
 521         .sysc_addr      = 0xfffb0054,
 522 };
 523
 524 static struct clk uart2_ck = {
 525         .name           = "uart2_ck",
 526         .ops            = &clkops_generic,
 527         /* Direct from ULPD, no real parent */
 528         .parent         = &armper_ck.clk,
 529         .rate           = 12000000,
 530         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 531                           CLOCK_IN_OMAP310 | ENABLE_REG_32BIT |
 532                           ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT,
 533         .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 534         .enable_bit     = 30,   /* Chooses between 12MHz and 48MHz */
 535         .set_rate       = &omap1_set_uart_rate,
 536         .recalc         = &omap1_uart_recalc,
 537 };
 538
 539 static struct clk uart3_1510 = {
 540         .name           = "uart3_ck",
 541         .ops            = &clkops_generic,
 542         /* Direct from ULPD, no real parent */
 543         .parent         = &armper_ck.clk,
 544         .rate           = 12000000,
 545         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 546                           ENABLE_REG_32BIT | ALWAYS_ENABLED |
 547                           CLOCK_NO_IDLE_PARENT,
 548         .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 549         .enable_bit     = 31,   /* Chooses between 12MHz and 48MHz */
 550         .set_rate       = &omap1_set_uart_rate,
 551         .recalc         = &omap1_uart_recalc,
 552 };
 553
 554 static struct uart_clk uart3_16xx = {
 555         .clk    = {
 556                 .name           = "uart3_ck",
 557                 .ops            = &clkops_uart,
 558                 /* Direct from ULPD, no real parent */
 559                 .parent         = &armper_ck.clk,
 560                 .rate           = 48000000,
 561                 .flags          = CLOCK_IN_OMAP16XX | RATE_FIXED |
 562                                   ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 563                 .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 564                 .enable_bit     = 31,
 565         },
 566         .sysc_addr      = 0xfffb9854,
 567 };
 568
 569 static struct clk usb_clko = {  /* 6 MHz output on W4_USB_CLKO */
 570         .name           = "usb_clko",
 571         .ops            = &clkops_generic,
 572         /* Direct from ULPD, no parent */
 573         .rate           = 6000000,
 574         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 575                           CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT,
 576         .enable_reg     = (void __iomem *)ULPD_CLOCK_CTRL,
 577         .enable_bit     = USB_MCLK_EN_BIT,
 578 };
 579
 580 static struct clk usb_hhc_ck1510 = {
 581         .name           = "usb_hhc_ck",
 582         .ops            = &clkops_generic,
 583         /* Direct from ULPD, no parent */
 584         .rate           = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
 585         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 586                           RATE_FIXED | ENABLE_REG_32BIT,
 587         .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 588         .enable_bit     = USB_HOST_HHC_UHOST_EN,
 589 };
 590
 591 static struct clk usb_hhc_ck16xx = {
 592         .name           = "usb_hhc_ck",
 593         .ops            = &clkops_generic,
 594         /* Direct from ULPD, no parent */
 595         .rate           = 48000000,
 596         /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
 597         .flags          = CLOCK_IN_OMAP16XX |
 598                           RATE_FIXED | ENABLE_REG_32BIT,
 599         .enable_reg     = (void __iomem *)OTG_BASE + 0x08 /* OTG_SYSCON_2 */,
 600         .enable_bit     = 8 /* UHOST_EN */,
 601 };
 602
 603 static struct clk usb_dc_ck = {
 604         .name           = "usb_dc_ck",
 605         .ops            = &clkops_generic,
 606         /* Direct from ULPD, no parent */
 607         .rate           = 48000000,
 608         .flags          = CLOCK_IN_OMAP16XX | RATE_FIXED,
 609         .enable_reg     = (void __iomem *)SOFT_REQ_REG,
 610         .enable_bit     = 4,
 611 };
 612
 613 static struct clk mclk_1510 = {
 614         .name           = "mclk",
 615         .ops            = &clkops_generic,
 616         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 617         .rate           = 12000000,
 618         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED,
 619         .enable_reg     = (void __iomem *)SOFT_REQ_REG,
 620         .enable_bit     = 6,
 621 };
 622
 623 static struct clk mclk_16xx = {
 624         .name           = "mclk",
 625         .ops            = &clkops_generic,
 626         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 627         .flags          = CLOCK_IN_OMAP16XX,
 628         .enable_reg     = (void __iomem *)COM_CLK_DIV_CTRL_SEL,
 629         .enable_bit     = COM_ULPD_PLL_CLK_REQ,
 630         .set_rate       = &omap1_set_ext_clk_rate,
 631         .round_rate     = &omap1_round_ext_clk_rate,
 632         .init           = &omap1_init_ext_clk,
 633 };
 634
 635 static struct clk bclk_1510 = {
 636         .name           = "bclk",
 637         .ops            = &clkops_generic,
 638         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 639         .rate           = 12000000,
 640         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED,
 641 };
 642
 643 static struct clk bclk_16xx = {
 644         .name           = "bclk",
 645         .ops            = &clkops_generic,
 646         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 647         .flags          = CLOCK_IN_OMAP16XX,
 648         .enable_reg     = (void __iomem *)SWD_CLK_DIV_CTRL_SEL,
 649         .enable_bit     = SWD_ULPD_PLL_CLK_REQ,
 650         .set_rate       = &omap1_set_ext_clk_rate,
 651         .round_rate     = &omap1_round_ext_clk_rate,
 652         .init           = &omap1_init_ext_clk,
 653 };
 654
 655 static struct clk mmc1_ck = {
 656         .name           = "mmc_ck",
 657         .ops            = &clkops_generic,
 658         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 659         .parent         = &armper_ck.clk,
 660         .rate           = 48000000,
 661         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 662                           CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT |
 663                           CLOCK_NO_IDLE_PARENT,
 664         .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 665         .enable_bit     = 23,
 666 };
 667
 668 static struct clk mmc2_ck = {
 669         .name           = "mmc_ck",
 670         .id             = 1,
 671         .ops            = &clkops_generic,
 672         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 673         .parent         = &armper_ck.clk,
 674         .rate           = 48000000,
 675         .flags          = CLOCK_IN_OMAP16XX |
 676                           RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 677         .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 678         .enable_bit     = 20,
 679 };
 680
 681 static struct clk virtual_ck_mpu = {
 682         .name           = "mpu",
 683         .ops            = &clkops_generic,
 684         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 685                           CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
 686         .parent         = &arm_ck, /* Is smarter alias for */
 687         .recalc         = &followparent_recalc,
 688         .set_rate       = &omap1_select_table_rate,
 689         .round_rate     = &omap1_round_to_table_rate,
 690 };
 691
 692 /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
 693 remains active during MPU idle whenever this is enabled */
 694 static struct clk i2c_fck = {
 695         .name           = "i2c_fck",
 696         .id             = 1,
 697         .ops            = &clkops_generic,
 698         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 699                           CLOCK_NO_IDLE_PARENT | ALWAYS_ENABLED,
 700         .parent         = &armxor_ck.clk,
 701         .recalc         = &followparent_recalc,
 702 };
 703
 704 static struct clk i2c_ick = {
 705         .name           = "i2c_ick",
 706         .id             = 1,
 707         .ops            = &clkops_generic,
 708         .flags          = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT |
 709                           ALWAYS_ENABLED,
 710         .parent         = &armper_ck.clk,
 711         .recalc         = &followparent_recalc,
 712 };
 713
 714 static struct clk * onchip_clks[] = {
 715         /* non-ULPD clocks */
 716         &ck_ref,
 717         &ck_dpll1,
 718         /* CK_GEN1 clocks */
 719         &ck_dpll1out.clk,
 720         &sossi_ck,
 721         &arm_ck,
 722         &armper_ck.clk,
 723         &arm_gpio_ck,
 724         &armxor_ck.clk,
 725         &armtim_ck.clk,
 726         &armwdt_ck.clk,
 727         &arminth_ck1510,  &arminth_ck16xx,
 728         /* CK_GEN2 clocks */
 729         &dsp_ck,
 730         &dspmmu_ck,
 731         &dspper_ck,
 732         &dspxor_ck,
 733         &dsptim_ck,
 734         /* CK_GEN3 clocks */
 735         &tc_ck.clk,
 736         &tipb_ck,
 737         &l3_ocpi_ck,
 738         &tc1_ck,
 739         &tc2_ck,
 740         &dma_ck,
 741         &dma_lcdfree_ck,
 742         &api_ck.clk,
 743         &lb_ck.clk,
 744         &rhea1_ck,
 745         &rhea2_ck,
 746         &lcd_ck_16xx,
 747         &lcd_ck_1510.clk,
 748         /* ULPD clocks */
 749         &uart1_1510,
 750         &uart1_16xx.clk,
 751         &uart2_ck,
 752         &uart3_1510,
 753         &uart3_16xx.clk,
 754         &usb_clko,
 755         &usb_hhc_ck1510, &usb_hhc_ck16xx,
 756         &usb_dc_ck,
 757         &mclk_1510,  &mclk_16xx,
 758         &bclk_1510,  &bclk_16xx,
 759         &mmc1_ck,
 760         &mmc2_ck,
 761         /* Virtual clocks */
 762         &virtual_ck_mpu,
 763         &i2c_fck,
 764         &i2c_ick,
 765 };
 766
 767 #endif