arch/arm/mach-omap1/clock.c

   1 /*
   2  *  linux/arch/arm/mach-omap1/clock.c
   3  *
   4  *  Copyright (C) 2004 - 2005 Nokia corporation
   5  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  *
   7  *  Modified to use omap shared clock framework by
   8  *  Tony Lindgren <tony@atomide.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/io.h>
  21
  22 #include <asm/mach-types.h>
  23 #include <asm/clkdev.h>
  24
  25 #include <mach/cpu.h>
  26 #include <mach/usb.h>
  27 #include <mach/clock.h>
  28 #include <mach/sram.h>
  29
  30 static const struct clkops clkops_generic;
  31 static const struct clkops clkops_uart;
  32 static const struct clkops clkops_dspck;
  33
  34 #include "clock.h"
  35
  36 static int clk_omap1_dummy_enable(struct clk *clk)
  37 {
  38         return 0;
  39 }
  40
  41 static void clk_omap1_dummy_disable(struct clk *clk)
  42 {
  43 }
  44
  45 static const struct clkops clkops_dummy = {
  46         .enable = clk_omap1_dummy_enable,
  47         .disable = clk_omap1_dummy_disable,
  48 };
  49
  50 static struct clk dummy_ck = {
  51         .name   = "dummy",
  52         .ops    = &clkops_dummy,
  53         .flags  = RATE_FIXED,
  54 };
  55
  56 struct omap_clk {
  57         u32             cpu;
  58         struct clk_lookup lk;
  59 };
  60
  61 #define CLK(dev, con, ck, cp)           \
  62         {                               \
  63                  .cpu = cp,             \
  64                 .lk = {                 \
  65                         .dev_id = dev,  \
  66                         .con_id = con,  \
  67                         .clk = ck,      \
  68                 },                      \
  69         }
  70
  71 #define CK_310  (1 << 0)
  72 #define CK_730  (1 << 1)
  73 #define CK_1510 (1 << 2)
  74 #define CK_16XX (1 << 3)
  75
  76 static struct omap_clk omap_clks[] = {
  77         /* non-ULPD clocks */
  78         CLK(NULL,       "ck_ref",       &ck_ref,        CK_16XX | CK_1510 | CK_310),
  79         CLK(NULL,       "ck_dpll1",     &ck_dpll1,      CK_16XX | CK_1510 | CK_310),
  80         /* CK_GEN1 clocks */
  81         CLK(NULL,       "ck_dpll1out",  &ck_dpll1out.clk, CK_16XX),
  82         CLK(NULL,       "ck_sossi",     &sossi_ck,      CK_16XX),
  83         CLK(NULL,       "arm_ck",       &arm_ck,        CK_16XX | CK_1510 | CK_310),
  84         CLK(NULL,       "armper_ck",    &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
  85         CLK(NULL,       "arm_gpio_ck",  &arm_gpio_ck,   CK_1510 | CK_310),
  86         CLK(NULL,       "armxor_ck",    &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
  87         CLK(NULL,       "armtim_ck",    &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
  88         CLK("omap_wdt", "fck",          &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
  89         CLK("omap_wdt", "ick",          &armper_ck.clk, CK_16XX),
  90         CLK("omap_wdt", "ick",          &dummy_ck,      CK_1510 | CK_310),
  91         CLK(NULL,       "arminth_ck",   &arminth_ck1510, CK_1510 | CK_310),
  92         CLK(NULL,       "arminth_ck",   &arminth_ck16xx, CK_16XX),
  93         /* CK_GEN2 clocks */
  94         CLK(NULL,       "dsp_ck",       &dsp_ck,        CK_16XX | CK_1510 | CK_310),
  95         CLK(NULL,       "dspmmu_ck",    &dspmmu_ck,     CK_16XX | CK_1510 | CK_310),
  96         CLK(NULL,       "dspper_ck",    &dspper_ck,     CK_16XX | CK_1510 | CK_310),
  97         CLK(NULL,       "dspxor_ck",    &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
  98         CLK(NULL,       "dsptim_ck",    &dsptim_ck,     CK_16XX | CK_1510 | CK_310),
  99         /* CK_GEN3 clocks */
 100         CLK(NULL,       "tc_ck",        &tc_ck.clk,     CK_16XX | CK_1510 | CK_310 | CK_730),
 101         CLK(NULL,       "tipb_ck",      &tipb_ck,       CK_1510 | CK_310),
 102         CLK(NULL,       "l3_ocpi_ck",   &l3_ocpi_ck,    CK_16XX),
 103         CLK(NULL,       "tc1_ck",       &tc1_ck,        CK_16XX),
 104         CLK(NULL,       "tc2_ck",       &tc2_ck,        CK_16XX),
 105         CLK(NULL,       "dma_ck",       &dma_ck,        CK_16XX | CK_1510 | CK_310),
 106         CLK(NULL,       "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
 107         CLK(NULL,       "api_ck",       &api_ck.clk,    CK_16XX | CK_1510 | CK_310),
 108         CLK(NULL,       "lb_ck",        &lb_ck.clk,     CK_1510 | CK_310),
 109         CLK(NULL,       "rhea1_ck",     &rhea1_ck,      CK_16XX),
 110         CLK(NULL,       "rhea2_ck",     &rhea2_ck,      CK_16XX),
 111         CLK(NULL,       "lcd_ck",       &lcd_ck_16xx,   CK_16XX | CK_730),
 112         CLK(NULL,       "lcd_ck",       &lcd_ck_1510.clk, CK_1510 | CK_310),
 113         /* ULPD clocks */
 114         CLK(NULL,       "uart1_ck",     &uart1_1510,    CK_1510 | CK_310),
 115         CLK(NULL,       "uart1_ck",     &uart1_16xx.clk, CK_16XX),
 116         CLK(NULL,       "uart2_ck",     &uart2_ck,      CK_16XX | CK_1510 | CK_310),
 117         CLK(NULL,       "uart3_ck",     &uart3_1510,    CK_1510 | CK_310),
 118         CLK(NULL,       "uart3_ck",     &uart3_16xx.clk, CK_16XX),
 119         CLK(NULL,       "usb_clko",     &usb_clko,      CK_16XX | CK_1510 | CK_310),
 120         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck1510, CK_1510 | CK_310),
 121         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck16xx, CK_16XX),
 122         CLK(NULL,       "usb_dc_ck",    &usb_dc_ck,     CK_16XX),
 123         CLK(NULL,       "mclk",         &mclk_1510,     CK_1510 | CK_310),
 124         CLK(NULL,       "mclk",         &mclk_16xx,     CK_16XX),
 125         CLK(NULL,       "bclk",         &bclk_1510,     CK_1510 | CK_310),
 126         CLK(NULL,       "bclk",         &bclk_16xx,     CK_16XX),
 127         CLK("mmci-omap.0", "fck",       &mmc1_ck,       CK_16XX | CK_1510 | CK_310),
 128         CLK("mmci-omap.1", "fck",       &mmc2_ck,       CK_16XX),
 129         /* Virtual clocks */
 130         CLK(NULL,       "mpu",          &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
 131         CLK("i2c_omap.1", "i2c_fck",    &i2c_fck,       CK_16XX | CK_1510 | CK_310),
 132         CLK("i2c_omap.1", "i2c_ick",    &i2c_ick,       CK_16XX),
 133 };
 134
 135 static int omap1_clk_enable_generic(struct clk * clk);
 136 static int omap1_clk_enable(struct clk *clk);
 137 static void omap1_clk_disable_generic(struct clk * clk);
 138 static void omap1_clk_disable(struct clk *clk);
 139
 140 __u32 arm_idlect1_mask;
 141
 142 /*-------------------------------------------------------------------------
 143  * Omap1 specific clock functions
 144  *-------------------------------------------------------------------------*/
 145
 146 static void omap1_watchdog_recalc(struct clk * clk)
 147 {
 148         clk->rate = clk->parent->rate / 14;
 149 }
 150
 151 static void omap1_uart_recalc(struct clk * clk)
 152 {
 153         unsigned int val = omap_readl(clk->enable_reg);
 154         if (val & clk->enable_bit)
 155                 clk->rate = 48000000;
 156         else
 157                 clk->rate = 12000000;
 158 }
 159
 160 static void omap1_sossi_recalc(struct clk *clk)
 161 {
 162         u32 div = omap_readl(MOD_CONF_CTRL_1);
 163
 164         div = (div >> 17) & 0x7;
 165         div++;
 166         clk->rate = clk->parent->rate / div;
 167 }
 168
 169 static int omap1_clk_enable_dsp_domain(struct clk *clk)
 170 {
 171         int retval;
 172
 173         retval = omap1_clk_enable(&api_ck.clk);
 174         if (!retval) {
 175                 retval = omap1_clk_enable_generic(clk);
 176                 omap1_clk_disable(&api_ck.clk);
 177         }
 178
 179         return retval;
 180 }
 181
 182 static void omap1_clk_disable_dsp_domain(struct clk *clk)
 183 {
 184         if (omap1_clk_enable(&api_ck.clk) == 0) {
 185                 omap1_clk_disable_generic(clk);
 186                 omap1_clk_disable(&api_ck.clk);
 187         }
 188 }
 189
 190 static const struct clkops clkops_dspck = {
 191         .enable         = &omap1_clk_enable_dsp_domain,
 192         .disable        = &omap1_clk_disable_dsp_domain,
 193 };
 194
 195 static int omap1_clk_enable_uart_functional(struct clk *clk)
 196 {
 197         int ret;
 198         struct uart_clk *uclk;
 199
 200         ret = omap1_clk_enable_generic(clk);
 201         if (ret == 0) {
 202                 /* Set smart idle acknowledgement mode */
 203                 uclk = (struct uart_clk *)clk;
 204                 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
 205                             uclk->sysc_addr);
 206         }
 207
 208         return ret;
 209 }
 210
 211 static void omap1_clk_disable_uart_functional(struct clk *clk)
 212 {
 213         struct uart_clk *uclk;
 214
 215         /* Set force idle acknowledgement mode */
 216         uclk = (struct uart_clk *)clk;
 217         omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
 218
 219         omap1_clk_disable_generic(clk);
 220 }
 221
 222 static const struct clkops clkops_uart = {
 223         .enable         = &omap1_clk_enable_uart_functional,
 224         .disable        = &omap1_clk_disable_uart_functional,
 225 };
 226
 227 static void omap1_clk_allow_idle(struct clk *clk)
 228 {
 229         struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
 230
 231         if (!(clk->flags & CLOCK_IDLE_CONTROL))
 232                 return;
 233
 234         if (iclk->no_idle_count > 0 && !(--iclk->no_idle_count))
 235                 arm_idlect1_mask |= 1 << iclk->idlect_shift;
 236 }
 237
 238 static void omap1_clk_deny_idle(struct clk *clk)
 239 {
 240         struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
 241
 242         if (!(clk->flags & CLOCK_IDLE_CONTROL))
 243                 return;
 244
 245         if (iclk->no_idle_count++ == 0)
 246                 arm_idlect1_mask &= ~(1 << iclk->idlect_shift);
 247 }
 248
 249 static __u16 verify_ckctl_value(__u16 newval)
 250 {
 251         /* This function checks for following limitations set
 252          * by the hardware (all conditions must be true):
 253          * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
 254          * ARM_CK >= TC_CK
 255          * DSP_CK >= TC_CK
 256          * DSPMMU_CK >= TC_CK
 257          *
 258          * In addition following rules are enforced:
 259          * LCD_CK <= TC_CK
 260          * ARMPER_CK <= TC_CK
 261          *
 262          * However, maximum frequencies are not checked for!
 263          */
 264         __u8 per_exp;
 265         __u8 lcd_exp;
 266         __u8 arm_exp;
 267         __u8 dsp_exp;
 268         __u8 tc_exp;
 269         __u8 dspmmu_exp;
 270
 271         per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
 272         lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
 273         arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
 274         dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
 275         tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
 276         dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
 277
 278         if (dspmmu_exp < dsp_exp)
 279                 dspmmu_exp = dsp_exp;
 280         if (dspmmu_exp > dsp_exp+1)
 281                 dspmmu_exp = dsp_exp+1;
 282         if (tc_exp < arm_exp)
 283                 tc_exp = arm_exp;
 284         if (tc_exp < dspmmu_exp)
 285                 tc_exp = dspmmu_exp;
 286         if (tc_exp > lcd_exp)
 287                 lcd_exp = tc_exp;
 288         if (tc_exp > per_exp)
 289                 per_exp = tc_exp;
 290
 291         newval &= 0xf000;
 292         newval |= per_exp << CKCTL_PERDIV_OFFSET;
 293         newval |= lcd_exp << CKCTL_LCDDIV_OFFSET;
 294         newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
 295         newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
 296         newval |= tc_exp << CKCTL_TCDIV_OFFSET;
 297         newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
 298
 299         return newval;
 300 }
 301
 302 static int calc_dsor_exp(struct clk *clk, unsigned long rate)
 303 {
 304         /* Note: If target frequency is too low, this function will return 4,
 305          * which is invalid value. Caller must check for this value and act
 306          * accordingly.
 307          *
 308          * Note: This function does not check for following limitations set
 309          * by the hardware (all conditions must be true):
 310          * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
 311          * ARM_CK >= TC_CK
 312          * DSP_CK >= TC_CK
 313          * DSPMMU_CK >= TC_CK
 314          */
 315         unsigned long realrate;
 316         struct clk * parent;
 317         unsigned  dsor_exp;
 318
 319         parent = clk->parent;
 320         if (unlikely(parent == NULL))
 321                 return -EIO;
 322
 323         realrate = parent->rate;
 324         for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
 325                 if (realrate <= rate)
 326                         break;
 327
 328                 realrate /= 2;
 329         }
 330
 331         return dsor_exp;
 332 }
 333
 334 static void omap1_ckctl_recalc(struct clk * clk)
 335 {
 336         int dsor;
 337
 338         /* Calculate divisor encoded as 2-bit exponent */
 339         dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
 340
 341         if (unlikely(clk->rate == clk->parent->rate / dsor))
 342                 return; /* No change, quick exit */
 343         clk->rate = clk->parent->rate / dsor;
 344 }
 345
 346 static void omap1_ckctl_recalc_dsp_domain(struct clk * clk)
 347 {
 348         int dsor;
 349
 350         /* Calculate divisor encoded as 2-bit exponent
 351          *
 352          * The clock control bits are in DSP domain,
 353          * so api_ck is needed for access.
 354          * Note that DSP_CKCTL virt addr = phys addr, so
 355          * we must use __raw_readw() instead of omap_readw().
 356          */
 357         omap1_clk_enable(&api_ck.clk);
 358         dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
 359         omap1_clk_disable(&api_ck.clk);
 360
 361         if (unlikely(clk->rate == clk->parent->rate / dsor))
 362                 return; /* No change, quick exit */
 363         clk->rate = clk->parent->rate / dsor;
 364 }
 365
 366 /* MPU virtual clock functions */
 367 static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
 368 {
 369         /* Find the highest supported frequency <= rate and switch to it */
 370         struct mpu_rate * ptr;
 371
 372         if (clk != &virtual_ck_mpu)
 373                 return -EINVAL;
 374
 375         for (ptr = rate_table; ptr->rate; ptr++) {
 376                 if (ptr->xtal != ck_ref.rate)
 377                         continue;
 378
 379                 /* DPLL1 cannot be reprogrammed without risking system crash */
 380                 if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate)
 381                         continue;
 382
 383                 /* Can check only after xtal frequency check */
 384                 if (ptr->rate <= rate)
 385                         break;
 386         }
 387
 388         if (!ptr->rate)
 389                 return -EINVAL;
 390
 391         /*
 392          * In most cases we should not need to reprogram DPLL.
 393          * Reprogramming the DPLL is tricky, it must be done from SRAM.
 394          * (on 730, bit 13 must always be 1)
 395          */
 396         if (cpu_is_omap730())
 397                 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
 398         else
 399                 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
 400
 401         ck_dpll1.rate = ptr->pll_rate;
 402         return 0;
 403 }
 404
 405 static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
 406 {
 407         int dsor_exp;
 408         u16 regval;
 409
 410         dsor_exp = calc_dsor_exp(clk, rate);
 411         if (dsor_exp > 3)
 412                 dsor_exp = -EINVAL;
 413         if (dsor_exp < 0)
 414                 return dsor_exp;
 415
 416         regval = __raw_readw(DSP_CKCTL);
 417         regval &= ~(3 << clk->rate_offset);
 418         regval |= dsor_exp << clk->rate_offset;
 419         __raw_writew(regval, DSP_CKCTL);
 420         clk->rate = clk->parent->rate / (1 << dsor_exp);
 421
 422         return 0;
 423 }
 424
 425 static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
 426 {
 427         int dsor_exp = calc_dsor_exp(clk, rate);
 428         if (dsor_exp < 0)
 429                 return dsor_exp;
 430         if (dsor_exp > 3)
 431                 dsor_exp = 3;
 432         return clk->parent->rate / (1 << dsor_exp);
 433 }
 434
 435 static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
 436 {
 437         int dsor_exp;
 438         u16 regval;
 439
 440         dsor_exp = calc_dsor_exp(clk, rate);
 441         if (dsor_exp > 3)
 442                 dsor_exp = -EINVAL;
 443         if (dsor_exp < 0)
 444                 return dsor_exp;
 445
 446         regval = omap_readw(ARM_CKCTL);
 447         regval &= ~(3 << clk->rate_offset);
 448         regval |= dsor_exp << clk->rate_offset;
 449         regval = verify_ckctl_value(regval);
 450         omap_writew(regval, ARM_CKCTL);
 451         clk->rate = clk->parent->rate / (1 << dsor_exp);
 452         return 0;
 453 }
 454
 455 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate)
 456 {
 457         /* Find the highest supported frequency <= rate */
 458         struct mpu_rate * ptr;
 459         long  highest_rate;
 460
 461         if (clk != &virtual_ck_mpu)
 462                 return -EINVAL;
 463
 464         highest_rate = -EINVAL;
 465
 466         for (ptr = rate_table; ptr->rate; ptr++) {
 467                 if (ptr->xtal != ck_ref.rate)
 468                         continue;
 469
 470                 highest_rate = ptr->rate;
 471
 472                 /* Can check only after xtal frequency check */
 473                 if (ptr->rate <= rate)
 474                         break;
 475         }
 476
 477         return highest_rate;
 478 }
 479
 480 static unsigned calc_ext_dsor(unsigned long rate)
 481 {
 482         unsigned dsor;
 483
 484         /* MCLK and BCLK divisor selection is not linear:
 485          * freq = 96MHz / dsor
 486          *
 487          * RATIO_SEL range: dsor <-> RATIO_SEL
 488          * 0..6: (RATIO_SEL+2) <-> (dsor-2)
 489          * 6..48:  (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
 490          * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
 491          * can not be used.
 492          */
 493         for (dsor = 2; dsor < 96; ++dsor) {
 494                 if ((dsor & 1) && dsor > 8)
 495                         continue;
 496                 if (rate >= 96000000 / dsor)
 497                         break;
 498         }
 499         return dsor;
 500 }
 501
 502 /* Only needed on 1510 */
 503 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate)
 504 {
 505         unsigned int val;
 506
 507         val = omap_readl(clk->enable_reg);
 508         if (rate == 12000000)
 509                 val &= ~(1 << clk->enable_bit);
 510         else if (rate == 48000000)
 511                 val |= (1 << clk->enable_bit);
 512         else
 513                 return -EINVAL;
 514         omap_writel(val, clk->enable_reg);
 515         clk->rate = rate;
 516
 517         return 0;
 518 }
 519
 520 /* External clock (MCLK & BCLK) functions */
 521 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate)
 522 {
 523         unsigned dsor;
 524         __u16 ratio_bits;
 525
 526         dsor = calc_ext_dsor(rate);
 527         clk->rate = 96000000 / dsor;
 528         if (dsor > 8)
 529                 ratio_bits = ((dsor - 8) / 2 + 6) << 2;
 530         else
 531                 ratio_bits = (dsor - 2) << 2;
 532
 533         ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd;
 534         omap_writew(ratio_bits, clk->enable_reg);
 535
 536         return 0;
 537 }
 538
 539 static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
 540 {
 541         u32 l;
 542         int div;
 543         unsigned long p_rate;
 544
 545         p_rate = clk->parent->rate;
 546         /* Round towards slower frequency */
 547         div = (p_rate + rate - 1) / rate;
 548         div--;
 549         if (div < 0 || div > 7)
 550                 return -EINVAL;
 551
 552         l = omap_readl(MOD_CONF_CTRL_1);
 553         l &= ~(7 << 17);
 554         l |= div << 17;
 555         omap_writel(l, MOD_CONF_CTRL_1);
 556
 557         clk->rate = p_rate / (div + 1);
 558
 559         return 0;
 560 }
 561
 562 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate)
 563 {
 564         return 96000000 / calc_ext_dsor(rate);
 565 }
 566
 567 static void omap1_init_ext_clk(struct clk * clk)
 568 {
 569         unsigned dsor;
 570         __u16 ratio_bits;
 571
 572         /* Determine current rate and ensure clock is based on 96MHz APLL */
 573         ratio_bits = omap_readw(clk->enable_reg) & ~1;
 574         omap_writew(ratio_bits, clk->enable_reg);
 575
 576         ratio_bits = (ratio_bits & 0xfc) >> 2;
 577         if (ratio_bits > 6)
 578                 dsor = (ratio_bits - 6) * 2 + 8;
 579         else
 580                 dsor = ratio_bits + 2;
 581
 582         clk-> rate = 96000000 / dsor;
 583 }
 584
 585 static int omap1_clk_enable(struct clk *clk)
 586 {
 587         int ret = 0;
 588         if (clk->usecount++ == 0) {
 589                 if (likely(clk->parent)) {
 590                         ret = omap1_clk_enable(clk->parent);
 591
 592                         if (unlikely(ret != 0)) {
 593                                 clk->usecount--;
 594                                 return ret;
 595                         }
 596
 597                         if (clk->flags & CLOCK_NO_IDLE_PARENT)
 598                                 omap1_clk_deny_idle(clk->parent);
 599                 }
 600
 601                 ret = clk->ops->enable(clk);
 602
 603                 if (unlikely(ret != 0) && clk->parent) {
 604                         omap1_clk_disable(clk->parent);
 605                         clk->usecount--;
 606                 }
 607         }
 608
 609         return ret;
 610 }
 611
 612 static void omap1_clk_disable(struct clk *clk)
 613 {
 614         if (clk->usecount > 0 && !(--clk->usecount)) {
 615                 clk->ops->disable(clk);
 616                 if (likely(clk->parent)) {
 617                         omap1_clk_disable(clk->parent);
 618                         if (clk->flags & CLOCK_NO_IDLE_PARENT)
 619                                 omap1_clk_allow_idle(clk->parent);
 620                 }
 621         }
 622 }
 623
 624 static int omap1_clk_enable_generic(struct clk *clk)
 625 {
 626         __u16 regval16;
 627         __u32 regval32;
 628
 629         if (unlikely(clk->enable_reg == NULL)) {
 630                 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
 631                        clk->name);
 632                 return -EINVAL;
 633         }
 634
 635         if (clk->flags & ENABLE_REG_32BIT) {
 636                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 637                         regval32 = __raw_readl(clk->enable_reg);
 638                         regval32 |= (1 << clk->enable_bit);
 639                         __raw_writel(regval32, clk->enable_reg);
 640                 } else {
 641                         regval32 = omap_readl(clk->enable_reg);
 642                         regval32 |= (1 << clk->enable_bit);
 643                         omap_writel(regval32, clk->enable_reg);
 644                 }
 645         } else {
 646                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 647                         regval16 = __raw_readw(clk->enable_reg);
 648                         regval16 |= (1 << clk->enable_bit);
 649                         __raw_writew(regval16, clk->enable_reg);
 650                 } else {
 651                         regval16 = omap_readw(clk->enable_reg);
 652                         regval16 |= (1 << clk->enable_bit);
 653                         omap_writew(regval16, clk->enable_reg);
 654                 }
 655         }
 656
 657         return 0;
 658 }
 659
 660 static void omap1_clk_disable_generic(struct clk *clk)
 661 {
 662         __u16 regval16;
 663         __u32 regval32;
 664
 665         if (clk->enable_reg == NULL)
 666                 return;
 667
 668         if (clk->flags & ENABLE_REG_32BIT) {
 669                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 670                         regval32 = __raw_readl(clk->enable_reg);
 671                         regval32 &= ~(1 << clk->enable_bit);
 672                         __raw_writel(regval32, clk->enable_reg);
 673                 } else {
 674                         regval32 = omap_readl(clk->enable_reg);
 675                         regval32 &= ~(1 << clk->enable_bit);
 676                         omap_writel(regval32, clk->enable_reg);
 677                 }
 678         } else {
 679                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 680                         regval16 = __raw_readw(clk->enable_reg);
 681                         regval16 &= ~(1 << clk->enable_bit);
 682                         __raw_writew(regval16, clk->enable_reg);
 683                 } else {
 684                         regval16 = omap_readw(clk->enable_reg);
 685                         regval16 &= ~(1 << clk->enable_bit);
 686                         omap_writew(regval16, clk->enable_reg);
 687                 }
 688         }
 689 }
 690
 691 static const struct clkops clkops_generic = {
 692         .enable         = &omap1_clk_enable_generic,
 693         .disable        = &omap1_clk_disable_generic,
 694 };
 695
 696 static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
 697 {
 698         if (clk->flags & RATE_FIXED)
 699                 return clk->rate;
 700
 701         if (clk->round_rate != NULL)
 702                 return clk->round_rate(clk, rate);
 703
 704         return clk->rate;
 705 }
 706
 707 static int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
 708 {
 709         int  ret = -EINVAL;
 710
 711         if (clk->set_rate)
 712                 ret = clk->set_rate(clk, rate);
 713         return ret;
 714 }
 715
 716 /*-------------------------------------------------------------------------
 717  * Omap1 clock reset and init functions
 718  *-------------------------------------------------------------------------*/
 719
 720 #ifdef CONFIG_OMAP_RESET_CLOCKS
 721
 722 static void __init omap1_clk_disable_unused(struct clk *clk)
 723 {
 724         __u32 regval32;
 725
 726         /* Clocks in the DSP domain need api_ck. Just assume bootloader
 727          * has not enabled any DSP clocks */
 728         if (clk->enable_reg == DSP_IDLECT2) {
 729                 printk(KERN_INFO "Skipping reset check for DSP domain "
 730                        "clock \"%s\"\n", clk->name);
 731                 return;
 732         }
 733
 734         /* Is the clock already disabled? */
 735         if (clk->flags & ENABLE_REG_32BIT) {
 736                 if (clk->flags & VIRTUAL_IO_ADDRESS)
 737                         regval32 = __raw_readl(clk->enable_reg);
 738                         else
 739                                 regval32 = omap_readl(clk->enable_reg);
 740         } else {
 741                 if (clk->flags & VIRTUAL_IO_ADDRESS)
 742                         regval32 = __raw_readw(clk->enable_reg);
 743                 else
 744                         regval32 = omap_readw(clk->enable_reg);
 745         }
 746
 747         if ((regval32 & (1 << clk->enable_bit)) == 0)
 748                 return;
 749
 750         /* FIXME: This clock seems to be necessary but no-one
 751          * has asked for its activation. */
 752         if (clk == &tc2_ck              /* FIX: pm.c (SRAM), CCP, Camera */
 753             || clk == &ck_dpll1out.clk  /* FIX: SoSSI, SSR */
 754             || clk == &arm_gpio_ck      /* FIX: GPIO code for 1510 */
 755                 ) {
 756                 printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
 757                        clk->name);
 758                 return;
 759         }
 760
 761         printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name);
 762         clk->ops->disable(clk);
 763         printk(" done\n");
 764 }
 765
 766 #else
 767 #define omap1_clk_disable_unused        NULL
 768 #endif
 769
 770 static struct clk_functions omap1_clk_functions = {
 771         .clk_enable             = omap1_clk_enable,
 772         .clk_disable            = omap1_clk_disable,
 773         .clk_round_rate         = omap1_clk_round_rate,
 774         .clk_set_rate           = omap1_clk_set_rate,
 775         .clk_disable_unused     = omap1_clk_disable_unused,
 776 };
 777
 778 int __init omap1_clk_init(void)
 779 {
 780         struct omap_clk *c;
 781         const struct omap_clock_config *info;
 782         int crystal_type = 0; /* Default 12 MHz */
 783         u32 reg, cpu_mask;
 784
 785 #ifdef CONFIG_DEBUG_LL
 786         /* Resets some clocks that may be left on from bootloader,
 787          * but leaves serial clocks on.
 788          */
 789         omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
 790 #endif
 791
 792         /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
 793         reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
 794         omap_writew(reg, SOFT_REQ_REG);
 795         if (!cpu_is_omap15xx())
 796                 omap_writew(0, SOFT_REQ_REG2);
 797
 798         clk_init(&omap1_clk_functions);
 799
 800         /* By default all idlect1 clocks are allowed to idle */
 801         arm_idlect1_mask = ~0;
 802
 803         cpu_mask = 0;
 804         if (cpu_is_omap16xx())
 805                 cpu_mask |= CK_16XX;
 806         if (cpu_is_omap1510())
 807                 cpu_mask |= CK_1510;
 808         if (cpu_is_omap730())
 809                 cpu_mask |= CK_730;
 810         if (cpu_is_omap310())
 811                 cpu_mask |= CK_310;
 812
 813         for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
 814                 if (c->cpu & cpu_mask) {
 815                         clkdev_add(&c->lk);
 816                         clk_register(c->lk.clk);
 817                 }
 818
 819         info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
 820         if (info != NULL) {
 821                 if (!cpu_is_omap15xx())
 822                         crystal_type = info->system_clock_type;
 823         }
 824
 825 #if defined(CONFIG_ARCH_OMAP730)
 826         ck_ref.rate = 13000000;
 827 #elif defined(CONFIG_ARCH_OMAP16XX)
 828         if (crystal_type == 2)
 829                 ck_ref.rate = 19200000;
 830 #endif
 831
 832         printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
 833                omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
 834                omap_readw(ARM_CKCTL));
 835
 836         /* We want to be in syncronous scalable mode */
 837         omap_writew(0x1000, ARM_SYSST);
 838
 839 #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
 840         /* Use values set by bootloader. Determine PLL rate and recalculate
 841          * dependent clocks as if kernel had changed PLL or divisors.
 842          */
 843         {
 844                 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
 845
 846                 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
 847                 if (pll_ctl_val & 0x10) {
 848                         /* PLL enabled, apply multiplier and divisor */
 849                         if (pll_ctl_val & 0xf80)
 850                                 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
 851                         ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
 852                 } else {
 853                         /* PLL disabled, apply bypass divisor */
 854                         switch (pll_ctl_val & 0xc) {
 855                         case 0:
 856                                 break;
 857                         case 0x4:
 858                                 ck_dpll1.rate /= 2;
 859                                 break;
 860                         default:
 861                                 ck_dpll1.rate /= 4;
 862                                 break;
 863                         }
 864                 }
 865         }
 866 #else
 867         /* Find the highest supported frequency and enable it */
 868         if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
 869                 printk(KERN_ERR "System frequencies not set. Check your config.\n");
 870                 /* Guess sane values (60MHz) */
 871                 omap_writew(0x2290, DPLL_CTL);
 872                 omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL);
 873                 ck_dpll1.rate = 60000000;
 874         }
 875 #endif
 876         propagate_rate(&ck_dpll1);
 877         /* Cache rates for clocks connected to ck_ref (not dpll1) */
 878         propagate_rate(&ck_ref);
 879         printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
 880                 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
 881                ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
 882                ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
 883                arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
 884
 885 #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
 886         /* Select slicer output as OMAP input clock */
 887         omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
 888 #endif
 889
 890         /* Amstrad Delta wants BCLK high when inactive */
 891         if (machine_is_ams_delta())
 892                 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
 893                                 (1 << SDW_MCLK_INV_BIT),
 894                                 ULPD_CLOCK_CTRL);
 895
 896         /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
 897         /* (on 730, bit 13 must not be cleared) */
 898         if (cpu_is_omap730())
 899                 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
 900         else
 901                 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
 902
 903         /* Put DSP/MPUI into reset until needed */
 904         omap_writew(0, ARM_RSTCT1);
 905         omap_writew(1, ARM_RSTCT2);
 906         omap_writew(0x400, ARM_IDLECT1);
 907
 908         /*
 909          * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
 910          * of the ARM_IDLECT2 register must be set to zero. The power-on
 911          * default value of this bit is one.
 912          */
 913         omap_writew(0x0000, ARM_IDLECT2);       /* Turn LCD clock off also */
 914
 915         /*
 916          * Only enable those clocks we will need, let the drivers
 917          * enable other clocks as necessary
 918          */
 919         clk_enable(&armper_ck.clk);
 920         clk_enable(&armxor_ck.clk);
 921         clk_enable(&armtim_ck.clk); /* This should be done by timer code */
 922
 923         if (cpu_is_omap15xx())
 924                 clk_enable(&arm_gpio_ck);
 925
 926         return 0;
 927 }