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[linux-2.6-omap-h63xx.git] / arch / arm / mach-omap1 / clock.c
1 /*
2  *  linux/arch/arm/mach-omap1/clock.c
3  *
4  *  Copyright (C) 2004 - 2005 Nokia corporation
5  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6  *
7  *  Modified to use omap shared clock framework by
8  *  Tony Lindgren <tony@atomide.com>
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software Foundation.
13  */
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/io.h>
21
22 #include <asm/mach-types.h>
23
24 #include <mach/cpu.h>
25 #include <mach/usb.h>
26 #include <mach/clock.h>
27 #include <mach/sram.h>
28
29 #include "clock.h"
30
31 __u32 arm_idlect1_mask;
32
33 /*-------------------------------------------------------------------------
34  * Omap1 specific clock functions
35  *-------------------------------------------------------------------------*/
36
37 static void omap1_watchdog_recalc(struct clk * clk)
38 {
39         clk->rate = clk->parent->rate / 14;
40 }
41
42 static void omap1_uart_recalc(struct clk * clk)
43 {
44         unsigned int val = omap_readl(clk->enable_reg);
45         if (val & clk->enable_bit)
46                 clk->rate = 48000000;
47         else
48                 clk->rate = 12000000;
49 }
50
51 static void omap1_sossi_recalc(struct clk *clk)
52 {
53         u32 div = omap_readl(MOD_CONF_CTRL_1);
54
55         div = (div >> 17) & 0x7;
56         div++;
57         clk->rate = clk->parent->rate / div;
58 }
59
60 static int omap1_clk_enable_dsp_domain(struct clk *clk)
61 {
62         int retval;
63
64         retval = omap1_clk_enable(&api_ck.clk);
65         if (!retval) {
66                 retval = omap1_clk_enable_generic(clk);
67                 omap1_clk_disable(&api_ck.clk);
68         }
69
70         return retval;
71 }
72
73 static void omap1_clk_disable_dsp_domain(struct clk *clk)
74 {
75         if (omap1_clk_enable(&api_ck.clk) == 0) {
76                 omap1_clk_disable_generic(clk);
77                 omap1_clk_disable(&api_ck.clk);
78         }
79 }
80
81 static int omap1_clk_enable_uart_functional(struct clk *clk)
82 {
83         int ret;
84         struct uart_clk *uclk;
85
86         ret = omap1_clk_enable_generic(clk);
87         if (ret == 0) {
88                 /* Set smart idle acknowledgement mode */
89                 uclk = (struct uart_clk *)clk;
90                 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
91                             uclk->sysc_addr);
92         }
93
94         return ret;
95 }
96
97 static void omap1_clk_disable_uart_functional(struct clk *clk)
98 {
99         struct uart_clk *uclk;
100
101         /* Set force idle acknowledgement mode */
102         uclk = (struct uart_clk *)clk;
103         omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
104
105         omap1_clk_disable_generic(clk);
106 }
107
108 static void omap1_clk_allow_idle(struct clk *clk)
109 {
110         struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
111
112         if (!(clk->flags & CLOCK_IDLE_CONTROL))
113                 return;
114
115         if (iclk->no_idle_count > 0 && !(--iclk->no_idle_count))
116                 arm_idlect1_mask |= 1 << iclk->idlect_shift;
117 }
118
119 static void omap1_clk_deny_idle(struct clk *clk)
120 {
121         struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
122
123         if (!(clk->flags & CLOCK_IDLE_CONTROL))
124                 return;
125
126         if (iclk->no_idle_count++ == 0)
127                 arm_idlect1_mask &= ~(1 << iclk->idlect_shift);
128 }
129
130 static __u16 verify_ckctl_value(__u16 newval)
131 {
132         /* This function checks for following limitations set
133          * by the hardware (all conditions must be true):
134          * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
135          * ARM_CK >= TC_CK
136          * DSP_CK >= TC_CK
137          * DSPMMU_CK >= TC_CK
138          *
139          * In addition following rules are enforced:
140          * LCD_CK <= TC_CK
141          * ARMPER_CK <= TC_CK
142          *
143          * However, maximum frequencies are not checked for!
144          */
145         __u8 per_exp;
146         __u8 lcd_exp;
147         __u8 arm_exp;
148         __u8 dsp_exp;
149         __u8 tc_exp;
150         __u8 dspmmu_exp;
151
152         per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
153         lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
154         arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
155         dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
156         tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
157         dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
158
159         if (dspmmu_exp < dsp_exp)
160                 dspmmu_exp = dsp_exp;
161         if (dspmmu_exp > dsp_exp+1)
162                 dspmmu_exp = dsp_exp+1;
163         if (tc_exp < arm_exp)
164                 tc_exp = arm_exp;
165         if (tc_exp < dspmmu_exp)
166                 tc_exp = dspmmu_exp;
167         if (tc_exp > lcd_exp)
168                 lcd_exp = tc_exp;
169         if (tc_exp > per_exp)
170                 per_exp = tc_exp;
171
172         newval &= 0xf000;
173         newval |= per_exp << CKCTL_PERDIV_OFFSET;
174         newval |= lcd_exp << CKCTL_LCDDIV_OFFSET;
175         newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
176         newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
177         newval |= tc_exp << CKCTL_TCDIV_OFFSET;
178         newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
179
180         return newval;
181 }
182
183 static int calc_dsor_exp(struct clk *clk, unsigned long rate)
184 {
185         /* Note: If target frequency is too low, this function will return 4,
186          * which is invalid value. Caller must check for this value and act
187          * accordingly.
188          *
189          * Note: This function does not check for following limitations set
190          * by the hardware (all conditions must be true):
191          * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
192          * ARM_CK >= TC_CK
193          * DSP_CK >= TC_CK
194          * DSPMMU_CK >= TC_CK
195          */
196         unsigned long realrate;
197         struct clk * parent;
198         unsigned  dsor_exp;
199
200         if (unlikely(!(clk->flags & RATE_CKCTL)))
201                 return -EINVAL;
202
203         parent = clk->parent;
204         if (unlikely(parent == 0))
205                 return -EIO;
206
207         realrate = parent->rate;
208         for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
209                 if (realrate <= rate)
210                         break;
211
212                 realrate /= 2;
213         }
214
215         return dsor_exp;
216 }
217
218 static void omap1_ckctl_recalc(struct clk * clk)
219 {
220         int dsor;
221
222         /* Calculate divisor encoded as 2-bit exponent */
223         dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
224
225         if (unlikely(clk->rate == clk->parent->rate / dsor))
226                 return; /* No change, quick exit */
227         clk->rate = clk->parent->rate / dsor;
228
229         if (unlikely(clk->flags & RATE_PROPAGATES))
230                 propagate_rate(clk);
231 }
232
233 static void omap1_ckctl_recalc_dsp_domain(struct clk * clk)
234 {
235         int dsor;
236
237         /* Calculate divisor encoded as 2-bit exponent
238          *
239          * The clock control bits are in DSP domain,
240          * so api_ck is needed for access.
241          * Note that DSP_CKCTL virt addr = phys addr, so
242          * we must use __raw_readw() instead of omap_readw().
243          */
244         omap1_clk_enable(&api_ck.clk);
245         dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
246         omap1_clk_disable(&api_ck.clk);
247
248         if (unlikely(clk->rate == clk->parent->rate / dsor))
249                 return; /* No change, quick exit */
250         clk->rate = clk->parent->rate / dsor;
251
252         if (unlikely(clk->flags & RATE_PROPAGATES))
253                 propagate_rate(clk);
254 }
255
256 /* MPU virtual clock functions */
257 static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
258 {
259         /* Find the highest supported frequency <= rate and switch to it */
260         struct mpu_rate * ptr;
261
262         if (clk != &virtual_ck_mpu)
263                 return -EINVAL;
264
265         for (ptr = rate_table; ptr->rate; ptr++) {
266                 if (ptr->xtal != ck_ref.rate)
267                         continue;
268
269                 /* DPLL1 cannot be reprogrammed without risking system crash */
270                 if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate)
271                         continue;
272
273                 /* Can check only after xtal frequency check */
274                 if (ptr->rate <= rate)
275                         break;
276         }
277
278         if (!ptr->rate)
279                 return -EINVAL;
280
281         /*
282          * In most cases we should not need to reprogram DPLL.
283          * Reprogramming the DPLL is tricky, it must be done from SRAM.
284          * (on 730, bit 13 must always be 1)
285          */
286         if (cpu_is_omap730())
287                 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
288         else
289                 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
290
291         ck_dpll1.rate = ptr->pll_rate;
292         propagate_rate(&ck_dpll1);
293         return 0;
294 }
295
296 static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
297 {
298         int  ret = -EINVAL;
299         int  dsor_exp;
300         __u16  regval;
301
302         if (clk->flags & RATE_CKCTL) {
303                 dsor_exp = calc_dsor_exp(clk, rate);
304                 if (dsor_exp > 3)
305                         dsor_exp = -EINVAL;
306                 if (dsor_exp < 0)
307                         return dsor_exp;
308
309                 regval = __raw_readw(DSP_CKCTL);
310                 regval &= ~(3 << clk->rate_offset);
311                 regval |= dsor_exp << clk->rate_offset;
312                 __raw_writew(regval, DSP_CKCTL);
313                 clk->rate = clk->parent->rate / (1 << dsor_exp);
314                 ret = 0;
315         }
316
317         if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
318                 propagate_rate(clk);
319
320         return ret;
321 }
322
323 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate)
324 {
325         /* Find the highest supported frequency <= rate */
326         struct mpu_rate * ptr;
327         long  highest_rate;
328
329         if (clk != &virtual_ck_mpu)
330                 return -EINVAL;
331
332         highest_rate = -EINVAL;
333
334         for (ptr = rate_table; ptr->rate; ptr++) {
335                 if (ptr->xtal != ck_ref.rate)
336                         continue;
337
338                 highest_rate = ptr->rate;
339
340                 /* Can check only after xtal frequency check */
341                 if (ptr->rate <= rate)
342                         break;
343         }
344
345         return highest_rate;
346 }
347
348 static unsigned calc_ext_dsor(unsigned long rate)
349 {
350         unsigned dsor;
351
352         /* MCLK and BCLK divisor selection is not linear:
353          * freq = 96MHz / dsor
354          *
355          * RATIO_SEL range: dsor <-> RATIO_SEL
356          * 0..6: (RATIO_SEL+2) <-> (dsor-2)
357          * 6..48:  (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
358          * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
359          * can not be used.
360          */
361         for (dsor = 2; dsor < 96; ++dsor) {
362                 if ((dsor & 1) && dsor > 8)
363                         continue;
364                 if (rate >= 96000000 / dsor)
365                         break;
366         }
367         return dsor;
368 }
369
370 /* Only needed on 1510 */
371 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate)
372 {
373         unsigned int val;
374
375         val = omap_readl(clk->enable_reg);
376         if (rate == 12000000)
377                 val &= ~(1 << clk->enable_bit);
378         else if (rate == 48000000)
379                 val |= (1 << clk->enable_bit);
380         else
381                 return -EINVAL;
382         omap_writel(val, clk->enable_reg);
383         clk->rate = rate;
384
385         return 0;
386 }
387
388 /* External clock (MCLK & BCLK) functions */
389 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate)
390 {
391         unsigned dsor;
392         __u16 ratio_bits;
393
394         dsor = calc_ext_dsor(rate);
395         clk->rate = 96000000 / dsor;
396         if (dsor > 8)
397                 ratio_bits = ((dsor - 8) / 2 + 6) << 2;
398         else
399                 ratio_bits = (dsor - 2) << 2;
400
401         ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd;
402         omap_writew(ratio_bits, clk->enable_reg);
403
404         return 0;
405 }
406
407 static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
408 {
409         u32 l;
410         int div;
411         unsigned long p_rate;
412
413         p_rate = clk->parent->rate;
414         /* Round towards slower frequency */
415         div = (p_rate + rate - 1) / rate;
416         div--;
417         if (div < 0 || div > 7)
418                 return -EINVAL;
419
420         l = omap_readl(MOD_CONF_CTRL_1);
421         l &= ~(7 << 17);
422         l |= div << 17;
423         omap_writel(l, MOD_CONF_CTRL_1);
424
425         clk->rate = p_rate / (div + 1);
426         if (unlikely(clk->flags & RATE_PROPAGATES))
427                 propagate_rate(clk);
428
429         return 0;
430 }
431
432 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate)
433 {
434         return 96000000 / calc_ext_dsor(rate);
435 }
436
437 static void omap1_init_ext_clk(struct clk * clk)
438 {
439         unsigned dsor;
440         __u16 ratio_bits;
441
442         /* Determine current rate and ensure clock is based on 96MHz APLL */
443         ratio_bits = omap_readw(clk->enable_reg) & ~1;
444         omap_writew(ratio_bits, clk->enable_reg);
445
446         ratio_bits = (ratio_bits & 0xfc) >> 2;
447         if (ratio_bits > 6)
448                 dsor = (ratio_bits - 6) * 2 + 8;
449         else
450                 dsor = ratio_bits + 2;
451
452         clk-> rate = 96000000 / dsor;
453 }
454
455 static int omap1_clk_enable(struct clk *clk)
456 {
457         int ret = 0;
458         if (clk->usecount++ == 0) {
459                 if (likely(clk->parent)) {
460                         ret = omap1_clk_enable(clk->parent);
461
462                         if (unlikely(ret != 0)) {
463                                 clk->usecount--;
464                                 return ret;
465                         }
466
467                         if (clk->flags & CLOCK_NO_IDLE_PARENT)
468                                 omap1_clk_deny_idle(clk->parent);
469                 }
470
471                 ret = clk->enable(clk);
472
473                 if (unlikely(ret != 0) && clk->parent) {
474                         omap1_clk_disable(clk->parent);
475                         clk->usecount--;
476                 }
477         }
478
479         return ret;
480 }
481
482 static void omap1_clk_disable(struct clk *clk)
483 {
484         if (clk->usecount > 0 && !(--clk->usecount)) {
485                 clk->disable(clk);
486                 if (likely(clk->parent)) {
487                         omap1_clk_disable(clk->parent);
488                         if (clk->flags & CLOCK_NO_IDLE_PARENT)
489                                 omap1_clk_allow_idle(clk->parent);
490                 }
491         }
492 }
493
494 static int omap1_clk_enable_generic(struct clk *clk)
495 {
496         __u16 regval16;
497         __u32 regval32;
498
499         if (clk->flags & ALWAYS_ENABLED)
500                 return 0;
501
502         if (unlikely(clk->enable_reg == 0)) {
503                 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
504                        clk->name);
505                 return -EINVAL;
506         }
507
508         if (clk->flags & ENABLE_REG_32BIT) {
509                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
510                         regval32 = __raw_readl(clk->enable_reg);
511                         regval32 |= (1 << clk->enable_bit);
512                         __raw_writel(regval32, clk->enable_reg);
513                 } else {
514                         regval32 = omap_readl(clk->enable_reg);
515                         regval32 |= (1 << clk->enable_bit);
516                         omap_writel(regval32, clk->enable_reg);
517                 }
518         } else {
519                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
520                         regval16 = __raw_readw(clk->enable_reg);
521                         regval16 |= (1 << clk->enable_bit);
522                         __raw_writew(regval16, clk->enable_reg);
523                 } else {
524                         regval16 = omap_readw(clk->enable_reg);
525                         regval16 |= (1 << clk->enable_bit);
526                         omap_writew(regval16, clk->enable_reg);
527                 }
528         }
529
530         return 0;
531 }
532
533 static void omap1_clk_disable_generic(struct clk *clk)
534 {
535         __u16 regval16;
536         __u32 regval32;
537
538         if (clk->enable_reg == 0)
539                 return;
540
541         if (clk->flags & ENABLE_REG_32BIT) {
542                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
543                         regval32 = __raw_readl(clk->enable_reg);
544                         regval32 &= ~(1 << clk->enable_bit);
545                         __raw_writel(regval32, clk->enable_reg);
546                 } else {
547                         regval32 = omap_readl(clk->enable_reg);
548                         regval32 &= ~(1 << clk->enable_bit);
549                         omap_writel(regval32, clk->enable_reg);
550                 }
551         } else {
552                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
553                         regval16 = __raw_readw(clk->enable_reg);
554                         regval16 &= ~(1 << clk->enable_bit);
555                         __raw_writew(regval16, clk->enable_reg);
556                 } else {
557                         regval16 = omap_readw(clk->enable_reg);
558                         regval16 &= ~(1 << clk->enable_bit);
559                         omap_writew(regval16, clk->enable_reg);
560                 }
561         }
562 }
563
564 static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
565 {
566         int dsor_exp;
567
568         if (clk->flags & RATE_FIXED)
569                 return clk->rate;
570
571         if (clk->flags & RATE_CKCTL) {
572                 dsor_exp = calc_dsor_exp(clk, rate);
573                 if (dsor_exp < 0)
574                         return dsor_exp;
575                 if (dsor_exp > 3)
576                         dsor_exp = 3;
577                 return clk->parent->rate / (1 << dsor_exp);
578         }
579
580         if(clk->round_rate != 0)
581                 return clk->round_rate(clk, rate);
582
583         return clk->rate;
584 }
585
586 static int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
587 {
588         int  ret = -EINVAL;
589         int  dsor_exp;
590         __u16  regval;
591
592         if (clk->set_rate)
593                 ret = clk->set_rate(clk, rate);
594         else if (clk->flags & RATE_CKCTL) {
595                 dsor_exp = calc_dsor_exp(clk, rate);
596                 if (dsor_exp > 3)
597                         dsor_exp = -EINVAL;
598                 if (dsor_exp < 0)
599                         return dsor_exp;
600
601                 regval = omap_readw(ARM_CKCTL);
602                 regval &= ~(3 << clk->rate_offset);
603                 regval |= dsor_exp << clk->rate_offset;
604                 regval = verify_ckctl_value(regval);
605                 omap_writew(regval, ARM_CKCTL);
606                 clk->rate = clk->parent->rate / (1 << dsor_exp);
607                 ret = 0;
608         }
609
610         if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
611                 propagate_rate(clk);
612
613         return ret;
614 }
615
616 /*-------------------------------------------------------------------------
617  * Omap1 clock reset and init functions
618  *-------------------------------------------------------------------------*/
619
620 #ifdef CONFIG_OMAP_RESET_CLOCKS
621
622 static void __init omap1_clk_disable_unused(struct clk *clk)
623 {
624         __u32 regval32;
625
626         /* Clocks in the DSP domain need api_ck. Just assume bootloader
627          * has not enabled any DSP clocks */
628         if ((u32)clk->enable_reg == DSP_IDLECT2) {
629                 printk(KERN_INFO "Skipping reset check for DSP domain "
630                        "clock \"%s\"\n", clk->name);
631                 return;
632         }
633
634         /* Is the clock already disabled? */
635         if (clk->flags & ENABLE_REG_32BIT) {
636                 if (clk->flags & VIRTUAL_IO_ADDRESS)
637                         regval32 = __raw_readl(clk->enable_reg);
638                         else
639                                 regval32 = omap_readl(clk->enable_reg);
640         } else {
641                 if (clk->flags & VIRTUAL_IO_ADDRESS)
642                         regval32 = __raw_readw(clk->enable_reg);
643                 else
644                         regval32 = omap_readw(clk->enable_reg);
645         }
646
647         if ((regval32 & (1 << clk->enable_bit)) == 0)
648                 return;
649
650         /* FIXME: This clock seems to be necessary but no-one
651          * has asked for its activation. */
652         if (clk == &tc2_ck              /* FIX: pm.c (SRAM), CCP, Camera */
653             || clk == &ck_dpll1out.clk  /* FIX: SoSSI, SSR */
654             || clk == &arm_gpio_ck      /* FIX: GPIO code for 1510 */
655                 ) {
656                 printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
657                        clk->name);
658                 return;
659         }
660
661         printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name);
662         clk->disable(clk);
663         printk(" done\n");
664 }
665
666 #else
667 #define omap1_clk_disable_unused        NULL
668 #endif
669
670 static struct clk_functions omap1_clk_functions = {
671         .clk_enable             = omap1_clk_enable,
672         .clk_disable            = omap1_clk_disable,
673         .clk_round_rate         = omap1_clk_round_rate,
674         .clk_set_rate           = omap1_clk_set_rate,
675         .clk_disable_unused     = omap1_clk_disable_unused,
676 };
677
678 int __init omap1_clk_init(void)
679 {
680         struct clk ** clkp;
681         const struct omap_clock_config *info;
682         int crystal_type = 0; /* Default 12 MHz */
683         u32 reg;
684
685 #ifdef CONFIG_DEBUG_LL
686         /* Resets some clocks that may be left on from bootloader,
687          * but leaves serial clocks on.
688          */
689         omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
690 #endif
691
692         /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
693         reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
694         omap_writew(reg, SOFT_REQ_REG);
695         if (!cpu_is_omap15xx())
696                 omap_writew(0, SOFT_REQ_REG2);
697
698         clk_init(&omap1_clk_functions);
699
700         /* By default all idlect1 clocks are allowed to idle */
701         arm_idlect1_mask = ~0;
702
703         for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) {
704                 if (((*clkp)->flags &CLOCK_IN_OMAP1510) && cpu_is_omap1510()) {
705                         clk_register(*clkp);
706                         continue;
707                 }
708
709                 if (((*clkp)->flags &CLOCK_IN_OMAP16XX) && cpu_is_omap16xx()) {
710                         clk_register(*clkp);
711                         continue;
712                 }
713
714                 if (((*clkp)->flags &CLOCK_IN_OMAP730) && cpu_is_omap730()) {
715                         clk_register(*clkp);
716                         continue;
717                 }
718
719                 if (((*clkp)->flags &CLOCK_IN_OMAP310) && cpu_is_omap310()) {
720                         clk_register(*clkp);
721                         continue;
722                 }
723         }
724
725         info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
726         if (info != NULL) {
727                 if (!cpu_is_omap15xx())
728                         crystal_type = info->system_clock_type;
729         }
730
731 #if defined(CONFIG_ARCH_OMAP730)
732         ck_ref.rate = 13000000;
733 #elif defined(CONFIG_ARCH_OMAP16XX)
734         if (crystal_type == 2)
735                 ck_ref.rate = 19200000;
736 #endif
737
738         printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
739                omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
740                omap_readw(ARM_CKCTL));
741
742         /* We want to be in syncronous scalable mode */
743         omap_writew(0x1000, ARM_SYSST);
744
745 #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
746         /* Use values set by bootloader. Determine PLL rate and recalculate
747          * dependent clocks as if kernel had changed PLL or divisors.
748          */
749         {
750                 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
751
752                 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
753                 if (pll_ctl_val & 0x10) {
754                         /* PLL enabled, apply multiplier and divisor */
755                         if (pll_ctl_val & 0xf80)
756                                 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
757                         ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
758                 } else {
759                         /* PLL disabled, apply bypass divisor */
760                         switch (pll_ctl_val & 0xc) {
761                         case 0:
762                                 break;
763                         case 0x4:
764                                 ck_dpll1.rate /= 2;
765                                 break;
766                         default:
767                                 ck_dpll1.rate /= 4;
768                                 break;
769                         }
770                 }
771         }
772         propagate_rate(&ck_dpll1);
773 #else
774         /* Find the highest supported frequency and enable it */
775         if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
776                 printk(KERN_ERR "System frequencies not set. Check your config.\n");
777                 /* Guess sane values (60MHz) */
778                 omap_writew(0x2290, DPLL_CTL);
779                 omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL);
780                 ck_dpll1.rate = 60000000;
781                 propagate_rate(&ck_dpll1);
782         }
783 #endif
784         /* Cache rates for clocks connected to ck_ref (not dpll1) */
785         propagate_rate(&ck_ref);
786         printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
787                 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
788                ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
789                ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
790                arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
791
792 #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
793         /* Select slicer output as OMAP input clock */
794         omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
795 #endif
796
797         /* Amstrad Delta wants BCLK high when inactive */
798         if (machine_is_ams_delta())
799                 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
800                                 (1 << SDW_MCLK_INV_BIT),
801                                 ULPD_CLOCK_CTRL);
802
803         /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
804         /* (on 730, bit 13 must not be cleared) */
805         if (cpu_is_omap730())
806                 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
807         else
808                 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
809
810         /* Put DSP/MPUI into reset until needed */
811         omap_writew(0, ARM_RSTCT1);
812         omap_writew(1, ARM_RSTCT2);
813         omap_writew(0x400, ARM_IDLECT1);
814
815         /*
816          * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
817          * of the ARM_IDLECT2 register must be set to zero. The power-on
818          * default value of this bit is one.
819          */
820         omap_writew(0x0000, ARM_IDLECT2);       /* Turn LCD clock off also */
821
822         /*
823          * Only enable those clocks we will need, let the drivers
824          * enable other clocks as necessary
825          */
826         clk_enable(&armper_ck.clk);
827         clk_enable(&armxor_ck.clk);
828         clk_enable(&armtim_ck.clk); /* This should be done by timer code */
829
830         if (cpu_is_omap15xx())
831                 clk_enable(&arm_gpio_ck);
832
833         return 0;
834 }
835