2 * linux/arch/arm/mach-omap1/clock.c
4 * Copyright (C) 2004 - 2005 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
7 * Modified to use omap shared clock framework by
8 * Tony Lindgren <tony@atomide.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
22 #include <asm/mach-types.h>
26 #include <mach/clock.h>
27 #include <mach/sram.h>
31 __u32 arm_idlect1_mask;
33 /*-------------------------------------------------------------------------
34 * Omap1 specific clock functions
35 *-------------------------------------------------------------------------*/
37 static void omap1_watchdog_recalc(struct clk * clk)
39 clk->rate = clk->parent->rate / 14;
42 static void omap1_uart_recalc(struct clk * clk)
44 unsigned int val = omap_readl(clk->enable_reg);
45 if (val & clk->enable_bit)
51 static void omap1_sossi_recalc(struct clk *clk)
53 u32 div = omap_readl(MOD_CONF_CTRL_1);
55 div = (div >> 17) & 0x7;
57 clk->rate = clk->parent->rate / div;
60 static int omap1_clk_enable_dsp_domain(struct clk *clk)
64 retval = omap1_clk_enable(&api_ck.clk);
66 retval = omap1_clk_enable_generic(clk);
67 omap1_clk_disable(&api_ck.clk);
73 static void omap1_clk_disable_dsp_domain(struct clk *clk)
75 if (omap1_clk_enable(&api_ck.clk) == 0) {
76 omap1_clk_disable_generic(clk);
77 omap1_clk_disable(&api_ck.clk);
81 static int omap1_clk_enable_uart_functional(struct clk *clk)
84 struct uart_clk *uclk;
86 ret = omap1_clk_enable_generic(clk);
88 /* Set smart idle acknowledgement mode */
89 uclk = (struct uart_clk *)clk;
90 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
97 static void omap1_clk_disable_uart_functional(struct clk *clk)
99 struct uart_clk *uclk;
101 /* Set force idle acknowledgement mode */
102 uclk = (struct uart_clk *)clk;
103 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
105 omap1_clk_disable_generic(clk);
108 static void omap1_clk_allow_idle(struct clk *clk)
110 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
112 if (!(clk->flags & CLOCK_IDLE_CONTROL))
115 if (iclk->no_idle_count > 0 && !(--iclk->no_idle_count))
116 arm_idlect1_mask |= 1 << iclk->idlect_shift;
119 static void omap1_clk_deny_idle(struct clk *clk)
121 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
123 if (!(clk->flags & CLOCK_IDLE_CONTROL))
126 if (iclk->no_idle_count++ == 0)
127 arm_idlect1_mask &= ~(1 << iclk->idlect_shift);
130 static __u16 verify_ckctl_value(__u16 newval)
132 /* This function checks for following limitations set
133 * by the hardware (all conditions must be true):
134 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
139 * In addition following rules are enforced:
143 * However, maximum frequencies are not checked for!
152 per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
153 lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
154 arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
155 dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
156 tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
157 dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
159 if (dspmmu_exp < dsp_exp)
160 dspmmu_exp = dsp_exp;
161 if (dspmmu_exp > dsp_exp+1)
162 dspmmu_exp = dsp_exp+1;
163 if (tc_exp < arm_exp)
165 if (tc_exp < dspmmu_exp)
167 if (tc_exp > lcd_exp)
169 if (tc_exp > per_exp)
173 newval |= per_exp << CKCTL_PERDIV_OFFSET;
174 newval |= lcd_exp << CKCTL_LCDDIV_OFFSET;
175 newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
176 newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
177 newval |= tc_exp << CKCTL_TCDIV_OFFSET;
178 newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
183 static int calc_dsor_exp(struct clk *clk, unsigned long rate)
185 /* Note: If target frequency is too low, this function will return 4,
186 * which is invalid value. Caller must check for this value and act
189 * Note: This function does not check for following limitations set
190 * by the hardware (all conditions must be true):
191 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
196 unsigned long realrate;
200 if (unlikely(!(clk->flags & RATE_CKCTL)))
203 parent = clk->parent;
204 if (unlikely(parent == 0))
207 realrate = parent->rate;
208 for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
209 if (realrate <= rate)
218 static void omap1_ckctl_recalc(struct clk * clk)
222 /* Calculate divisor encoded as 2-bit exponent */
223 dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
225 if (unlikely(clk->rate == clk->parent->rate / dsor))
226 return; /* No change, quick exit */
227 clk->rate = clk->parent->rate / dsor;
229 if (unlikely(clk->flags & RATE_PROPAGATES))
233 static void omap1_ckctl_recalc_dsp_domain(struct clk * clk)
237 /* Calculate divisor encoded as 2-bit exponent
239 * The clock control bits are in DSP domain,
240 * so api_ck is needed for access.
241 * Note that DSP_CKCTL virt addr = phys addr, so
242 * we must use __raw_readw() instead of omap_readw().
244 omap1_clk_enable(&api_ck.clk);
245 dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
246 omap1_clk_disable(&api_ck.clk);
248 if (unlikely(clk->rate == clk->parent->rate / dsor))
249 return; /* No change, quick exit */
250 clk->rate = clk->parent->rate / dsor;
252 if (unlikely(clk->flags & RATE_PROPAGATES))
256 /* MPU virtual clock functions */
257 static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
259 /* Find the highest supported frequency <= rate and switch to it */
260 struct mpu_rate * ptr;
262 if (clk != &virtual_ck_mpu)
265 for (ptr = rate_table; ptr->rate; ptr++) {
266 if (ptr->xtal != ck_ref.rate)
269 /* DPLL1 cannot be reprogrammed without risking system crash */
270 if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate)
273 /* Can check only after xtal frequency check */
274 if (ptr->rate <= rate)
282 * In most cases we should not need to reprogram DPLL.
283 * Reprogramming the DPLL is tricky, it must be done from SRAM.
284 * (on 730, bit 13 must always be 1)
286 if (cpu_is_omap730())
287 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
289 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
291 ck_dpll1.rate = ptr->pll_rate;
292 propagate_rate(&ck_dpll1);
296 static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
302 if (clk->flags & RATE_CKCTL) {
303 dsor_exp = calc_dsor_exp(clk, rate);
309 regval = __raw_readw(DSP_CKCTL);
310 regval &= ~(3 << clk->rate_offset);
311 regval |= dsor_exp << clk->rate_offset;
312 __raw_writew(regval, DSP_CKCTL);
313 clk->rate = clk->parent->rate / (1 << dsor_exp);
317 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
323 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate)
325 /* Find the highest supported frequency <= rate */
326 struct mpu_rate * ptr;
329 if (clk != &virtual_ck_mpu)
332 highest_rate = -EINVAL;
334 for (ptr = rate_table; ptr->rate; ptr++) {
335 if (ptr->xtal != ck_ref.rate)
338 highest_rate = ptr->rate;
340 /* Can check only after xtal frequency check */
341 if (ptr->rate <= rate)
348 static unsigned calc_ext_dsor(unsigned long rate)
352 /* MCLK and BCLK divisor selection is not linear:
353 * freq = 96MHz / dsor
355 * RATIO_SEL range: dsor <-> RATIO_SEL
356 * 0..6: (RATIO_SEL+2) <-> (dsor-2)
357 * 6..48: (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
358 * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
361 for (dsor = 2; dsor < 96; ++dsor) {
362 if ((dsor & 1) && dsor > 8)
364 if (rate >= 96000000 / dsor)
370 /* Only needed on 1510 */
371 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate)
375 val = omap_readl(clk->enable_reg);
376 if (rate == 12000000)
377 val &= ~(1 << clk->enable_bit);
378 else if (rate == 48000000)
379 val |= (1 << clk->enable_bit);
382 omap_writel(val, clk->enable_reg);
388 /* External clock (MCLK & BCLK) functions */
389 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate)
394 dsor = calc_ext_dsor(rate);
395 clk->rate = 96000000 / dsor;
397 ratio_bits = ((dsor - 8) / 2 + 6) << 2;
399 ratio_bits = (dsor - 2) << 2;
401 ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd;
402 omap_writew(ratio_bits, clk->enable_reg);
407 static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
411 unsigned long p_rate;
413 p_rate = clk->parent->rate;
414 /* Round towards slower frequency */
415 div = (p_rate + rate - 1) / rate;
417 if (div < 0 || div > 7)
420 l = omap_readl(MOD_CONF_CTRL_1);
423 omap_writel(l, MOD_CONF_CTRL_1);
425 clk->rate = p_rate / (div + 1);
426 if (unlikely(clk->flags & RATE_PROPAGATES))
432 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate)
434 return 96000000 / calc_ext_dsor(rate);
437 static void omap1_init_ext_clk(struct clk * clk)
442 /* Determine current rate and ensure clock is based on 96MHz APLL */
443 ratio_bits = omap_readw(clk->enable_reg) & ~1;
444 omap_writew(ratio_bits, clk->enable_reg);
446 ratio_bits = (ratio_bits & 0xfc) >> 2;
448 dsor = (ratio_bits - 6) * 2 + 8;
450 dsor = ratio_bits + 2;
452 clk-> rate = 96000000 / dsor;
455 static int omap1_clk_enable(struct clk *clk)
458 if (clk->usecount++ == 0) {
459 if (likely(clk->parent)) {
460 ret = omap1_clk_enable(clk->parent);
462 if (unlikely(ret != 0)) {
467 if (clk->flags & CLOCK_NO_IDLE_PARENT)
468 omap1_clk_deny_idle(clk->parent);
471 ret = clk->enable(clk);
473 if (unlikely(ret != 0) && clk->parent) {
474 omap1_clk_disable(clk->parent);
482 static void omap1_clk_disable(struct clk *clk)
484 if (clk->usecount > 0 && !(--clk->usecount)) {
486 if (likely(clk->parent)) {
487 omap1_clk_disable(clk->parent);
488 if (clk->flags & CLOCK_NO_IDLE_PARENT)
489 omap1_clk_allow_idle(clk->parent);
494 static int omap1_clk_enable_generic(struct clk *clk)
499 if (clk->flags & ALWAYS_ENABLED)
502 if (unlikely(clk->enable_reg == 0)) {
503 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
508 if (clk->flags & ENABLE_REG_32BIT) {
509 if (clk->flags & VIRTUAL_IO_ADDRESS) {
510 regval32 = __raw_readl(clk->enable_reg);
511 regval32 |= (1 << clk->enable_bit);
512 __raw_writel(regval32, clk->enable_reg);
514 regval32 = omap_readl(clk->enable_reg);
515 regval32 |= (1 << clk->enable_bit);
516 omap_writel(regval32, clk->enable_reg);
519 if (clk->flags & VIRTUAL_IO_ADDRESS) {
520 regval16 = __raw_readw(clk->enable_reg);
521 regval16 |= (1 << clk->enable_bit);
522 __raw_writew(regval16, clk->enable_reg);
524 regval16 = omap_readw(clk->enable_reg);
525 regval16 |= (1 << clk->enable_bit);
526 omap_writew(regval16, clk->enable_reg);
533 static void omap1_clk_disable_generic(struct clk *clk)
538 if (clk->enable_reg == 0)
541 if (clk->flags & ENABLE_REG_32BIT) {
542 if (clk->flags & VIRTUAL_IO_ADDRESS) {
543 regval32 = __raw_readl(clk->enable_reg);
544 regval32 &= ~(1 << clk->enable_bit);
545 __raw_writel(regval32, clk->enable_reg);
547 regval32 = omap_readl(clk->enable_reg);
548 regval32 &= ~(1 << clk->enable_bit);
549 omap_writel(regval32, clk->enable_reg);
552 if (clk->flags & VIRTUAL_IO_ADDRESS) {
553 regval16 = __raw_readw(clk->enable_reg);
554 regval16 &= ~(1 << clk->enable_bit);
555 __raw_writew(regval16, clk->enable_reg);
557 regval16 = omap_readw(clk->enable_reg);
558 regval16 &= ~(1 << clk->enable_bit);
559 omap_writew(regval16, clk->enable_reg);
564 static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
568 if (clk->flags & RATE_FIXED)
571 if (clk->flags & RATE_CKCTL) {
572 dsor_exp = calc_dsor_exp(clk, rate);
577 return clk->parent->rate / (1 << dsor_exp);
580 if(clk->round_rate != 0)
581 return clk->round_rate(clk, rate);
586 static int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
593 ret = clk->set_rate(clk, rate);
594 else if (clk->flags & RATE_CKCTL) {
595 dsor_exp = calc_dsor_exp(clk, rate);
601 regval = omap_readw(ARM_CKCTL);
602 regval &= ~(3 << clk->rate_offset);
603 regval |= dsor_exp << clk->rate_offset;
604 regval = verify_ckctl_value(regval);
605 omap_writew(regval, ARM_CKCTL);
606 clk->rate = clk->parent->rate / (1 << dsor_exp);
610 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
616 /*-------------------------------------------------------------------------
617 * Omap1 clock reset and init functions
618 *-------------------------------------------------------------------------*/
620 #ifdef CONFIG_OMAP_RESET_CLOCKS
622 static void __init omap1_clk_disable_unused(struct clk *clk)
626 /* Clocks in the DSP domain need api_ck. Just assume bootloader
627 * has not enabled any DSP clocks */
628 if ((u32)clk->enable_reg == DSP_IDLECT2) {
629 printk(KERN_INFO "Skipping reset check for DSP domain "
630 "clock \"%s\"\n", clk->name);
634 /* Is the clock already disabled? */
635 if (clk->flags & ENABLE_REG_32BIT) {
636 if (clk->flags & VIRTUAL_IO_ADDRESS)
637 regval32 = __raw_readl(clk->enable_reg);
639 regval32 = omap_readl(clk->enable_reg);
641 if (clk->flags & VIRTUAL_IO_ADDRESS)
642 regval32 = __raw_readw(clk->enable_reg);
644 regval32 = omap_readw(clk->enable_reg);
647 if ((regval32 & (1 << clk->enable_bit)) == 0)
650 /* FIXME: This clock seems to be necessary but no-one
651 * has asked for its activation. */
652 if (clk == &tc2_ck /* FIX: pm.c (SRAM), CCP, Camera */
653 || clk == &ck_dpll1out.clk /* FIX: SoSSI, SSR */
654 || clk == &arm_gpio_ck /* FIX: GPIO code for 1510 */
656 printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
661 printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name);
667 #define omap1_clk_disable_unused NULL
670 static struct clk_functions omap1_clk_functions = {
671 .clk_enable = omap1_clk_enable,
672 .clk_disable = omap1_clk_disable,
673 .clk_round_rate = omap1_clk_round_rate,
674 .clk_set_rate = omap1_clk_set_rate,
675 .clk_disable_unused = omap1_clk_disable_unused,
678 int __init omap1_clk_init(void)
681 const struct omap_clock_config *info;
682 int crystal_type = 0; /* Default 12 MHz */
685 #ifdef CONFIG_DEBUG_LL
686 /* Resets some clocks that may be left on from bootloader,
687 * but leaves serial clocks on.
689 omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
692 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
693 reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
694 omap_writew(reg, SOFT_REQ_REG);
695 if (!cpu_is_omap15xx())
696 omap_writew(0, SOFT_REQ_REG2);
698 clk_init(&omap1_clk_functions);
700 /* By default all idlect1 clocks are allowed to idle */
701 arm_idlect1_mask = ~0;
703 for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) {
704 if (((*clkp)->flags &CLOCK_IN_OMAP1510) && cpu_is_omap1510()) {
709 if (((*clkp)->flags &CLOCK_IN_OMAP16XX) && cpu_is_omap16xx()) {
714 if (((*clkp)->flags &CLOCK_IN_OMAP730) && cpu_is_omap730()) {
719 if (((*clkp)->flags &CLOCK_IN_OMAP310) && cpu_is_omap310()) {
725 info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
727 if (!cpu_is_omap15xx())
728 crystal_type = info->system_clock_type;
731 #if defined(CONFIG_ARCH_OMAP730)
732 ck_ref.rate = 13000000;
733 #elif defined(CONFIG_ARCH_OMAP16XX)
734 if (crystal_type == 2)
735 ck_ref.rate = 19200000;
738 printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
739 omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
740 omap_readw(ARM_CKCTL));
742 /* We want to be in syncronous scalable mode */
743 omap_writew(0x1000, ARM_SYSST);
745 #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
746 /* Use values set by bootloader. Determine PLL rate and recalculate
747 * dependent clocks as if kernel had changed PLL or divisors.
750 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
752 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
753 if (pll_ctl_val & 0x10) {
754 /* PLL enabled, apply multiplier and divisor */
755 if (pll_ctl_val & 0xf80)
756 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
757 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
759 /* PLL disabled, apply bypass divisor */
760 switch (pll_ctl_val & 0xc) {
772 propagate_rate(&ck_dpll1);
774 /* Find the highest supported frequency and enable it */
775 if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
776 printk(KERN_ERR "System frequencies not set. Check your config.\n");
777 /* Guess sane values (60MHz) */
778 omap_writew(0x2290, DPLL_CTL);
779 omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL);
780 ck_dpll1.rate = 60000000;
781 propagate_rate(&ck_dpll1);
784 /* Cache rates for clocks connected to ck_ref (not dpll1) */
785 propagate_rate(&ck_ref);
786 printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
787 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
788 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
789 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
790 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
792 #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
793 /* Select slicer output as OMAP input clock */
794 omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
797 /* Amstrad Delta wants BCLK high when inactive */
798 if (machine_is_ams_delta())
799 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
800 (1 << SDW_MCLK_INV_BIT),
803 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
804 /* (on 730, bit 13 must not be cleared) */
805 if (cpu_is_omap730())
806 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
808 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
810 /* Put DSP/MPUI into reset until needed */
811 omap_writew(0, ARM_RSTCT1);
812 omap_writew(1, ARM_RSTCT2);
813 omap_writew(0x400, ARM_IDLECT1);
816 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
817 * of the ARM_IDLECT2 register must be set to zero. The power-on
818 * default value of this bit is one.
820 omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */
823 * Only enable those clocks we will need, let the drivers
824 * enable other clocks as necessary
826 clk_enable(&armper_ck.clk);
827 clk_enable(&armxor_ck.clk);
828 clk_enable(&armtim_ck.clk); /* This should be done by timer code */
830 if (cpu_is_omap15xx())
831 clk_enable(&arm_gpio_ck);