arch/arm/mach-omap1/clock.c

   1 /*
   2  *  linux/arch/arm/mach-omap1/clock.c
   3  *
   4  *  Copyright (C) 2004 - 2005 Nokia corporation
   5  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  *
   7  *  Modified to use omap shared clock framework by
   8  *  Tony Lindgren <tony@atomide.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/io.h>
  21
  22 #include <asm/mach-types.h>
  23 #include <asm/clkdev.h>
  24
  25 #include <mach/cpu.h>
  26 #include <mach/usb.h>
  27 #include <mach/clock.h>
  28 #include <mach/sram.h>
  29
  30 static const struct clkops clkops_generic;
  31 static const struct clkops clkops_uart;
  32 static const struct clkops clkops_dspck;
  33
  34 #include "clock.h"
  35
  36 struct omap_clk {
  37         u32             cpu;
  38         struct clk_lookup lk;
  39 };
  40
  41 #define CLK(dev, con, ck, cp)           \
  42         {                               \
  43                  .cpu = cp,             \
  44                 .lk = {                 \
  45                         .dev_id = dev,  \
  46                         .con_id = con,  \
  47                         .clk = ck,      \
  48                 },                      \
  49         }
  50
  51 #define CK_310  (1 << 0)
  52 #define CK_730  (1 << 1)
  53 #define CK_1510 (1 << 2)
  54 #define CK_16XX (1 << 3)
  55
  56 static struct omap_clk omap_clks[] = {
  57         /* non-ULPD clocks */
  58         CLK(NULL,       "ck_ref",       &ck_ref,        CK_16XX | CK_1510 | CK_310),
  59         CLK(NULL,       "ck_dpll1",     &ck_dpll1,      CK_16XX | CK_1510 | CK_310),
  60         /* CK_GEN1 clocks */
  61         CLK(NULL,       "ck_dpll1out",  &ck_dpll1out.clk, CK_16XX),
  62         CLK(NULL,       "ck_sossi",     &sossi_ck,      CK_16XX),
  63         CLK(NULL,       "arm_ck",       &arm_ck,        CK_16XX | CK_1510 | CK_310),
  64         CLK(NULL,       "armper_ck",    &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
  65         CLK(NULL,       "arm_gpio_ck",  &arm_gpio_ck,   CK_1510 | CK_310),
  66         CLK(NULL,       "armxor_ck",    &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
  67         CLK(NULL,       "armtim_ck",    &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
  68         CLK(NULL,       "armwdt_ck",    &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
  69         CLK(NULL,       "arminth_ck",   &arminth_ck1510, CK_1510 | CK_310),
  70         CLK(NULL,       "arminth_ck",   &arminth_ck16xx, CK_16XX),
  71         /* CK_GEN2 clocks */
  72         CLK(NULL,       "dsp_ck",       &dsp_ck,        CK_16XX | CK_1510 | CK_310),
  73         CLK(NULL,       "dspmmu_ck",    &dspmmu_ck,     CK_16XX | CK_1510 | CK_310),
  74         CLK(NULL,       "dspper_ck",    &dspper_ck,     CK_16XX | CK_1510 | CK_310),
  75         CLK(NULL,       "dspxor_ck",    &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
  76         CLK(NULL,       "dsptim_ck",    &dsptim_ck,     CK_16XX | CK_1510 | CK_310),
  77         /* CK_GEN3 clocks */
  78         CLK(NULL,       "tc_ck",        &tc_ck.clk,     CK_16XX | CK_1510 | CK_310 | CK_730),
  79         CLK(NULL,       "tipb_ck",      &tipb_ck,       CK_1510 | CK_310),
  80         CLK(NULL,       "l3_ocpi_ck",   &l3_ocpi_ck,    CK_16XX),
  81         CLK(NULL,       "tc1_ck",       &tc1_ck,        CK_16XX),
  82         CLK(NULL,       "tc2_ck",       &tc2_ck,        CK_16XX),
  83         CLK(NULL,       "dma_ck",       &dma_ck,        CK_16XX | CK_1510 | CK_310),
  84         CLK(NULL,       "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
  85         CLK(NULL,       "api_ck",       &api_ck.clk,    CK_16XX | CK_1510 | CK_310),
  86         CLK(NULL,       "lb_ck",        &lb_ck.clk,     CK_1510 | CK_310),
  87         CLK(NULL,       "rhea1_ck",     &rhea1_ck,      CK_16XX),
  88         CLK(NULL,       "rhea2_ck",     &rhea2_ck,      CK_16XX),
  89         CLK(NULL,       "lcd_ck",       &lcd_ck_16xx,   CK_16XX | CK_730),
  90         CLK(NULL,       "lcd_ck",       &lcd_ck_1510.clk, CK_1510 | CK_310),
  91         /* ULPD clocks */
  92         CLK(NULL,       "uart1_ck",     &uart1_1510,    CK_1510 | CK_310),
  93         CLK(NULL,       "uart1_ck",     &uart1_16xx.clk, CK_16XX),
  94         CLK(NULL,       "uart2_ck",     &uart2_ck,      CK_16XX | CK_1510 | CK_310),
  95         CLK(NULL,       "uart3_ck",     &uart3_1510,    CK_1510 | CK_310),
  96         CLK(NULL,       "uart3_ck",     &uart3_16xx.clk, CK_16XX),
  97         CLK(NULL,       "usb_clko",     &usb_clko,      CK_16XX | CK_1510 | CK_310),
  98         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck1510, CK_1510 | CK_310),
  99         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck16xx, CK_16XX),
 100         CLK(NULL,       "usb_dc_ck",    &usb_dc_ck,     CK_16XX),
 101         CLK(NULL,       "mclk",         &mclk_1510,     CK_1510 | CK_310),
 102         CLK(NULL,       "mclk",         &mclk_16xx,     CK_16XX),
 103         CLK(NULL,       "bclk",         &bclk_1510,     CK_1510 | CK_310),
 104         CLK(NULL,       "bclk",         &bclk_16xx,     CK_16XX),
 105         CLK("mmci-omap.0", "mmc_ck",    &mmc1_ck,       CK_16XX | CK_1510 | CK_310),
 106         CLK("mmci-omap.1", "mmc_ck",    &mmc2_ck,       CK_16XX),
 107         /* Virtual clocks */
 108         CLK(NULL,       "mpu",          &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
 109         CLK("i2c_omap.1", "i2c_fck",    &i2c_fck,       CK_16XX | CK_1510 | CK_310),
 110         CLK("i2c_omap.1", "i2c_ick",    &i2c_ick,       CK_16XX),
 111 };
 112
 113 static int omap1_clk_enable_generic(struct clk * clk);
 114 static int omap1_clk_enable(struct clk *clk);
 115 static void omap1_clk_disable_generic(struct clk * clk);
 116 static void omap1_clk_disable(struct clk *clk);
 117
 118 __u32 arm_idlect1_mask;
 119
 120 /*-------------------------------------------------------------------------
 121  * Omap1 specific clock functions
 122  *-------------------------------------------------------------------------*/
 123
 124 static void omap1_watchdog_recalc(struct clk * clk)
 125 {
 126         clk->rate = clk->parent->rate / 14;
 127 }
 128
 129 static void omap1_uart_recalc(struct clk * clk)
 130 {
 131         unsigned int val = omap_readl(clk->enable_reg);
 132         if (val & clk->enable_bit)
 133                 clk->rate = 48000000;
 134         else
 135                 clk->rate = 12000000;
 136 }
 137
 138 static void omap1_sossi_recalc(struct clk *clk)
 139 {
 140         u32 div = omap_readl(MOD_CONF_CTRL_1);
 141
 142         div = (div >> 17) & 0x7;
 143         div++;
 144         clk->rate = clk->parent->rate / div;
 145 }
 146
 147 static int omap1_clk_enable_dsp_domain(struct clk *clk)
 148 {
 149         int retval;
 150
 151         retval = omap1_clk_enable(&api_ck.clk);
 152         if (!retval) {
 153                 retval = omap1_clk_enable_generic(clk);
 154                 omap1_clk_disable(&api_ck.clk);
 155         }
 156
 157         return retval;
 158 }
 159
 160 static void omap1_clk_disable_dsp_domain(struct clk *clk)
 161 {
 162         if (omap1_clk_enable(&api_ck.clk) == 0) {
 163                 omap1_clk_disable_generic(clk);
 164                 omap1_clk_disable(&api_ck.clk);
 165         }
 166 }
 167
 168 static const struct clkops clkops_dspck = {
 169         .enable         = &omap1_clk_enable_dsp_domain,
 170         .disable        = &omap1_clk_disable_dsp_domain,
 171 };
 172
 173 static int omap1_clk_enable_uart_functional(struct clk *clk)
 174 {
 175         int ret;
 176         struct uart_clk *uclk;
 177
 178         ret = omap1_clk_enable_generic(clk);
 179         if (ret == 0) {
 180                 /* Set smart idle acknowledgement mode */
 181                 uclk = (struct uart_clk *)clk;
 182                 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
 183                             uclk->sysc_addr);
 184         }
 185
 186         return ret;
 187 }
 188
 189 static void omap1_clk_disable_uart_functional(struct clk *clk)
 190 {
 191         struct uart_clk *uclk;
 192
 193         /* Set force idle acknowledgement mode */
 194         uclk = (struct uart_clk *)clk;
 195         omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
 196
 197         omap1_clk_disable_generic(clk);
 198 }
 199
 200 static const struct clkops clkops_uart = {
 201         .enable         = &omap1_clk_enable_uart_functional,
 202         .disable        = &omap1_clk_disable_uart_functional,
 203 };
 204
 205 static void omap1_clk_allow_idle(struct clk *clk)
 206 {
 207         struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
 208
 209         if (!(clk->flags & CLOCK_IDLE_CONTROL))
 210                 return;
 211
 212         if (iclk->no_idle_count > 0 && !(--iclk->no_idle_count))
 213                 arm_idlect1_mask |= 1 << iclk->idlect_shift;
 214 }
 215
 216 static void omap1_clk_deny_idle(struct clk *clk)
 217 {
 218         struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
 219
 220         if (!(clk->flags & CLOCK_IDLE_CONTROL))
 221                 return;
 222
 223         if (iclk->no_idle_count++ == 0)
 224                 arm_idlect1_mask &= ~(1 << iclk->idlect_shift);
 225 }
 226
 227 static __u16 verify_ckctl_value(__u16 newval)
 228 {
 229         /* This function checks for following limitations set
 230          * by the hardware (all conditions must be true):
 231          * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
 232          * ARM_CK >= TC_CK
 233          * DSP_CK >= TC_CK
 234          * DSPMMU_CK >= TC_CK
 235          *
 236          * In addition following rules are enforced:
 237          * LCD_CK <= TC_CK
 238          * ARMPER_CK <= TC_CK
 239          *
 240          * However, maximum frequencies are not checked for!
 241          */
 242         __u8 per_exp;
 243         __u8 lcd_exp;
 244         __u8 arm_exp;
 245         __u8 dsp_exp;
 246         __u8 tc_exp;
 247         __u8 dspmmu_exp;
 248
 249         per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
 250         lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
 251         arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
 252         dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
 253         tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
 254         dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
 255
 256         if (dspmmu_exp < dsp_exp)
 257                 dspmmu_exp = dsp_exp;
 258         if (dspmmu_exp > dsp_exp+1)
 259                 dspmmu_exp = dsp_exp+1;
 260         if (tc_exp < arm_exp)
 261                 tc_exp = arm_exp;
 262         if (tc_exp < dspmmu_exp)
 263                 tc_exp = dspmmu_exp;
 264         if (tc_exp > lcd_exp)
 265                 lcd_exp = tc_exp;
 266         if (tc_exp > per_exp)
 267                 per_exp = tc_exp;
 268
 269         newval &= 0xf000;
 270         newval |= per_exp << CKCTL_PERDIV_OFFSET;
 271         newval |= lcd_exp << CKCTL_LCDDIV_OFFSET;
 272         newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
 273         newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
 274         newval |= tc_exp << CKCTL_TCDIV_OFFSET;
 275         newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
 276
 277         return newval;
 278 }
 279
 280 static int calc_dsor_exp(struct clk *clk, unsigned long rate)
 281 {
 282         /* Note: If target frequency is too low, this function will return 4,
 283          * which is invalid value. Caller must check for this value and act
 284          * accordingly.
 285          *
 286          * Note: This function does not check for following limitations set
 287          * by the hardware (all conditions must be true):
 288          * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
 289          * ARM_CK >= TC_CK
 290          * DSP_CK >= TC_CK
 291          * DSPMMU_CK >= TC_CK
 292          */
 293         unsigned long realrate;
 294         struct clk * parent;
 295         unsigned  dsor_exp;
 296
 297         parent = clk->parent;
 298         if (unlikely(parent == NULL))
 299                 return -EIO;
 300
 301         realrate = parent->rate;
 302         for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
 303                 if (realrate <= rate)
 304                         break;
 305
 306                 realrate /= 2;
 307         }
 308
 309         return dsor_exp;
 310 }
 311
 312 static void omap1_ckctl_recalc(struct clk * clk)
 313 {
 314         int dsor;
 315
 316         /* Calculate divisor encoded as 2-bit exponent */
 317         dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
 318
 319         if (unlikely(clk->rate == clk->parent->rate / dsor))
 320                 return; /* No change, quick exit */
 321         clk->rate = clk->parent->rate / dsor;
 322 }
 323
 324 static void omap1_ckctl_recalc_dsp_domain(struct clk * clk)
 325 {
 326         int dsor;
 327
 328         /* Calculate divisor encoded as 2-bit exponent
 329          *
 330          * The clock control bits are in DSP domain,
 331          * so api_ck is needed for access.
 332          * Note that DSP_CKCTL virt addr = phys addr, so
 333          * we must use __raw_readw() instead of omap_readw().
 334          */
 335         omap1_clk_enable(&api_ck.clk);
 336         dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
 337         omap1_clk_disable(&api_ck.clk);
 338
 339         if (unlikely(clk->rate == clk->parent->rate / dsor))
 340                 return; /* No change, quick exit */
 341         clk->rate = clk->parent->rate / dsor;
 342 }
 343
 344 /* MPU virtual clock functions */
 345 static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
 346 {
 347         /* Find the highest supported frequency <= rate and switch to it */
 348         struct mpu_rate * ptr;
 349
 350         if (clk != &virtual_ck_mpu)
 351                 return -EINVAL;
 352
 353         for (ptr = rate_table; ptr->rate; ptr++) {
 354                 if (ptr->xtal != ck_ref.rate)
 355                         continue;
 356
 357                 /* DPLL1 cannot be reprogrammed without risking system crash */
 358                 if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate)
 359                         continue;
 360
 361                 /* Can check only after xtal frequency check */
 362                 if (ptr->rate <= rate)
 363                         break;
 364         }
 365
 366         if (!ptr->rate)
 367                 return -EINVAL;
 368
 369         /*
 370          * In most cases we should not need to reprogram DPLL.
 371          * Reprogramming the DPLL is tricky, it must be done from SRAM.
 372          * (on 730, bit 13 must always be 1)
 373          */
 374         if (cpu_is_omap730())
 375                 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
 376         else
 377                 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
 378
 379         ck_dpll1.rate = ptr->pll_rate;
 380         return 0;
 381 }
 382
 383 static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
 384 {
 385         int dsor_exp;
 386         u16 regval;
 387
 388         dsor_exp = calc_dsor_exp(clk, rate);
 389         if (dsor_exp > 3)
 390                 dsor_exp = -EINVAL;
 391         if (dsor_exp < 0)
 392                 return dsor_exp;
 393
 394         regval = __raw_readw(DSP_CKCTL);
 395         regval &= ~(3 << clk->rate_offset);
 396         regval |= dsor_exp << clk->rate_offset;
 397         __raw_writew(regval, DSP_CKCTL);
 398         clk->rate = clk->parent->rate / (1 << dsor_exp);
 399
 400         return 0;
 401 }
 402
 403 static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
 404 {
 405         int dsor_exp = calc_dsor_exp(clk, rate);
 406         if (dsor_exp < 0)
 407                 return dsor_exp;
 408         if (dsor_exp > 3)
 409                 dsor_exp = 3;
 410         return clk->parent->rate / (1 << dsor_exp);
 411 }
 412
 413 static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
 414 {
 415         int dsor_exp;
 416         u16 regval;
 417
 418         dsor_exp = calc_dsor_exp(clk, rate);
 419         if (dsor_exp > 3)
 420                 dsor_exp = -EINVAL;
 421         if (dsor_exp < 0)
 422                 return dsor_exp;
 423
 424         regval = omap_readw(ARM_CKCTL);
 425         regval &= ~(3 << clk->rate_offset);
 426         regval |= dsor_exp << clk->rate_offset;
 427         regval = verify_ckctl_value(regval);
 428         omap_writew(regval, ARM_CKCTL);
 429         clk->rate = clk->parent->rate / (1 << dsor_exp);
 430         return 0;
 431 }
 432
 433 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate)
 434 {
 435         /* Find the highest supported frequency <= rate */
 436         struct mpu_rate * ptr;
 437         long  highest_rate;
 438
 439         if (clk != &virtual_ck_mpu)
 440                 return -EINVAL;
 441
 442         highest_rate = -EINVAL;
 443
 444         for (ptr = rate_table; ptr->rate; ptr++) {
 445                 if (ptr->xtal != ck_ref.rate)
 446                         continue;
 447
 448                 highest_rate = ptr->rate;
 449
 450                 /* Can check only after xtal frequency check */
 451                 if (ptr->rate <= rate)
 452                         break;
 453         }
 454
 455         return highest_rate;
 456 }
 457
 458 static unsigned calc_ext_dsor(unsigned long rate)
 459 {
 460         unsigned dsor;
 461
 462         /* MCLK and BCLK divisor selection is not linear:
 463          * freq = 96MHz / dsor
 464          *
 465          * RATIO_SEL range: dsor <-> RATIO_SEL
 466          * 0..6: (RATIO_SEL+2) <-> (dsor-2)
 467          * 6..48:  (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
 468          * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
 469          * can not be used.
 470          */
 471         for (dsor = 2; dsor < 96; ++dsor) {
 472                 if ((dsor & 1) && dsor > 8)
 473                         continue;
 474                 if (rate >= 96000000 / dsor)
 475                         break;
 476         }
 477         return dsor;
 478 }
 479
 480 /* Only needed on 1510 */
 481 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate)
 482 {
 483         unsigned int val;
 484
 485         val = omap_readl(clk->enable_reg);
 486         if (rate == 12000000)
 487                 val &= ~(1 << clk->enable_bit);
 488         else if (rate == 48000000)
 489                 val |= (1 << clk->enable_bit);
 490         else
 491                 return -EINVAL;
 492         omap_writel(val, clk->enable_reg);
 493         clk->rate = rate;
 494
 495         return 0;
 496 }
 497
 498 /* External clock (MCLK & BCLK) functions */
 499 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate)
 500 {
 501         unsigned dsor;
 502         __u16 ratio_bits;
 503
 504         dsor = calc_ext_dsor(rate);
 505         clk->rate = 96000000 / dsor;
 506         if (dsor > 8)
 507                 ratio_bits = ((dsor - 8) / 2 + 6) << 2;
 508         else
 509                 ratio_bits = (dsor - 2) << 2;
 510
 511         ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd;
 512         omap_writew(ratio_bits, clk->enable_reg);
 513
 514         return 0;
 515 }
 516
 517 static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
 518 {
 519         u32 l;
 520         int div;
 521         unsigned long p_rate;
 522
 523         p_rate = clk->parent->rate;
 524         /* Round towards slower frequency */
 525         div = (p_rate + rate - 1) / rate;
 526         div--;
 527         if (div < 0 || div > 7)
 528                 return -EINVAL;
 529
 530         l = omap_readl(MOD_CONF_CTRL_1);
 531         l &= ~(7 << 17);
 532         l |= div << 17;
 533         omap_writel(l, MOD_CONF_CTRL_1);
 534
 535         clk->rate = p_rate / (div + 1);
 536
 537         return 0;
 538 }
 539
 540 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate)
 541 {
 542         return 96000000 / calc_ext_dsor(rate);
 543 }
 544
 545 static void omap1_init_ext_clk(struct clk * clk)
 546 {
 547         unsigned dsor;
 548         __u16 ratio_bits;
 549
 550         /* Determine current rate and ensure clock is based on 96MHz APLL */
 551         ratio_bits = omap_readw(clk->enable_reg) & ~1;
 552         omap_writew(ratio_bits, clk->enable_reg);
 553
 554         ratio_bits = (ratio_bits & 0xfc) >> 2;
 555         if (ratio_bits > 6)
 556                 dsor = (ratio_bits - 6) * 2 + 8;
 557         else
 558                 dsor = ratio_bits + 2;
 559
 560         clk-> rate = 96000000 / dsor;
 561 }
 562
 563 static int omap1_clk_enable(struct clk *clk)
 564 {
 565         int ret = 0;
 566         if (clk->usecount++ == 0) {
 567                 if (likely(clk->parent)) {
 568                         ret = omap1_clk_enable(clk->parent);
 569
 570                         if (unlikely(ret != 0)) {
 571                                 clk->usecount--;
 572                                 return ret;
 573                         }
 574
 575                         if (clk->flags & CLOCK_NO_IDLE_PARENT)
 576                                 omap1_clk_deny_idle(clk->parent);
 577                 }
 578
 579                 ret = clk->ops->enable(clk);
 580
 581                 if (unlikely(ret != 0) && clk->parent) {
 582                         omap1_clk_disable(clk->parent);
 583                         clk->usecount--;
 584                 }
 585         }
 586
 587         return ret;
 588 }
 589
 590 static void omap1_clk_disable(struct clk *clk)
 591 {
 592         if (clk->usecount > 0 && !(--clk->usecount)) {
 593                 clk->ops->disable(clk);
 594                 if (likely(clk->parent)) {
 595                         omap1_clk_disable(clk->parent);
 596                         if (clk->flags & CLOCK_NO_IDLE_PARENT)
 597                                 omap1_clk_allow_idle(clk->parent);
 598                 }
 599         }
 600 }
 601
 602 static int omap1_clk_enable_generic(struct clk *clk)
 603 {
 604         __u16 regval16;
 605         __u32 regval32;
 606
 607         if (unlikely(clk->enable_reg == NULL)) {
 608                 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
 609                        clk->name);
 610                 return -EINVAL;
 611         }
 612
 613         if (clk->flags & ENABLE_REG_32BIT) {
 614                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 615                         regval32 = __raw_readl(clk->enable_reg);
 616                         regval32 |= (1 << clk->enable_bit);
 617                         __raw_writel(regval32, clk->enable_reg);
 618                 } else {
 619                         regval32 = omap_readl(clk->enable_reg);
 620                         regval32 |= (1 << clk->enable_bit);
 621                         omap_writel(regval32, clk->enable_reg);
 622                 }
 623         } else {
 624                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 625                         regval16 = __raw_readw(clk->enable_reg);
 626                         regval16 |= (1 << clk->enable_bit);
 627                         __raw_writew(regval16, clk->enable_reg);
 628                 } else {
 629                         regval16 = omap_readw(clk->enable_reg);
 630                         regval16 |= (1 << clk->enable_bit);
 631                         omap_writew(regval16, clk->enable_reg);
 632                 }
 633         }
 634
 635         return 0;
 636 }
 637
 638 static void omap1_clk_disable_generic(struct clk *clk)
 639 {
 640         __u16 regval16;
 641         __u32 regval32;
 642
 643         if (clk->enable_reg == NULL)
 644                 return;
 645
 646         if (clk->flags & ENABLE_REG_32BIT) {
 647                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 648                         regval32 = __raw_readl(clk->enable_reg);
 649                         regval32 &= ~(1 << clk->enable_bit);
 650                         __raw_writel(regval32, clk->enable_reg);
 651                 } else {
 652                         regval32 = omap_readl(clk->enable_reg);
 653                         regval32 &= ~(1 << clk->enable_bit);
 654                         omap_writel(regval32, clk->enable_reg);
 655                 }
 656         } else {
 657                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 658                         regval16 = __raw_readw(clk->enable_reg);
 659                         regval16 &= ~(1 << clk->enable_bit);
 660                         __raw_writew(regval16, clk->enable_reg);
 661                 } else {
 662                         regval16 = omap_readw(clk->enable_reg);
 663                         regval16 &= ~(1 << clk->enable_bit);
 664                         omap_writew(regval16, clk->enable_reg);
 665                 }
 666         }
 667 }
 668
 669 static const struct clkops clkops_generic = {
 670         .enable         = &omap1_clk_enable_generic,
 671         .disable        = &omap1_clk_disable_generic,
 672 };
 673
 674 static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
 675 {
 676         if (clk->flags & RATE_FIXED)
 677                 return clk->rate;
 678
 679         if (clk->round_rate != NULL)
 680                 return clk->round_rate(clk, rate);
 681
 682         return clk->rate;
 683 }
 684
 685 static int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
 686 {
 687         int  ret = -EINVAL;
 688
 689         if (clk->set_rate)
 690                 ret = clk->set_rate(clk, rate);
 691         return ret;
 692 }
 693
 694 /*-------------------------------------------------------------------------
 695  * Omap1 clock reset and init functions
 696  *-------------------------------------------------------------------------*/
 697
 698 #ifdef CONFIG_OMAP_RESET_CLOCKS
 699
 700 static void __init omap1_clk_disable_unused(struct clk *clk)
 701 {
 702         __u32 regval32;
 703
 704         /* Clocks in the DSP domain need api_ck. Just assume bootloader
 705          * has not enabled any DSP clocks */
 706         if (clk->enable_reg == DSP_IDLECT2) {
 707                 printk(KERN_INFO "Skipping reset check for DSP domain "
 708                        "clock \"%s\"\n", clk->name);
 709                 return;
 710         }
 711
 712         /* Is the clock already disabled? */
 713         if (clk->flags & ENABLE_REG_32BIT) {
 714                 if (clk->flags & VIRTUAL_IO_ADDRESS)
 715                         regval32 = __raw_readl(clk->enable_reg);
 716                         else
 717                                 regval32 = omap_readl(clk->enable_reg);
 718         } else {
 719                 if (clk->flags & VIRTUAL_IO_ADDRESS)
 720                         regval32 = __raw_readw(clk->enable_reg);
 721                 else
 722                         regval32 = omap_readw(clk->enable_reg);
 723         }
 724
 725         if ((regval32 & (1 << clk->enable_bit)) == 0)
 726                 return;
 727
 728         /* FIXME: This clock seems to be necessary but no-one
 729          * has asked for its activation. */
 730         if (clk == &tc2_ck              /* FIX: pm.c (SRAM), CCP, Camera */
 731             || clk == &ck_dpll1out.clk  /* FIX: SoSSI, SSR */
 732             || clk == &arm_gpio_ck      /* FIX: GPIO code for 1510 */
 733                 ) {
 734                 printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
 735                        clk->name);
 736                 return;
 737         }
 738
 739         printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name);
 740         clk->ops->disable(clk);
 741         printk(" done\n");
 742 }
 743
 744 #else
 745 #define omap1_clk_disable_unused        NULL
 746 #endif
 747
 748 static struct clk_functions omap1_clk_functions = {
 749         .clk_enable             = omap1_clk_enable,
 750         .clk_disable            = omap1_clk_disable,
 751         .clk_round_rate         = omap1_clk_round_rate,
 752         .clk_set_rate           = omap1_clk_set_rate,
 753         .clk_disable_unused     = omap1_clk_disable_unused,
 754 };
 755
 756 int __init omap1_clk_init(void)
 757 {
 758         struct omap_clk *c;
 759         const struct omap_clock_config *info;
 760         int crystal_type = 0; /* Default 12 MHz */
 761         u32 reg, cpu_mask;
 762
 763 #ifdef CONFIG_DEBUG_LL
 764         /* Resets some clocks that may be left on from bootloader,
 765          * but leaves serial clocks on.
 766          */
 767         omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
 768 #endif
 769
 770         /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
 771         reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
 772         omap_writew(reg, SOFT_REQ_REG);
 773         if (!cpu_is_omap15xx())
 774                 omap_writew(0, SOFT_REQ_REG2);
 775
 776         clk_init(&omap1_clk_functions);
 777
 778         /* By default all idlect1 clocks are allowed to idle */
 779         arm_idlect1_mask = ~0;
 780
 781         cpu_mask = 0;
 782         if (cpu_is_omap16xx())
 783                 cpu_mask |= CK_16XX;
 784         if (cpu_is_omap1510())
 785                 cpu_mask |= CK_1510;
 786         if (cpu_is_omap730())
 787                 cpu_mask |= CK_730;
 788         if (cpu_is_omap310())
 789                 cpu_mask |= CK_310;
 790
 791         for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
 792                 if (c->cpu & cpu_mask) {
 793                         clkdev_add(&c->lk);
 794                         clk_register(c->lk.clk);
 795                 }
 796
 797         info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
 798         if (info != NULL) {
 799                 if (!cpu_is_omap15xx())
 800                         crystal_type = info->system_clock_type;
 801         }
 802
 803 #if defined(CONFIG_ARCH_OMAP730)
 804         ck_ref.rate = 13000000;
 805 #elif defined(CONFIG_ARCH_OMAP16XX)
 806         if (crystal_type == 2)
 807                 ck_ref.rate = 19200000;
 808 #endif
 809
 810         printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
 811                omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
 812                omap_readw(ARM_CKCTL));
 813
 814         /* We want to be in syncronous scalable mode */
 815         omap_writew(0x1000, ARM_SYSST);
 816
 817 #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
 818         /* Use values set by bootloader. Determine PLL rate and recalculate
 819          * dependent clocks as if kernel had changed PLL or divisors.
 820          */
 821         {
 822                 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
 823
 824                 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
 825                 if (pll_ctl_val & 0x10) {
 826                         /* PLL enabled, apply multiplier and divisor */
 827                         if (pll_ctl_val & 0xf80)
 828                                 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
 829                         ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
 830                 } else {
 831                         /* PLL disabled, apply bypass divisor */
 832                         switch (pll_ctl_val & 0xc) {
 833                         case 0:
 834                                 break;
 835                         case 0x4:
 836                                 ck_dpll1.rate /= 2;
 837                                 break;
 838                         default:
 839                                 ck_dpll1.rate /= 4;
 840                                 break;
 841                         }
 842                 }
 843         }
 844 #else
 845         /* Find the highest supported frequency and enable it */
 846         if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
 847                 printk(KERN_ERR "System frequencies not set. Check your config.\n");
 848                 /* Guess sane values (60MHz) */
 849                 omap_writew(0x2290, DPLL_CTL);
 850                 omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL);
 851                 ck_dpll1.rate = 60000000;
 852         }
 853 #endif
 854         propagate_rate(&ck_dpll1);
 855         /* Cache rates for clocks connected to ck_ref (not dpll1) */
 856         propagate_rate(&ck_ref);
 857         printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
 858                 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
 859                ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
 860                ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
 861                arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
 862
 863 #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
 864         /* Select slicer output as OMAP input clock */
 865         omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
 866 #endif
 867
 868         /* Amstrad Delta wants BCLK high when inactive */
 869         if (machine_is_ams_delta())
 870                 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
 871                                 (1 << SDW_MCLK_INV_BIT),
 872                                 ULPD_CLOCK_CTRL);
 873
 874         /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
 875         /* (on 730, bit 13 must not be cleared) */
 876         if (cpu_is_omap730())
 877                 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
 878         else
 879                 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
 880
 881         /* Put DSP/MPUI into reset until needed */
 882         omap_writew(0, ARM_RSTCT1);
 883         omap_writew(1, ARM_RSTCT2);
 884         omap_writew(0x400, ARM_IDLECT1);
 885
 886         /*
 887          * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
 888          * of the ARM_IDLECT2 register must be set to zero. The power-on
 889          * default value of this bit is one.
 890          */
 891         omap_writew(0x0000, ARM_IDLECT2);       /* Turn LCD clock off also */
 892
 893         /*
 894          * Only enable those clocks we will need, let the drivers
 895          * enable other clocks as necessary
 896          */
 897         clk_enable(&armper_ck.clk);
 898         clk_enable(&armxor_ck.clk);
 899         clk_enable(&armtim_ck.clk); /* This should be done by timer code */
 900
 901         if (cpu_is_omap15xx())
 902                 clk_enable(&arm_gpio_ck);
 903
 904         return 0;
 905 }