arch/arm/mach-omap1/clock.c

   1 /*
   2  *  linux/arch/arm/mach-omap1/clock.c
   3  *
   4  *  Copyright (C) 2004 - 2005 Nokia corporation
   5  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  *
   7  *  Modified to use omap shared clock framework by
   8  *  Tony Lindgren <tony@atomide.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/io.h>
  21
  22 #include <asm/mach-types.h>
  23 #include <asm/clkdev.h>
  24
  25 #include <mach/cpu.h>
  26 #include <mach/usb.h>
  27 #include <mach/clock.h>
  28 #include <mach/sram.h>
  29
  30 static const struct clkops clkops_generic;
  31 static const struct clkops clkops_uart;
  32 static const struct clkops clkops_dspck;
  33
  34 #include "clock.h"
  35
  36 static int clk_omap1_dummy_enable(struct clk *clk)
  37 {
  38         return 0;
  39 }
  40
  41 static void clk_omap1_dummy_disable(struct clk *clk)
  42 {
  43 }
  44
  45 static const struct clkops clkops_dummy = {
  46         .enable = clk_omap1_dummy_enable,
  47         .disable = clk_omap1_dummy_disable,
  48 };
  49
  50 static struct clk dummy_ck = {
  51         .name   = "dummy",
  52         .ops    = &clkops_dummy,
  53         .flags  = RATE_FIXED,
  54 };
  55
  56 struct omap_clk {
  57         u32             cpu;
  58         struct clk_lookup lk;
  59 };
  60
  61 #define CLK(dev, con, ck, cp)           \
  62         {                               \
  63                  .cpu = cp,             \
  64                 .lk = {                 \
  65                         .dev_id = dev,  \
  66                         .con_id = con,  \
  67                         .clk = ck,      \
  68                 },                      \
  69         }
  70
  71 #define CK_310  (1 << 0)
  72 #define CK_730  (1 << 1)
  73 #define CK_1510 (1 << 2)
  74 #define CK_16XX (1 << 3)
  75
  76 static struct omap_clk omap_clks[] = {
  77         /* non-ULPD clocks */
  78         CLK(NULL,       "ck_ref",       &ck_ref,        CK_16XX | CK_1510 | CK_310),
  79         CLK(NULL,       "ck_dpll1",     &ck_dpll1,      CK_16XX | CK_1510 | CK_310),
  80         /* CK_GEN1 clocks */
  81         CLK(NULL,       "ck_dpll1out",  &ck_dpll1out.clk, CK_16XX),
  82         CLK(NULL,       "ck_sossi",     &sossi_ck,      CK_16XX),
  83         CLK(NULL,       "arm_ck",       &arm_ck,        CK_16XX | CK_1510 | CK_310),
  84         CLK(NULL,       "armper_ck",    &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
  85         CLK(NULL,       "arm_gpio_ck",  &arm_gpio_ck,   CK_1510 | CK_310),
  86         CLK(NULL,       "armxor_ck",    &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
  87         CLK(NULL,       "armtim_ck",    &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
  88         CLK("omap_wdt", "fck",          &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
  89         CLK("omap_wdt", "ick",          &armper_ck.clk, CK_16XX),
  90         CLK("omap_wdt", "ick",          &dummy_ck,      CK_1510 | CK_310),
  91         CLK(NULL,       "arminth_ck",   &arminth_ck1510, CK_1510 | CK_310),
  92         CLK(NULL,       "arminth_ck",   &arminth_ck16xx, CK_16XX),
  93         /* CK_GEN2 clocks */
  94         CLK(NULL,       "dsp_ck",       &dsp_ck,        CK_16XX | CK_1510 | CK_310),
  95         CLK(NULL,       "dspmmu_ck",    &dspmmu_ck,     CK_16XX | CK_1510 | CK_310),
  96         CLK(NULL,       "dspper_ck",    &dspper_ck,     CK_16XX | CK_1510 | CK_310),
  97         CLK(NULL,       "dspxor_ck",    &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
  98         CLK(NULL,       "dsptim_ck",    &dsptim_ck,     CK_16XX | CK_1510 | CK_310),
  99         /* CK_GEN3 clocks */
 100         CLK(NULL,       "tc_ck",        &tc_ck.clk,     CK_16XX | CK_1510 | CK_310 | CK_730),
 101         CLK(NULL,       "tipb_ck",      &tipb_ck,       CK_1510 | CK_310),
 102         CLK(NULL,       "l3_ocpi_ck",   &l3_ocpi_ck,    CK_16XX),
 103         CLK(NULL,       "tc1_ck",       &tc1_ck,        CK_16XX),
 104         CLK(NULL,       "tc2_ck",       &tc2_ck,        CK_16XX),
 105         CLK(NULL,       "dma_ck",       &dma_ck,        CK_16XX | CK_1510 | CK_310),
 106         CLK(NULL,       "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
 107         CLK(NULL,       "api_ck",       &api_ck.clk,    CK_16XX | CK_1510 | CK_310),
 108         CLK(NULL,       "lb_ck",        &lb_ck.clk,     CK_1510 | CK_310),
 109         CLK(NULL,       "rhea1_ck",     &rhea1_ck,      CK_16XX),
 110         CLK(NULL,       "rhea2_ck",     &rhea2_ck,      CK_16XX),
 111         CLK(NULL,       "lcd_ck",       &lcd_ck_16xx,   CK_16XX | CK_730),
 112         CLK(NULL,       "lcd_ck",       &lcd_ck_1510.clk, CK_1510 | CK_310),
 113         /* ULPD clocks */
 114         CLK(NULL,       "uart1_ck",     &uart1_1510,    CK_1510 | CK_310),
 115         CLK(NULL,       "uart1_ck",     &uart1_16xx.clk, CK_16XX),
 116         CLK(NULL,       "uart2_ck",     &uart2_ck,      CK_16XX | CK_1510 | CK_310),
 117         CLK(NULL,       "uart3_ck",     &uart3_1510,    CK_1510 | CK_310),
 118         CLK(NULL,       "uart3_ck",     &uart3_16xx.clk, CK_16XX),
 119         CLK(NULL,       "usb_clko",     &usb_clko,      CK_16XX | CK_1510 | CK_310),
 120         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck1510, CK_1510 | CK_310),
 121         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck16xx, CK_16XX),
 122         CLK(NULL,       "usb_dc_ck",    &usb_dc_ck,     CK_16XX),
 123         CLK(NULL,       "mclk",         &mclk_1510,     CK_1510 | CK_310),
 124         CLK(NULL,       "mclk",         &mclk_16xx,     CK_16XX),
 125         CLK(NULL,       "bclk",         &bclk_1510,     CK_1510 | CK_310),
 126         CLK(NULL,       "bclk",         &bclk_16xx,     CK_16XX),
 127         CLK("mmci-omap.0", "fck",       &mmc1_ck,       CK_16XX | CK_1510 | CK_310),
 128         CLK("mmci-omap.0", "ick",       &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
 129         CLK("mmci-omap.1", "fck",       &mmc2_ck,       CK_16XX),
 130         CLK("mmci-omap.1", "ick",       &armper_ck.clk, CK_16XX),
 131         /* Virtual clocks */
 132         CLK(NULL,       "mpu",          &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
 133         CLK("i2c_omap.1", "i2c_fck",    &i2c_fck,       CK_16XX | CK_1510 | CK_310),
 134         CLK("i2c_omap.1", "i2c_ick",    &i2c_ick,       CK_16XX),
 135 };
 136
 137 static int omap1_clk_enable_generic(struct clk * clk);
 138 static int omap1_clk_enable(struct clk *clk);
 139 static void omap1_clk_disable_generic(struct clk * clk);
 140 static void omap1_clk_disable(struct clk *clk);
 141
 142 __u32 arm_idlect1_mask;
 143
 144 /*-------------------------------------------------------------------------
 145  * Omap1 specific clock functions
 146  *-------------------------------------------------------------------------*/
 147
 148 static void omap1_watchdog_recalc(struct clk * clk)
 149 {
 150         clk->rate = clk->parent->rate / 14;
 151 }
 152
 153 static void omap1_uart_recalc(struct clk * clk)
 154 {
 155         unsigned int val = omap_readl(clk->enable_reg);
 156         if (val & clk->enable_bit)
 157                 clk->rate = 48000000;
 158         else
 159                 clk->rate = 12000000;
 160 }
 161
 162 static void omap1_sossi_recalc(struct clk *clk)
 163 {
 164         u32 div = omap_readl(MOD_CONF_CTRL_1);
 165
 166         div = (div >> 17) & 0x7;
 167         div++;
 168         clk->rate = clk->parent->rate / div;
 169 }
 170
 171 static int omap1_clk_enable_dsp_domain(struct clk *clk)
 172 {
 173         int retval;
 174
 175         retval = omap1_clk_enable(&api_ck.clk);
 176         if (!retval) {
 177                 retval = omap1_clk_enable_generic(clk);
 178                 omap1_clk_disable(&api_ck.clk);
 179         }
 180
 181         return retval;
 182 }
 183
 184 static void omap1_clk_disable_dsp_domain(struct clk *clk)
 185 {
 186         if (omap1_clk_enable(&api_ck.clk) == 0) {
 187                 omap1_clk_disable_generic(clk);
 188                 omap1_clk_disable(&api_ck.clk);
 189         }
 190 }
 191
 192 static const struct clkops clkops_dspck = {
 193         .enable         = &omap1_clk_enable_dsp_domain,
 194         .disable        = &omap1_clk_disable_dsp_domain,
 195 };
 196
 197 static int omap1_clk_enable_uart_functional(struct clk *clk)
 198 {
 199         int ret;
 200         struct uart_clk *uclk;
 201
 202         ret = omap1_clk_enable_generic(clk);
 203         if (ret == 0) {
 204                 /* Set smart idle acknowledgement mode */
 205                 uclk = (struct uart_clk *)clk;
 206                 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
 207                             uclk->sysc_addr);
 208         }
 209
 210         return ret;
 211 }
 212
 213 static void omap1_clk_disable_uart_functional(struct clk *clk)
 214 {
 215         struct uart_clk *uclk;
 216
 217         /* Set force idle acknowledgement mode */
 218         uclk = (struct uart_clk *)clk;
 219         omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
 220
 221         omap1_clk_disable_generic(clk);
 222 }
 223
 224 static const struct clkops clkops_uart = {
 225         .enable         = &omap1_clk_enable_uart_functional,
 226         .disable        = &omap1_clk_disable_uart_functional,
 227 };
 228
 229 static void omap1_clk_allow_idle(struct clk *clk)
 230 {
 231         struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
 232
 233         if (!(clk->flags & CLOCK_IDLE_CONTROL))
 234                 return;
 235
 236         if (iclk->no_idle_count > 0 && !(--iclk->no_idle_count))
 237                 arm_idlect1_mask |= 1 << iclk->idlect_shift;
 238 }
 239
 240 static void omap1_clk_deny_idle(struct clk *clk)
 241 {
 242         struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
 243
 244         if (!(clk->flags & CLOCK_IDLE_CONTROL))
 245                 return;
 246
 247         if (iclk->no_idle_count++ == 0)
 248                 arm_idlect1_mask &= ~(1 << iclk->idlect_shift);
 249 }
 250
 251 static __u16 verify_ckctl_value(__u16 newval)
 252 {
 253         /* This function checks for following limitations set
 254          * by the hardware (all conditions must be true):
 255          * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
 256          * ARM_CK >= TC_CK
 257          * DSP_CK >= TC_CK
 258          * DSPMMU_CK >= TC_CK
 259          *
 260          * In addition following rules are enforced:
 261          * LCD_CK <= TC_CK
 262          * ARMPER_CK <= TC_CK
 263          *
 264          * However, maximum frequencies are not checked for!
 265          */
 266         __u8 per_exp;
 267         __u8 lcd_exp;
 268         __u8 arm_exp;
 269         __u8 dsp_exp;
 270         __u8 tc_exp;
 271         __u8 dspmmu_exp;
 272
 273         per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
 274         lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
 275         arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
 276         dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
 277         tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
 278         dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
 279
 280         if (dspmmu_exp < dsp_exp)
 281                 dspmmu_exp = dsp_exp;
 282         if (dspmmu_exp > dsp_exp+1)
 283                 dspmmu_exp = dsp_exp+1;
 284         if (tc_exp < arm_exp)
 285                 tc_exp = arm_exp;
 286         if (tc_exp < dspmmu_exp)
 287                 tc_exp = dspmmu_exp;
 288         if (tc_exp > lcd_exp)
 289                 lcd_exp = tc_exp;
 290         if (tc_exp > per_exp)
 291                 per_exp = tc_exp;
 292
 293         newval &= 0xf000;
 294         newval |= per_exp << CKCTL_PERDIV_OFFSET;
 295         newval |= lcd_exp << CKCTL_LCDDIV_OFFSET;
 296         newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
 297         newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
 298         newval |= tc_exp << CKCTL_TCDIV_OFFSET;
 299         newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
 300
 301         return newval;
 302 }
 303
 304 static int calc_dsor_exp(struct clk *clk, unsigned long rate)
 305 {
 306         /* Note: If target frequency is too low, this function will return 4,
 307          * which is invalid value. Caller must check for this value and act
 308          * accordingly.
 309          *
 310          * Note: This function does not check for following limitations set
 311          * by the hardware (all conditions must be true):
 312          * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
 313          * ARM_CK >= TC_CK
 314          * DSP_CK >= TC_CK
 315          * DSPMMU_CK >= TC_CK
 316          */
 317         unsigned long realrate;
 318         struct clk * parent;
 319         unsigned  dsor_exp;
 320
 321         parent = clk->parent;
 322         if (unlikely(parent == NULL))
 323                 return -EIO;
 324
 325         realrate = parent->rate;
 326         for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
 327                 if (realrate <= rate)
 328                         break;
 329
 330                 realrate /= 2;
 331         }
 332
 333         return dsor_exp;
 334 }
 335
 336 static void omap1_ckctl_recalc(struct clk * clk)
 337 {
 338         int dsor;
 339
 340         /* Calculate divisor encoded as 2-bit exponent */
 341         dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
 342
 343         if (unlikely(clk->rate == clk->parent->rate / dsor))
 344                 return; /* No change, quick exit */
 345         clk->rate = clk->parent->rate / dsor;
 346 }
 347
 348 static void omap1_ckctl_recalc_dsp_domain(struct clk * clk)
 349 {
 350         int dsor;
 351
 352         /* Calculate divisor encoded as 2-bit exponent
 353          *
 354          * The clock control bits are in DSP domain,
 355          * so api_ck is needed for access.
 356          * Note that DSP_CKCTL virt addr = phys addr, so
 357          * we must use __raw_readw() instead of omap_readw().
 358          */
 359         omap1_clk_enable(&api_ck.clk);
 360         dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
 361         omap1_clk_disable(&api_ck.clk);
 362
 363         if (unlikely(clk->rate == clk->parent->rate / dsor))
 364                 return; /* No change, quick exit */
 365         clk->rate = clk->parent->rate / dsor;
 366 }
 367
 368 /* MPU virtual clock functions */
 369 static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
 370 {
 371         /* Find the highest supported frequency <= rate and switch to it */
 372         struct mpu_rate * ptr;
 373
 374         if (clk != &virtual_ck_mpu)
 375                 return -EINVAL;
 376
 377         for (ptr = rate_table; ptr->rate; ptr++) {
 378                 if (ptr->xtal != ck_ref.rate)
 379                         continue;
 380
 381                 /* DPLL1 cannot be reprogrammed without risking system crash */
 382                 if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate)
 383                         continue;
 384
 385                 /* Can check only after xtal frequency check */
 386                 if (ptr->rate <= rate)
 387                         break;
 388         }
 389
 390         if (!ptr->rate)
 391                 return -EINVAL;
 392
 393         /*
 394          * In most cases we should not need to reprogram DPLL.
 395          * Reprogramming the DPLL is tricky, it must be done from SRAM.
 396          * (on 730, bit 13 must always be 1)
 397          */
 398         if (cpu_is_omap730())
 399                 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
 400         else
 401                 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
 402
 403         ck_dpll1.rate = ptr->pll_rate;
 404         return 0;
 405 }
 406
 407 static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
 408 {
 409         int dsor_exp;
 410         u16 regval;
 411
 412         dsor_exp = calc_dsor_exp(clk, rate);
 413         if (dsor_exp > 3)
 414                 dsor_exp = -EINVAL;
 415         if (dsor_exp < 0)
 416                 return dsor_exp;
 417
 418         regval = __raw_readw(DSP_CKCTL);
 419         regval &= ~(3 << clk->rate_offset);
 420         regval |= dsor_exp << clk->rate_offset;
 421         __raw_writew(regval, DSP_CKCTL);
 422         clk->rate = clk->parent->rate / (1 << dsor_exp);
 423
 424         return 0;
 425 }
 426
 427 static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
 428 {
 429         int dsor_exp = calc_dsor_exp(clk, rate);
 430         if (dsor_exp < 0)
 431                 return dsor_exp;
 432         if (dsor_exp > 3)
 433                 dsor_exp = 3;
 434         return clk->parent->rate / (1 << dsor_exp);
 435 }
 436
 437 static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
 438 {
 439         int dsor_exp;
 440         u16 regval;
 441
 442         dsor_exp = calc_dsor_exp(clk, rate);
 443         if (dsor_exp > 3)
 444                 dsor_exp = -EINVAL;
 445         if (dsor_exp < 0)
 446                 return dsor_exp;
 447
 448         regval = omap_readw(ARM_CKCTL);
 449         regval &= ~(3 << clk->rate_offset);
 450         regval |= dsor_exp << clk->rate_offset;
 451         regval = verify_ckctl_value(regval);
 452         omap_writew(regval, ARM_CKCTL);
 453         clk->rate = clk->parent->rate / (1 << dsor_exp);
 454         return 0;
 455 }
 456
 457 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate)
 458 {
 459         /* Find the highest supported frequency <= rate */
 460         struct mpu_rate * ptr;
 461         long  highest_rate;
 462
 463         if (clk != &virtual_ck_mpu)
 464                 return -EINVAL;
 465
 466         highest_rate = -EINVAL;
 467
 468         for (ptr = rate_table; ptr->rate; ptr++) {
 469                 if (ptr->xtal != ck_ref.rate)
 470                         continue;
 471
 472                 highest_rate = ptr->rate;
 473
 474                 /* Can check only after xtal frequency check */
 475                 if (ptr->rate <= rate)
 476                         break;
 477         }
 478
 479         return highest_rate;
 480 }
 481
 482 static unsigned calc_ext_dsor(unsigned long rate)
 483 {
 484         unsigned dsor;
 485
 486         /* MCLK and BCLK divisor selection is not linear:
 487          * freq = 96MHz / dsor
 488          *
 489          * RATIO_SEL range: dsor <-> RATIO_SEL
 490          * 0..6: (RATIO_SEL+2) <-> (dsor-2)
 491          * 6..48:  (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
 492          * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
 493          * can not be used.
 494          */
 495         for (dsor = 2; dsor < 96; ++dsor) {
 496                 if ((dsor & 1) && dsor > 8)
 497                         continue;
 498                 if (rate >= 96000000 / dsor)
 499                         break;
 500         }
 501         return dsor;
 502 }
 503
 504 /* Only needed on 1510 */
 505 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate)
 506 {
 507         unsigned int val;
 508
 509         val = omap_readl(clk->enable_reg);
 510         if (rate == 12000000)
 511                 val &= ~(1 << clk->enable_bit);
 512         else if (rate == 48000000)
 513                 val |= (1 << clk->enable_bit);
 514         else
 515                 return -EINVAL;
 516         omap_writel(val, clk->enable_reg);
 517         clk->rate = rate;
 518
 519         return 0;
 520 }
 521
 522 /* External clock (MCLK & BCLK) functions */
 523 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate)
 524 {
 525         unsigned dsor;
 526         __u16 ratio_bits;
 527
 528         dsor = calc_ext_dsor(rate);
 529         clk->rate = 96000000 / dsor;
 530         if (dsor > 8)
 531                 ratio_bits = ((dsor - 8) / 2 + 6) << 2;
 532         else
 533                 ratio_bits = (dsor - 2) << 2;
 534
 535         ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd;
 536         omap_writew(ratio_bits, clk->enable_reg);
 537
 538         return 0;
 539 }
 540
 541 static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
 542 {
 543         u32 l;
 544         int div;
 545         unsigned long p_rate;
 546
 547         p_rate = clk->parent->rate;
 548         /* Round towards slower frequency */
 549         div = (p_rate + rate - 1) / rate;
 550         div--;
 551         if (div < 0 || div > 7)
 552                 return -EINVAL;
 553
 554         l = omap_readl(MOD_CONF_CTRL_1);
 555         l &= ~(7 << 17);
 556         l |= div << 17;
 557         omap_writel(l, MOD_CONF_CTRL_1);
 558
 559         clk->rate = p_rate / (div + 1);
 560
 561         return 0;
 562 }
 563
 564 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate)
 565 {
 566         return 96000000 / calc_ext_dsor(rate);
 567 }
 568
 569 static void omap1_init_ext_clk(struct clk * clk)
 570 {
 571         unsigned dsor;
 572         __u16 ratio_bits;
 573
 574         /* Determine current rate and ensure clock is based on 96MHz APLL */
 575         ratio_bits = omap_readw(clk->enable_reg) & ~1;
 576         omap_writew(ratio_bits, clk->enable_reg);
 577
 578         ratio_bits = (ratio_bits & 0xfc) >> 2;
 579         if (ratio_bits > 6)
 580                 dsor = (ratio_bits - 6) * 2 + 8;
 581         else
 582                 dsor = ratio_bits + 2;
 583
 584         clk-> rate = 96000000 / dsor;
 585 }
 586
 587 static int omap1_clk_enable(struct clk *clk)
 588 {
 589         int ret = 0;
 590         if (clk->usecount++ == 0) {
 591                 if (likely(clk->parent)) {
 592                         ret = omap1_clk_enable(clk->parent);
 593
 594                         if (unlikely(ret != 0)) {
 595                                 clk->usecount--;
 596                                 return ret;
 597                         }
 598
 599                         if (clk->flags & CLOCK_NO_IDLE_PARENT)
 600                                 omap1_clk_deny_idle(clk->parent);
 601                 }
 602
 603                 ret = clk->ops->enable(clk);
 604
 605                 if (unlikely(ret != 0) && clk->parent) {
 606                         omap1_clk_disable(clk->parent);
 607                         clk->usecount--;
 608                 }
 609         }
 610
 611         return ret;
 612 }
 613
 614 static void omap1_clk_disable(struct clk *clk)
 615 {
 616         if (clk->usecount > 0 && !(--clk->usecount)) {
 617                 clk->ops->disable(clk);
 618                 if (likely(clk->parent)) {
 619                         omap1_clk_disable(clk->parent);
 620                         if (clk->flags & CLOCK_NO_IDLE_PARENT)
 621                                 omap1_clk_allow_idle(clk->parent);
 622                 }
 623         }
 624 }
 625
 626 static int omap1_clk_enable_generic(struct clk *clk)
 627 {
 628         __u16 regval16;
 629         __u32 regval32;
 630
 631         if (unlikely(clk->enable_reg == NULL)) {
 632                 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
 633                        clk->name);
 634                 return -EINVAL;
 635         }
 636
 637         if (clk->flags & ENABLE_REG_32BIT) {
 638                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 639                         regval32 = __raw_readl(clk->enable_reg);
 640                         regval32 |= (1 << clk->enable_bit);
 641                         __raw_writel(regval32, clk->enable_reg);
 642                 } else {
 643                         regval32 = omap_readl(clk->enable_reg);
 644                         regval32 |= (1 << clk->enable_bit);
 645                         omap_writel(regval32, clk->enable_reg);
 646                 }
 647         } else {
 648                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 649                         regval16 = __raw_readw(clk->enable_reg);
 650                         regval16 |= (1 << clk->enable_bit);
 651                         __raw_writew(regval16, clk->enable_reg);
 652                 } else {
 653                         regval16 = omap_readw(clk->enable_reg);
 654                         regval16 |= (1 << clk->enable_bit);
 655                         omap_writew(regval16, clk->enable_reg);
 656                 }
 657         }
 658
 659         return 0;
 660 }
 661
 662 static void omap1_clk_disable_generic(struct clk *clk)
 663 {
 664         __u16 regval16;
 665         __u32 regval32;
 666
 667         if (clk->enable_reg == NULL)
 668                 return;
 669
 670         if (clk->flags & ENABLE_REG_32BIT) {
 671                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 672                         regval32 = __raw_readl(clk->enable_reg);
 673                         regval32 &= ~(1 << clk->enable_bit);
 674                         __raw_writel(regval32, clk->enable_reg);
 675                 } else {
 676                         regval32 = omap_readl(clk->enable_reg);
 677                         regval32 &= ~(1 << clk->enable_bit);
 678                         omap_writel(regval32, clk->enable_reg);
 679                 }
 680         } else {
 681                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 682                         regval16 = __raw_readw(clk->enable_reg);
 683                         regval16 &= ~(1 << clk->enable_bit);
 684                         __raw_writew(regval16, clk->enable_reg);
 685                 } else {
 686                         regval16 = omap_readw(clk->enable_reg);
 687                         regval16 &= ~(1 << clk->enable_bit);
 688                         omap_writew(regval16, clk->enable_reg);
 689                 }
 690         }
 691 }
 692
 693 static const struct clkops clkops_generic = {
 694         .enable         = &omap1_clk_enable_generic,
 695         .disable        = &omap1_clk_disable_generic,
 696 };
 697
 698 static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
 699 {
 700         if (clk->flags & RATE_FIXED)
 701                 return clk->rate;
 702
 703         if (clk->round_rate != NULL)
 704                 return clk->round_rate(clk, rate);
 705
 706         return clk->rate;
 707 }
 708
 709 static int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
 710 {
 711         int  ret = -EINVAL;
 712
 713         if (clk->set_rate)
 714                 ret = clk->set_rate(clk, rate);
 715         return ret;
 716 }
 717
 718 /*-------------------------------------------------------------------------
 719  * Omap1 clock reset and init functions
 720  *-------------------------------------------------------------------------*/
 721
 722 #ifdef CONFIG_OMAP_RESET_CLOCKS
 723
 724 static void __init omap1_clk_disable_unused(struct clk *clk)
 725 {
 726         __u32 regval32;
 727
 728         /* Clocks in the DSP domain need api_ck. Just assume bootloader
 729          * has not enabled any DSP clocks */
 730         if (clk->enable_reg == DSP_IDLECT2) {
 731                 printk(KERN_INFO "Skipping reset check for DSP domain "
 732                        "clock \"%s\"\n", clk->name);
 733                 return;
 734         }
 735
 736         /* Is the clock already disabled? */
 737         if (clk->flags & ENABLE_REG_32BIT) {
 738                 if (clk->flags & VIRTUAL_IO_ADDRESS)
 739                         regval32 = __raw_readl(clk->enable_reg);
 740                         else
 741                                 regval32 = omap_readl(clk->enable_reg);
 742         } else {
 743                 if (clk->flags & VIRTUAL_IO_ADDRESS)
 744                         regval32 = __raw_readw(clk->enable_reg);
 745                 else
 746                         regval32 = omap_readw(clk->enable_reg);
 747         }
 748
 749         if ((regval32 & (1 << clk->enable_bit)) == 0)
 750                 return;
 751
 752         /* FIXME: This clock seems to be necessary but no-one
 753          * has asked for its activation. */
 754         if (clk == &tc2_ck              /* FIX: pm.c (SRAM), CCP, Camera */
 755             || clk == &ck_dpll1out.clk  /* FIX: SoSSI, SSR */
 756             || clk == &arm_gpio_ck      /* FIX: GPIO code for 1510 */
 757                 ) {
 758                 printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
 759                        clk->name);
 760                 return;
 761         }
 762
 763         printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name);
 764         clk->ops->disable(clk);
 765         printk(" done\n");
 766 }
 767
 768 #else
 769 #define omap1_clk_disable_unused        NULL
 770 #endif
 771
 772 static struct clk_functions omap1_clk_functions = {
 773         .clk_enable             = omap1_clk_enable,
 774         .clk_disable            = omap1_clk_disable,
 775         .clk_round_rate         = omap1_clk_round_rate,
 776         .clk_set_rate           = omap1_clk_set_rate,
 777         .clk_disable_unused     = omap1_clk_disable_unused,
 778 };
 779
 780 int __init omap1_clk_init(void)
 781 {
 782         struct omap_clk *c;
 783         const struct omap_clock_config *info;
 784         int crystal_type = 0; /* Default 12 MHz */
 785         u32 reg, cpu_mask;
 786
 787 #ifdef CONFIG_DEBUG_LL
 788         /* Resets some clocks that may be left on from bootloader,
 789          * but leaves serial clocks on.
 790          */
 791         omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
 792 #endif
 793
 794         /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
 795         reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
 796         omap_writew(reg, SOFT_REQ_REG);
 797         if (!cpu_is_omap15xx())
 798                 omap_writew(0, SOFT_REQ_REG2);
 799
 800         clk_init(&omap1_clk_functions);
 801
 802         /* By default all idlect1 clocks are allowed to idle */
 803         arm_idlect1_mask = ~0;
 804
 805         cpu_mask = 0;
 806         if (cpu_is_omap16xx())
 807                 cpu_mask |= CK_16XX;
 808         if (cpu_is_omap1510())
 809                 cpu_mask |= CK_1510;
 810         if (cpu_is_omap730())
 811                 cpu_mask |= CK_730;
 812         if (cpu_is_omap310())
 813                 cpu_mask |= CK_310;
 814
 815         for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
 816                 if (c->cpu & cpu_mask) {
 817                         clkdev_add(&c->lk);
 818                         clk_register(c->lk.clk);
 819                 }
 820
 821         info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
 822         if (info != NULL) {
 823                 if (!cpu_is_omap15xx())
 824                         crystal_type = info->system_clock_type;
 825         }
 826
 827 #if defined(CONFIG_ARCH_OMAP730)
 828         ck_ref.rate = 13000000;
 829 #elif defined(CONFIG_ARCH_OMAP16XX)
 830         if (crystal_type == 2)
 831                 ck_ref.rate = 19200000;
 832 #endif
 833
 834         printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
 835                omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
 836                omap_readw(ARM_CKCTL));
 837
 838         /* We want to be in syncronous scalable mode */
 839         omap_writew(0x1000, ARM_SYSST);
 840
 841 #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
 842         /* Use values set by bootloader. Determine PLL rate and recalculate
 843          * dependent clocks as if kernel had changed PLL or divisors.
 844          */
 845         {
 846                 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
 847
 848                 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
 849                 if (pll_ctl_val & 0x10) {
 850                         /* PLL enabled, apply multiplier and divisor */
 851                         if (pll_ctl_val & 0xf80)
 852                                 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
 853                         ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
 854                 } else {
 855                         /* PLL disabled, apply bypass divisor */
 856                         switch (pll_ctl_val & 0xc) {
 857                         case 0:
 858                                 break;
 859                         case 0x4:
 860                                 ck_dpll1.rate /= 2;
 861                                 break;
 862                         default:
 863                                 ck_dpll1.rate /= 4;
 864                                 break;
 865                         }
 866                 }
 867         }
 868 #else
 869         /* Find the highest supported frequency and enable it */
 870         if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
 871                 printk(KERN_ERR "System frequencies not set. Check your config.\n");
 872                 /* Guess sane values (60MHz) */
 873                 omap_writew(0x2290, DPLL_CTL);
 874                 omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL);
 875                 ck_dpll1.rate = 60000000;
 876         }
 877 #endif
 878         propagate_rate(&ck_dpll1);
 879         /* Cache rates for clocks connected to ck_ref (not dpll1) */
 880         propagate_rate(&ck_ref);
 881         printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
 882                 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
 883                ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
 884                ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
 885                arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
 886
 887 #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
 888         /* Select slicer output as OMAP input clock */
 889         omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
 890 #endif
 891
 892         /* Amstrad Delta wants BCLK high when inactive */
 893         if (machine_is_ams_delta())
 894                 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
 895                                 (1 << SDW_MCLK_INV_BIT),
 896                                 ULPD_CLOCK_CTRL);
 897
 898         /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
 899         /* (on 730, bit 13 must not be cleared) */
 900         if (cpu_is_omap730())
 901                 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
 902         else
 903                 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
 904
 905         /* Put DSP/MPUI into reset until needed */
 906         omap_writew(0, ARM_RSTCT1);
 907         omap_writew(1, ARM_RSTCT2);
 908         omap_writew(0x400, ARM_IDLECT1);
 909
 910         /*
 911          * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
 912          * of the ARM_IDLECT2 register must be set to zero. The power-on
 913          * default value of this bit is one.
 914          */
 915         omap_writew(0x0000, ARM_IDLECT2);       /* Turn LCD clock off also */
 916
 917         /*
 918          * Only enable those clocks we will need, let the drivers
 919          * enable other clocks as necessary
 920          */
 921         clk_enable(&armper_ck.clk);
 922         clk_enable(&armxor_ck.clk);
 923         clk_enable(&armtim_ck.clk); /* This should be done by timer code */
 924
 925         if (cpu_is_omap15xx())
 926                 clk_enable(&arm_gpio_ck);
 927
 928         return 0;
 929 }