arch/arm/mach-omap1/clock.c

   1 /*
   2  *  linux/arch/arm/mach-omap1/clock.c
   3  *
   4  *  Copyright (C) 2004 - 2005 Nokia corporation
   5  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  *
   7  *  Modified to use omap shared clock framework by
   8  *  Tony Lindgren <tony@atomide.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/io.h>
  21
  22 #include <asm/mach-types.h>
  23 #include <asm/clkdev.h>
  24
  25 #include <mach/cpu.h>
  26 #include <mach/usb.h>
  27 #include <mach/clock.h>
  28 #include <mach/sram.h>
  29
  30 static const struct clkops clkops_generic;
  31 static const struct clkops clkops_uart;
  32 static const struct clkops clkops_dspck;
  33
  34 #include "clock.h"
  35
  36 static int clk_omap1_dummy_enable(struct clk *clk)
  37 {
  38         return 0;
  39 }
  40
  41 static void clk_omap1_dummy_disable(struct clk *clk)
  42 {
  43 }
  44
  45 static const struct clkops clkops_dummy = {
  46         .enable = clk_omap1_dummy_enable,
  47         .disable = clk_omap1_dummy_disable,
  48 };
  49
  50 static struct clk dummy_ck = {
  51         .name   = "dummy",
  52         .ops    = &clkops_dummy,
  53         .flags  = RATE_FIXED,
  54 };
  55
  56 struct omap_clk {
  57         u32             cpu;
  58         struct clk_lookup lk;
  59 };
  60
  61 #define CLK(dev, con, ck, cp)           \
  62         {                               \
  63                  .cpu = cp,             \
  64                 .lk = {                 \
  65                         .dev_id = dev,  \
  66                         .con_id = con,  \
  67                         .clk = ck,      \
  68                 },                      \
  69         }
  70
  71 #define CK_310  (1 << 0)
  72 #define CK_730  (1 << 1)
  73 #define CK_1510 (1 << 2)
  74 #define CK_16XX (1 << 3)
  75
  76 static struct omap_clk omap_clks[] = {
  77         /* non-ULPD clocks */
  78         CLK(NULL,       "ck_ref",       &ck_ref,        CK_16XX | CK_1510 | CK_310),
  79         CLK(NULL,       "ck_dpll1",     &ck_dpll1,      CK_16XX | CK_1510 | CK_310),
  80         /* CK_GEN1 clocks */
  81         CLK(NULL,       "ck_dpll1out",  &ck_dpll1out.clk, CK_16XX),
  82         CLK(NULL,       "ck_sossi",     &sossi_ck,      CK_16XX),
  83         CLK(NULL,       "arm_ck",       &arm_ck,        CK_16XX | CK_1510 | CK_310),
  84         CLK(NULL,       "armper_ck",    &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
  85         CLK(NULL,       "arm_gpio_ck",  &arm_gpio_ck,   CK_1510 | CK_310),
  86         CLK(NULL,       "armxor_ck",    &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
  87         CLK(NULL,       "armtim_ck",    &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
  88         CLK("omap_wdt", "fck",          &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
  89         CLK("omap_wdt", "ick",          &armper_ck.clk, CK_16XX),
  90         CLK("omap_wdt", "ick",          &dummy_ck,      CK_1510 | CK_310),
  91         CLK(NULL,       "arminth_ck",   &arminth_ck1510, CK_1510 | CK_310),
  92         CLK(NULL,       "arminth_ck",   &arminth_ck16xx, CK_16XX),
  93         /* CK_GEN2 clocks */
  94         CLK(NULL,       "dsp_ck",       &dsp_ck,        CK_16XX | CK_1510 | CK_310),
  95         CLK(NULL,       "dspmmu_ck",    &dspmmu_ck,     CK_16XX | CK_1510 | CK_310),
  96         CLK(NULL,       "dspper_ck",    &dspper_ck,     CK_16XX | CK_1510 | CK_310),
  97         CLK(NULL,       "dspxor_ck",    &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
  98         CLK(NULL,       "dsptim_ck",    &dsptim_ck,     CK_16XX | CK_1510 | CK_310),
  99         /* CK_GEN3 clocks */
 100         CLK(NULL,       "tc_ck",        &tc_ck.clk,     CK_16XX | CK_1510 | CK_310 | CK_730),
 101         CLK(NULL,       "tipb_ck",      &tipb_ck,       CK_1510 | CK_310),
 102         CLK(NULL,       "l3_ocpi_ck",   &l3_ocpi_ck,    CK_16XX),
 103         CLK(NULL,       "tc1_ck",       &tc1_ck,        CK_16XX),
 104         CLK(NULL,       "tc2_ck",       &tc2_ck,        CK_16XX),
 105         CLK(NULL,       "dma_ck",       &dma_ck,        CK_16XX | CK_1510 | CK_310),
 106         CLK(NULL,       "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
 107         CLK(NULL,       "api_ck",       &api_ck.clk,    CK_16XX | CK_1510 | CK_310),
 108         CLK(NULL,       "lb_ck",        &lb_ck.clk,     CK_1510 | CK_310),
 109         CLK(NULL,       "rhea1_ck",     &rhea1_ck,      CK_16XX),
 110         CLK(NULL,       "rhea2_ck",     &rhea2_ck,      CK_16XX),
 111         CLK(NULL,       "lcd_ck",       &lcd_ck_16xx,   CK_16XX | CK_730),
 112         CLK(NULL,       "lcd_ck",       &lcd_ck_1510.clk, CK_1510 | CK_310),
 113         /* ULPD clocks */
 114         CLK(NULL,       "uart1_ck",     &uart1_1510,    CK_1510 | CK_310),
 115         CLK(NULL,       "uart1_ck",     &uart1_16xx.clk, CK_16XX),
 116         CLK(NULL,       "uart2_ck",     &uart2_ck,      CK_16XX | CK_1510 | CK_310),
 117         CLK(NULL,       "uart3_ck",     &uart3_1510,    CK_1510 | CK_310),
 118         CLK(NULL,       "uart3_ck",     &uart3_16xx.clk, CK_16XX),
 119         CLK(NULL,       "usb_clko",     &usb_clko,      CK_16XX | CK_1510 | CK_310),
 120         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck1510, CK_1510 | CK_310),
 121         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck16xx, CK_16XX),
 122         CLK(NULL,       "usb_dc_ck",    &usb_dc_ck,     CK_16XX),
 123         CLK(NULL,       "mclk",         &mclk_1510,     CK_1510 | CK_310),
 124         CLK(NULL,       "mclk",         &mclk_16xx,     CK_16XX),
 125         CLK(NULL,       "bclk",         &bclk_1510,     CK_1510 | CK_310),
 126         CLK(NULL,       "bclk",         &bclk_16xx,     CK_16XX),
 127         CLK("mmci-omap.0", "fck",       &mmc1_ck,       CK_16XX | CK_1510 | CK_310),
 128         CLK("mmci-omap.0", "ick",       &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
 129         CLK("mmci-omap.1", "fck",       &mmc2_ck,       CK_16XX),
 130         CLK("mmci-omap.1", "ick",       &armper_ck.clk, CK_16XX),
 131         /* Virtual clocks */
 132         CLK(NULL,       "mpu",          &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
 133         CLK("i2c_omap.1", "fck",        &i2c_fck,       CK_16XX | CK_1510 | CK_310),
 134         CLK("i2c_omap.1", "ick",        &i2c_ick,       CK_16XX),
 135         CLK("omap-mcbsp.1", "ick",      &dspper_ck,     CK_16XX),
 136         CLK("omap-mcbsp.1", "ick",      &dummy_ck,      CK_1510 | CK_310),
 137         CLK("omap-mcbsp.2", "ick",      &armper_ck.clk, CK_16XX),
 138         CLK("omap-mcbsp.2", "ick",      &dummy_ck,      CK_1510 | CK_310),
 139         CLK("omap-mcbsp.3", "ick",      &dspper_ck,     CK_16XX),
 140         CLK("omap-mcbsp.3", "ick",      &dummy_ck,      CK_1510 | CK_310),
 141         CLK("omap-mcbsp.1", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
 142         CLK("omap-mcbsp.2", "fck",      &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
 143         CLK("omap-mcbsp.3", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
 144 };
 145
 146 static int omap1_clk_enable_generic(struct clk * clk);
 147 static int omap1_clk_enable(struct clk *clk);
 148 static void omap1_clk_disable_generic(struct clk * clk);
 149 static void omap1_clk_disable(struct clk *clk);
 150
 151 __u32 arm_idlect1_mask;
 152
 153 /*-------------------------------------------------------------------------
 154  * Omap1 specific clock functions
 155  *-------------------------------------------------------------------------*/
 156
 157 static void omap1_watchdog_recalc(struct clk * clk)
 158 {
 159         clk->rate = clk->parent->rate / 14;
 160 }
 161
 162 static void omap1_uart_recalc(struct clk * clk)
 163 {
 164         unsigned int val = omap_readl(clk->enable_reg);
 165         if (val & clk->enable_bit)
 166                 clk->rate = 48000000;
 167         else
 168                 clk->rate = 12000000;
 169 }
 170
 171 static void omap1_sossi_recalc(struct clk *clk)
 172 {
 173         u32 div = omap_readl(MOD_CONF_CTRL_1);
 174
 175         div = (div >> 17) & 0x7;
 176         div++;
 177         clk->rate = clk->parent->rate / div;
 178 }
 179
 180 static int omap1_clk_enable_dsp_domain(struct clk *clk)
 181 {
 182         int retval;
 183
 184         retval = omap1_clk_enable(&api_ck.clk);
 185         if (!retval) {
 186                 retval = omap1_clk_enable_generic(clk);
 187                 omap1_clk_disable(&api_ck.clk);
 188         }
 189
 190         return retval;
 191 }
 192
 193 static void omap1_clk_disable_dsp_domain(struct clk *clk)
 194 {
 195         if (omap1_clk_enable(&api_ck.clk) == 0) {
 196                 omap1_clk_disable_generic(clk);
 197                 omap1_clk_disable(&api_ck.clk);
 198         }
 199 }
 200
 201 static const struct clkops clkops_dspck = {
 202         .enable         = &omap1_clk_enable_dsp_domain,
 203         .disable        = &omap1_clk_disable_dsp_domain,
 204 };
 205
 206 static int omap1_clk_enable_uart_functional(struct clk *clk)
 207 {
 208         int ret;
 209         struct uart_clk *uclk;
 210
 211         ret = omap1_clk_enable_generic(clk);
 212         if (ret == 0) {
 213                 /* Set smart idle acknowledgement mode */
 214                 uclk = (struct uart_clk *)clk;
 215                 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
 216                             uclk->sysc_addr);
 217         }
 218
 219         return ret;
 220 }
 221
 222 static void omap1_clk_disable_uart_functional(struct clk *clk)
 223 {
 224         struct uart_clk *uclk;
 225
 226         /* Set force idle acknowledgement mode */
 227         uclk = (struct uart_clk *)clk;
 228         omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
 229
 230         omap1_clk_disable_generic(clk);
 231 }
 232
 233 static const struct clkops clkops_uart = {
 234         .enable         = &omap1_clk_enable_uart_functional,
 235         .disable        = &omap1_clk_disable_uart_functional,
 236 };
 237
 238 static void omap1_clk_allow_idle(struct clk *clk)
 239 {
 240         struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
 241
 242         if (!(clk->flags & CLOCK_IDLE_CONTROL))
 243                 return;
 244
 245         if (iclk->no_idle_count > 0 && !(--iclk->no_idle_count))
 246                 arm_idlect1_mask |= 1 << iclk->idlect_shift;
 247 }
 248
 249 static void omap1_clk_deny_idle(struct clk *clk)
 250 {
 251         struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
 252
 253         if (!(clk->flags & CLOCK_IDLE_CONTROL))
 254                 return;
 255
 256         if (iclk->no_idle_count++ == 0)
 257                 arm_idlect1_mask &= ~(1 << iclk->idlect_shift);
 258 }
 259
 260 static __u16 verify_ckctl_value(__u16 newval)
 261 {
 262         /* This function checks for following limitations set
 263          * by the hardware (all conditions must be true):
 264          * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
 265          * ARM_CK >= TC_CK
 266          * DSP_CK >= TC_CK
 267          * DSPMMU_CK >= TC_CK
 268          *
 269          * In addition following rules are enforced:
 270          * LCD_CK <= TC_CK
 271          * ARMPER_CK <= TC_CK
 272          *
 273          * However, maximum frequencies are not checked for!
 274          */
 275         __u8 per_exp;
 276         __u8 lcd_exp;
 277         __u8 arm_exp;
 278         __u8 dsp_exp;
 279         __u8 tc_exp;
 280         __u8 dspmmu_exp;
 281
 282         per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
 283         lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
 284         arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
 285         dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
 286         tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
 287         dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
 288
 289         if (dspmmu_exp < dsp_exp)
 290                 dspmmu_exp = dsp_exp;
 291         if (dspmmu_exp > dsp_exp+1)
 292                 dspmmu_exp = dsp_exp+1;
 293         if (tc_exp < arm_exp)
 294                 tc_exp = arm_exp;
 295         if (tc_exp < dspmmu_exp)
 296                 tc_exp = dspmmu_exp;
 297         if (tc_exp > lcd_exp)
 298                 lcd_exp = tc_exp;
 299         if (tc_exp > per_exp)
 300                 per_exp = tc_exp;
 301
 302         newval &= 0xf000;
 303         newval |= per_exp << CKCTL_PERDIV_OFFSET;
 304         newval |= lcd_exp << CKCTL_LCDDIV_OFFSET;
 305         newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
 306         newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
 307         newval |= tc_exp << CKCTL_TCDIV_OFFSET;
 308         newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
 309
 310         return newval;
 311 }
 312
 313 static int calc_dsor_exp(struct clk *clk, unsigned long rate)
 314 {
 315         /* Note: If target frequency is too low, this function will return 4,
 316          * which is invalid value. Caller must check for this value and act
 317          * accordingly.
 318          *
 319          * Note: This function does not check for following limitations set
 320          * by the hardware (all conditions must be true):
 321          * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
 322          * ARM_CK >= TC_CK
 323          * DSP_CK >= TC_CK
 324          * DSPMMU_CK >= TC_CK
 325          */
 326         unsigned long realrate;
 327         struct clk * parent;
 328         unsigned  dsor_exp;
 329
 330         parent = clk->parent;
 331         if (unlikely(parent == NULL))
 332                 return -EIO;
 333
 334         realrate = parent->rate;
 335         for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
 336                 if (realrate <= rate)
 337                         break;
 338
 339                 realrate /= 2;
 340         }
 341
 342         return dsor_exp;
 343 }
 344
 345 static void omap1_ckctl_recalc(struct clk * clk)
 346 {
 347         int dsor;
 348
 349         /* Calculate divisor encoded as 2-bit exponent */
 350         dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
 351
 352         if (unlikely(clk->rate == clk->parent->rate / dsor))
 353                 return; /* No change, quick exit */
 354         clk->rate = clk->parent->rate / dsor;
 355 }
 356
 357 static void omap1_ckctl_recalc_dsp_domain(struct clk * clk)
 358 {
 359         int dsor;
 360
 361         /* Calculate divisor encoded as 2-bit exponent
 362          *
 363          * The clock control bits are in DSP domain,
 364          * so api_ck is needed for access.
 365          * Note that DSP_CKCTL virt addr = phys addr, so
 366          * we must use __raw_readw() instead of omap_readw().
 367          */
 368         omap1_clk_enable(&api_ck.clk);
 369         dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
 370         omap1_clk_disable(&api_ck.clk);
 371
 372         if (unlikely(clk->rate == clk->parent->rate / dsor))
 373                 return; /* No change, quick exit */
 374         clk->rate = clk->parent->rate / dsor;
 375 }
 376
 377 /* MPU virtual clock functions */
 378 static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
 379 {
 380         /* Find the highest supported frequency <= rate and switch to it */
 381         struct mpu_rate * ptr;
 382
 383         if (clk != &virtual_ck_mpu)
 384                 return -EINVAL;
 385
 386         for (ptr = rate_table; ptr->rate; ptr++) {
 387                 if (ptr->xtal != ck_ref.rate)
 388                         continue;
 389
 390                 /* DPLL1 cannot be reprogrammed without risking system crash */
 391                 if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate)
 392                         continue;
 393
 394                 /* Can check only after xtal frequency check */
 395                 if (ptr->rate <= rate)
 396                         break;
 397         }
 398
 399         if (!ptr->rate)
 400                 return -EINVAL;
 401
 402         /*
 403          * In most cases we should not need to reprogram DPLL.
 404          * Reprogramming the DPLL is tricky, it must be done from SRAM.
 405          * (on 730, bit 13 must always be 1)
 406          */
 407         if (cpu_is_omap730())
 408                 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
 409         else
 410                 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
 411
 412         ck_dpll1.rate = ptr->pll_rate;
 413         return 0;
 414 }
 415
 416 static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
 417 {
 418         int dsor_exp;
 419         u16 regval;
 420
 421         dsor_exp = calc_dsor_exp(clk, rate);
 422         if (dsor_exp > 3)
 423                 dsor_exp = -EINVAL;
 424         if (dsor_exp < 0)
 425                 return dsor_exp;
 426
 427         regval = __raw_readw(DSP_CKCTL);
 428         regval &= ~(3 << clk->rate_offset);
 429         regval |= dsor_exp << clk->rate_offset;
 430         __raw_writew(regval, DSP_CKCTL);
 431         clk->rate = clk->parent->rate / (1 << dsor_exp);
 432
 433         return 0;
 434 }
 435
 436 static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
 437 {
 438         int dsor_exp = calc_dsor_exp(clk, rate);
 439         if (dsor_exp < 0)
 440                 return dsor_exp;
 441         if (dsor_exp > 3)
 442                 dsor_exp = 3;
 443         return clk->parent->rate / (1 << dsor_exp);
 444 }
 445
 446 static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
 447 {
 448         int dsor_exp;
 449         u16 regval;
 450
 451         dsor_exp = calc_dsor_exp(clk, rate);
 452         if (dsor_exp > 3)
 453                 dsor_exp = -EINVAL;
 454         if (dsor_exp < 0)
 455                 return dsor_exp;
 456
 457         regval = omap_readw(ARM_CKCTL);
 458         regval &= ~(3 << clk->rate_offset);
 459         regval |= dsor_exp << clk->rate_offset;
 460         regval = verify_ckctl_value(regval);
 461         omap_writew(regval, ARM_CKCTL);
 462         clk->rate = clk->parent->rate / (1 << dsor_exp);
 463         return 0;
 464 }
 465
 466 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate)
 467 {
 468         /* Find the highest supported frequency <= rate */
 469         struct mpu_rate * ptr;
 470         long  highest_rate;
 471
 472         if (clk != &virtual_ck_mpu)
 473                 return -EINVAL;
 474
 475         highest_rate = -EINVAL;
 476
 477         for (ptr = rate_table; ptr->rate; ptr++) {
 478                 if (ptr->xtal != ck_ref.rate)
 479                         continue;
 480
 481                 highest_rate = ptr->rate;
 482
 483                 /* Can check only after xtal frequency check */
 484                 if (ptr->rate <= rate)
 485                         break;
 486         }
 487
 488         return highest_rate;
 489 }
 490
 491 static unsigned calc_ext_dsor(unsigned long rate)
 492 {
 493         unsigned dsor;
 494
 495         /* MCLK and BCLK divisor selection is not linear:
 496          * freq = 96MHz / dsor
 497          *
 498          * RATIO_SEL range: dsor <-> RATIO_SEL
 499          * 0..6: (RATIO_SEL+2) <-> (dsor-2)
 500          * 6..48:  (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
 501          * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
 502          * can not be used.
 503          */
 504         for (dsor = 2; dsor < 96; ++dsor) {
 505                 if ((dsor & 1) && dsor > 8)
 506                         continue;
 507                 if (rate >= 96000000 / dsor)
 508                         break;
 509         }
 510         return dsor;
 511 }
 512
 513 /* Only needed on 1510 */
 514 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate)
 515 {
 516         unsigned int val;
 517
 518         val = omap_readl(clk->enable_reg);
 519         if (rate == 12000000)
 520                 val &= ~(1 << clk->enable_bit);
 521         else if (rate == 48000000)
 522                 val |= (1 << clk->enable_bit);
 523         else
 524                 return -EINVAL;
 525         omap_writel(val, clk->enable_reg);
 526         clk->rate = rate;
 527
 528         return 0;
 529 }
 530
 531 /* External clock (MCLK & BCLK) functions */
 532 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate)
 533 {
 534         unsigned dsor;
 535         __u16 ratio_bits;
 536
 537         dsor = calc_ext_dsor(rate);
 538         clk->rate = 96000000 / dsor;
 539         if (dsor > 8)
 540                 ratio_bits = ((dsor - 8) / 2 + 6) << 2;
 541         else
 542                 ratio_bits = (dsor - 2) << 2;
 543
 544         ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd;
 545         omap_writew(ratio_bits, clk->enable_reg);
 546
 547         return 0;
 548 }
 549
 550 static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
 551 {
 552         u32 l;
 553         int div;
 554         unsigned long p_rate;
 555
 556         p_rate = clk->parent->rate;
 557         /* Round towards slower frequency */
 558         div = (p_rate + rate - 1) / rate;
 559         div--;
 560         if (div < 0 || div > 7)
 561                 return -EINVAL;
 562
 563         l = omap_readl(MOD_CONF_CTRL_1);
 564         l &= ~(7 << 17);
 565         l |= div << 17;
 566         omap_writel(l, MOD_CONF_CTRL_1);
 567
 568         clk->rate = p_rate / (div + 1);
 569
 570         return 0;
 571 }
 572
 573 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate)
 574 {
 575         return 96000000 / calc_ext_dsor(rate);
 576 }
 577
 578 static void omap1_init_ext_clk(struct clk * clk)
 579 {
 580         unsigned dsor;
 581         __u16 ratio_bits;
 582
 583         /* Determine current rate and ensure clock is based on 96MHz APLL */
 584         ratio_bits = omap_readw(clk->enable_reg) & ~1;
 585         omap_writew(ratio_bits, clk->enable_reg);
 586
 587         ratio_bits = (ratio_bits & 0xfc) >> 2;
 588         if (ratio_bits > 6)
 589                 dsor = (ratio_bits - 6) * 2 + 8;
 590         else
 591                 dsor = ratio_bits + 2;
 592
 593         clk-> rate = 96000000 / dsor;
 594 }
 595
 596 static int omap1_clk_enable(struct clk *clk)
 597 {
 598         int ret = 0;
 599         if (clk->usecount++ == 0) {
 600                 if (likely(clk->parent)) {
 601                         ret = omap1_clk_enable(clk->parent);
 602
 603                         if (unlikely(ret != 0)) {
 604                                 clk->usecount--;
 605                                 return ret;
 606                         }
 607
 608                         if (clk->flags & CLOCK_NO_IDLE_PARENT)
 609                                 omap1_clk_deny_idle(clk->parent);
 610                 }
 611
 612                 ret = clk->ops->enable(clk);
 613
 614                 if (unlikely(ret != 0) && clk->parent) {
 615                         omap1_clk_disable(clk->parent);
 616                         clk->usecount--;
 617                 }
 618         }
 619
 620         return ret;
 621 }
 622
 623 static void omap1_clk_disable(struct clk *clk)
 624 {
 625         if (clk->usecount > 0 && !(--clk->usecount)) {
 626                 clk->ops->disable(clk);
 627                 if (likely(clk->parent)) {
 628                         omap1_clk_disable(clk->parent);
 629                         if (clk->flags & CLOCK_NO_IDLE_PARENT)
 630                                 omap1_clk_allow_idle(clk->parent);
 631                 }
 632         }
 633 }
 634
 635 static int omap1_clk_enable_generic(struct clk *clk)
 636 {
 637         __u16 regval16;
 638         __u32 regval32;
 639
 640         if (unlikely(clk->enable_reg == NULL)) {
 641                 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
 642                        clk->name);
 643                 return -EINVAL;
 644         }
 645
 646         if (clk->flags & ENABLE_REG_32BIT) {
 647                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 648                         regval32 = __raw_readl(clk->enable_reg);
 649                         regval32 |= (1 << clk->enable_bit);
 650                         __raw_writel(regval32, clk->enable_reg);
 651                 } else {
 652                         regval32 = omap_readl(clk->enable_reg);
 653                         regval32 |= (1 << clk->enable_bit);
 654                         omap_writel(regval32, clk->enable_reg);
 655                 }
 656         } else {
 657                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 658                         regval16 = __raw_readw(clk->enable_reg);
 659                         regval16 |= (1 << clk->enable_bit);
 660                         __raw_writew(regval16, clk->enable_reg);
 661                 } else {
 662                         regval16 = omap_readw(clk->enable_reg);
 663                         regval16 |= (1 << clk->enable_bit);
 664                         omap_writew(regval16, clk->enable_reg);
 665                 }
 666         }
 667
 668         return 0;
 669 }
 670
 671 static void omap1_clk_disable_generic(struct clk *clk)
 672 {
 673         __u16 regval16;
 674         __u32 regval32;
 675
 676         if (clk->enable_reg == NULL)
 677                 return;
 678
 679         if (clk->flags & ENABLE_REG_32BIT) {
 680                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 681                         regval32 = __raw_readl(clk->enable_reg);
 682                         regval32 &= ~(1 << clk->enable_bit);
 683                         __raw_writel(regval32, clk->enable_reg);
 684                 } else {
 685                         regval32 = omap_readl(clk->enable_reg);
 686                         regval32 &= ~(1 << clk->enable_bit);
 687                         omap_writel(regval32, clk->enable_reg);
 688                 }
 689         } else {
 690                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 691                         regval16 = __raw_readw(clk->enable_reg);
 692                         regval16 &= ~(1 << clk->enable_bit);
 693                         __raw_writew(regval16, clk->enable_reg);
 694                 } else {
 695                         regval16 = omap_readw(clk->enable_reg);
 696                         regval16 &= ~(1 << clk->enable_bit);
 697                         omap_writew(regval16, clk->enable_reg);
 698                 }
 699         }
 700 }
 701
 702 static const struct clkops clkops_generic = {
 703         .enable         = &omap1_clk_enable_generic,
 704         .disable        = &omap1_clk_disable_generic,
 705 };
 706
 707 static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
 708 {
 709         if (clk->flags & RATE_FIXED)
 710                 return clk->rate;
 711
 712         if (clk->round_rate != NULL)
 713                 return clk->round_rate(clk, rate);
 714
 715         return clk->rate;
 716 }
 717
 718 static int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
 719 {
 720         int  ret = -EINVAL;
 721
 722         if (clk->set_rate)
 723                 ret = clk->set_rate(clk, rate);
 724         return ret;
 725 }
 726
 727 /*-------------------------------------------------------------------------
 728  * Omap1 clock reset and init functions
 729  *-------------------------------------------------------------------------*/
 730
 731 #ifdef CONFIG_OMAP_RESET_CLOCKS
 732
 733 static void __init omap1_clk_disable_unused(struct clk *clk)
 734 {
 735         __u32 regval32;
 736
 737         /* Clocks in the DSP domain need api_ck. Just assume bootloader
 738          * has not enabled any DSP clocks */
 739         if (clk->enable_reg == DSP_IDLECT2) {
 740                 printk(KERN_INFO "Skipping reset check for DSP domain "
 741                        "clock \"%s\"\n", clk->name);
 742                 return;
 743         }
 744
 745         /* Is the clock already disabled? */
 746         if (clk->flags & ENABLE_REG_32BIT) {
 747                 if (clk->flags & VIRTUAL_IO_ADDRESS)
 748                         regval32 = __raw_readl(clk->enable_reg);
 749                         else
 750                                 regval32 = omap_readl(clk->enable_reg);
 751         } else {
 752                 if (clk->flags & VIRTUAL_IO_ADDRESS)
 753                         regval32 = __raw_readw(clk->enable_reg);
 754                 else
 755                         regval32 = omap_readw(clk->enable_reg);
 756         }
 757
 758         if ((regval32 & (1 << clk->enable_bit)) == 0)
 759                 return;
 760
 761         /* FIXME: This clock seems to be necessary but no-one
 762          * has asked for its activation. */
 763         if (clk == &tc2_ck              /* FIX: pm.c (SRAM), CCP, Camera */
 764             || clk == &ck_dpll1out.clk  /* FIX: SoSSI, SSR */
 765             || clk == &arm_gpio_ck      /* FIX: GPIO code for 1510 */
 766                 ) {
 767                 printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
 768                        clk->name);
 769                 return;
 770         }
 771
 772         printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name);
 773         clk->ops->disable(clk);
 774         printk(" done\n");
 775 }
 776
 777 #else
 778 #define omap1_clk_disable_unused        NULL
 779 #endif
 780
 781 static struct clk_functions omap1_clk_functions = {
 782         .clk_enable             = omap1_clk_enable,
 783         .clk_disable            = omap1_clk_disable,
 784         .clk_round_rate         = omap1_clk_round_rate,
 785         .clk_set_rate           = omap1_clk_set_rate,
 786         .clk_disable_unused     = omap1_clk_disable_unused,
 787 };
 788
 789 int __init omap1_clk_init(void)
 790 {
 791         struct omap_clk *c;
 792         const struct omap_clock_config *info;
 793         int crystal_type = 0; /* Default 12 MHz */
 794         u32 reg, cpu_mask;
 795
 796 #ifdef CONFIG_DEBUG_LL
 797         /* Resets some clocks that may be left on from bootloader,
 798          * but leaves serial clocks on.
 799          */
 800         omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
 801 #endif
 802
 803         /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
 804         reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
 805         omap_writew(reg, SOFT_REQ_REG);
 806         if (!cpu_is_omap15xx())
 807                 omap_writew(0, SOFT_REQ_REG2);
 808
 809         clk_init(&omap1_clk_functions);
 810
 811         /* By default all idlect1 clocks are allowed to idle */
 812         arm_idlect1_mask = ~0;
 813
 814         cpu_mask = 0;
 815         if (cpu_is_omap16xx())
 816                 cpu_mask |= CK_16XX;
 817         if (cpu_is_omap1510())
 818                 cpu_mask |= CK_1510;
 819         if (cpu_is_omap730())
 820                 cpu_mask |= CK_730;
 821         if (cpu_is_omap310())
 822                 cpu_mask |= CK_310;
 823
 824         for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
 825                 if (c->cpu & cpu_mask) {
 826                         clkdev_add(&c->lk);
 827                         clk_register(c->lk.clk);
 828                 }
 829
 830         info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
 831         if (info != NULL) {
 832                 if (!cpu_is_omap15xx())
 833                         crystal_type = info->system_clock_type;
 834         }
 835
 836 #if defined(CONFIG_ARCH_OMAP730)
 837         ck_ref.rate = 13000000;
 838 #elif defined(CONFIG_ARCH_OMAP16XX)
 839         if (crystal_type == 2)
 840                 ck_ref.rate = 19200000;
 841 #endif
 842
 843         printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
 844                omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
 845                omap_readw(ARM_CKCTL));
 846
 847         /* We want to be in syncronous scalable mode */
 848         omap_writew(0x1000, ARM_SYSST);
 849
 850 #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
 851         /* Use values set by bootloader. Determine PLL rate and recalculate
 852          * dependent clocks as if kernel had changed PLL or divisors.
 853          */
 854         {
 855                 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
 856
 857                 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
 858                 if (pll_ctl_val & 0x10) {
 859                         /* PLL enabled, apply multiplier and divisor */
 860                         if (pll_ctl_val & 0xf80)
 861                                 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
 862                         ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
 863                 } else {
 864                         /* PLL disabled, apply bypass divisor */
 865                         switch (pll_ctl_val & 0xc) {
 866                         case 0:
 867                                 break;
 868                         case 0x4:
 869                                 ck_dpll1.rate /= 2;
 870                                 break;
 871                         default:
 872                                 ck_dpll1.rate /= 4;
 873                                 break;
 874                         }
 875                 }
 876         }
 877 #else
 878         /* Find the highest supported frequency and enable it */
 879         if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
 880                 printk(KERN_ERR "System frequencies not set. Check your config.\n");
 881                 /* Guess sane values (60MHz) */
 882                 omap_writew(0x2290, DPLL_CTL);
 883                 omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL);
 884                 ck_dpll1.rate = 60000000;
 885         }
 886 #endif
 887         propagate_rate(&ck_dpll1);
 888         /* Cache rates for clocks connected to ck_ref (not dpll1) */
 889         propagate_rate(&ck_ref);
 890         printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
 891                 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
 892                ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
 893                ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
 894                arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
 895
 896 #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
 897         /* Select slicer output as OMAP input clock */
 898         omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
 899 #endif
 900
 901         /* Amstrad Delta wants BCLK high when inactive */
 902         if (machine_is_ams_delta())
 903                 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
 904                                 (1 << SDW_MCLK_INV_BIT),
 905                                 ULPD_CLOCK_CTRL);
 906
 907         /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
 908         /* (on 730, bit 13 must not be cleared) */
 909         if (cpu_is_omap730())
 910                 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
 911         else
 912                 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
 913
 914         /* Put DSP/MPUI into reset until needed */
 915         omap_writew(0, ARM_RSTCT1);
 916         omap_writew(1, ARM_RSTCT2);
 917         omap_writew(0x400, ARM_IDLECT1);
 918
 919         /*
 920          * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
 921          * of the ARM_IDLECT2 register must be set to zero. The power-on
 922          * default value of this bit is one.
 923          */
 924         omap_writew(0x0000, ARM_IDLECT2);       /* Turn LCD clock off also */
 925
 926         /*
 927          * Only enable those clocks we will need, let the drivers
 928          * enable other clocks as necessary
 929          */
 930         clk_enable(&armper_ck.clk);
 931         clk_enable(&armxor_ck.clk);
 932         clk_enable(&armtim_ck.clk); /* This should be done by timer code */
 933
 934         if (cpu_is_omap15xx())
 935                 clk_enable(&arm_gpio_ck);
 936
 937         return 0;
 938 }