2 * linux/arch/arm/mach-omap1/clock.c
4 * Copyright (C) 2004 - 2005 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
7 * Modified to use omap shared clock framework by
8 * Tony Lindgren <tony@atomide.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
22 #include <asm/mach-types.h>
26 #include <mach/clock.h>
27 #include <mach/sram.h>
29 static const struct clkops clkops_generic;
30 static const struct clkops clkops_uart;
31 static const struct clkops clkops_dspck;
35 static int omap1_clk_enable_generic(struct clk * clk);
36 static int omap1_clk_enable(struct clk *clk);
37 static void omap1_clk_disable_generic(struct clk * clk);
38 static void omap1_clk_disable(struct clk *clk);
40 __u32 arm_idlect1_mask;
42 /*-------------------------------------------------------------------------
43 * Omap1 specific clock functions
44 *-------------------------------------------------------------------------*/
46 static void omap1_watchdog_recalc(struct clk * clk)
48 clk->rate = clk->parent->rate / 14;
51 static void omap1_uart_recalc(struct clk * clk)
53 unsigned int val = omap_readl(clk->enable_reg);
54 if (val & clk->enable_bit)
60 static void omap1_sossi_recalc(struct clk *clk)
62 u32 div = omap_readl(MOD_CONF_CTRL_1);
64 div = (div >> 17) & 0x7;
66 clk->rate = clk->parent->rate / div;
69 static int omap1_clk_enable_dsp_domain(struct clk *clk)
73 retval = omap1_clk_enable(&api_ck.clk);
75 retval = omap1_clk_enable_generic(clk);
76 omap1_clk_disable(&api_ck.clk);
82 static void omap1_clk_disable_dsp_domain(struct clk *clk)
84 if (omap1_clk_enable(&api_ck.clk) == 0) {
85 omap1_clk_disable_generic(clk);
86 omap1_clk_disable(&api_ck.clk);
90 static const struct clkops clkops_dspck = {
91 .enable = &omap1_clk_enable_dsp_domain,
92 .disable = &omap1_clk_disable_dsp_domain,
95 static int omap1_clk_enable_uart_functional(struct clk *clk)
98 struct uart_clk *uclk;
100 ret = omap1_clk_enable_generic(clk);
102 /* Set smart idle acknowledgement mode */
103 uclk = (struct uart_clk *)clk;
104 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
111 static void omap1_clk_disable_uart_functional(struct clk *clk)
113 struct uart_clk *uclk;
115 /* Set force idle acknowledgement mode */
116 uclk = (struct uart_clk *)clk;
117 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
119 omap1_clk_disable_generic(clk);
122 static const struct clkops clkops_uart = {
123 .enable = &omap1_clk_enable_uart_functional,
124 .disable = &omap1_clk_disable_uart_functional,
127 static void omap1_clk_allow_idle(struct clk *clk)
129 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
131 if (!(clk->flags & CLOCK_IDLE_CONTROL))
134 if (iclk->no_idle_count > 0 && !(--iclk->no_idle_count))
135 arm_idlect1_mask |= 1 << iclk->idlect_shift;
138 static void omap1_clk_deny_idle(struct clk *clk)
140 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
142 if (!(clk->flags & CLOCK_IDLE_CONTROL))
145 if (iclk->no_idle_count++ == 0)
146 arm_idlect1_mask &= ~(1 << iclk->idlect_shift);
149 static __u16 verify_ckctl_value(__u16 newval)
151 /* This function checks for following limitations set
152 * by the hardware (all conditions must be true):
153 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
158 * In addition following rules are enforced:
162 * However, maximum frequencies are not checked for!
171 per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
172 lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
173 arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
174 dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
175 tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
176 dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
178 if (dspmmu_exp < dsp_exp)
179 dspmmu_exp = dsp_exp;
180 if (dspmmu_exp > dsp_exp+1)
181 dspmmu_exp = dsp_exp+1;
182 if (tc_exp < arm_exp)
184 if (tc_exp < dspmmu_exp)
186 if (tc_exp > lcd_exp)
188 if (tc_exp > per_exp)
192 newval |= per_exp << CKCTL_PERDIV_OFFSET;
193 newval |= lcd_exp << CKCTL_LCDDIV_OFFSET;
194 newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
195 newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
196 newval |= tc_exp << CKCTL_TCDIV_OFFSET;
197 newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
202 static int calc_dsor_exp(struct clk *clk, unsigned long rate)
204 /* Note: If target frequency is too low, this function will return 4,
205 * which is invalid value. Caller must check for this value and act
208 * Note: This function does not check for following limitations set
209 * by the hardware (all conditions must be true):
210 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
215 unsigned long realrate;
219 if (unlikely(!(clk->flags & RATE_CKCTL)))
222 parent = clk->parent;
223 if (unlikely(parent == NULL))
226 realrate = parent->rate;
227 for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
228 if (realrate <= rate)
237 static void omap1_ckctl_recalc(struct clk * clk)
241 /* Calculate divisor encoded as 2-bit exponent */
242 dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
244 if (unlikely(clk->rate == clk->parent->rate / dsor))
245 return; /* No change, quick exit */
246 clk->rate = clk->parent->rate / dsor;
248 if (unlikely(clk->flags & RATE_PROPAGATES))
252 static void omap1_ckctl_recalc_dsp_domain(struct clk * clk)
256 /* Calculate divisor encoded as 2-bit exponent
258 * The clock control bits are in DSP domain,
259 * so api_ck is needed for access.
260 * Note that DSP_CKCTL virt addr = phys addr, so
261 * we must use __raw_readw() instead of omap_readw().
263 omap1_clk_enable(&api_ck.clk);
264 dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
265 omap1_clk_disable(&api_ck.clk);
267 if (unlikely(clk->rate == clk->parent->rate / dsor))
268 return; /* No change, quick exit */
269 clk->rate = clk->parent->rate / dsor;
271 if (unlikely(clk->flags & RATE_PROPAGATES))
275 /* MPU virtual clock functions */
276 static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
278 /* Find the highest supported frequency <= rate and switch to it */
279 struct mpu_rate * ptr;
281 if (clk != &virtual_ck_mpu)
284 for (ptr = rate_table; ptr->rate; ptr++) {
285 if (ptr->xtal != ck_ref.rate)
288 /* DPLL1 cannot be reprogrammed without risking system crash */
289 if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate)
292 /* Can check only after xtal frequency check */
293 if (ptr->rate <= rate)
301 * In most cases we should not need to reprogram DPLL.
302 * Reprogramming the DPLL is tricky, it must be done from SRAM.
303 * (on 730, bit 13 must always be 1)
305 if (cpu_is_omap730())
306 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
308 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
310 ck_dpll1.rate = ptr->pll_rate;
311 propagate_rate(&ck_dpll1);
315 static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
321 if (clk->flags & RATE_CKCTL) {
322 dsor_exp = calc_dsor_exp(clk, rate);
328 regval = __raw_readw(DSP_CKCTL);
329 regval &= ~(3 << clk->rate_offset);
330 regval |= dsor_exp << clk->rate_offset;
331 __raw_writew(regval, DSP_CKCTL);
332 clk->rate = clk->parent->rate / (1 << dsor_exp);
336 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
342 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate)
344 /* Find the highest supported frequency <= rate */
345 struct mpu_rate * ptr;
348 if (clk != &virtual_ck_mpu)
351 highest_rate = -EINVAL;
353 for (ptr = rate_table; ptr->rate; ptr++) {
354 if (ptr->xtal != ck_ref.rate)
357 highest_rate = ptr->rate;
359 /* Can check only after xtal frequency check */
360 if (ptr->rate <= rate)
367 static unsigned calc_ext_dsor(unsigned long rate)
371 /* MCLK and BCLK divisor selection is not linear:
372 * freq = 96MHz / dsor
374 * RATIO_SEL range: dsor <-> RATIO_SEL
375 * 0..6: (RATIO_SEL+2) <-> (dsor-2)
376 * 6..48: (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
377 * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
380 for (dsor = 2; dsor < 96; ++dsor) {
381 if ((dsor & 1) && dsor > 8)
383 if (rate >= 96000000 / dsor)
389 /* Only needed on 1510 */
390 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate)
394 val = omap_readl(clk->enable_reg);
395 if (rate == 12000000)
396 val &= ~(1 << clk->enable_bit);
397 else if (rate == 48000000)
398 val |= (1 << clk->enable_bit);
401 omap_writel(val, clk->enable_reg);
407 /* External clock (MCLK & BCLK) functions */
408 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate)
413 dsor = calc_ext_dsor(rate);
414 clk->rate = 96000000 / dsor;
416 ratio_bits = ((dsor - 8) / 2 + 6) << 2;
418 ratio_bits = (dsor - 2) << 2;
420 ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd;
421 omap_writew(ratio_bits, clk->enable_reg);
426 static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
430 unsigned long p_rate;
432 p_rate = clk->parent->rate;
433 /* Round towards slower frequency */
434 div = (p_rate + rate - 1) / rate;
436 if (div < 0 || div > 7)
439 l = omap_readl(MOD_CONF_CTRL_1);
442 omap_writel(l, MOD_CONF_CTRL_1);
444 clk->rate = p_rate / (div + 1);
445 if (unlikely(clk->flags & RATE_PROPAGATES))
451 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate)
453 return 96000000 / calc_ext_dsor(rate);
456 static void omap1_init_ext_clk(struct clk * clk)
461 /* Determine current rate and ensure clock is based on 96MHz APLL */
462 ratio_bits = omap_readw(clk->enable_reg) & ~1;
463 omap_writew(ratio_bits, clk->enable_reg);
465 ratio_bits = (ratio_bits & 0xfc) >> 2;
467 dsor = (ratio_bits - 6) * 2 + 8;
469 dsor = ratio_bits + 2;
471 clk-> rate = 96000000 / dsor;
474 static int omap1_clk_enable(struct clk *clk)
477 if (clk->usecount++ == 0) {
478 if (likely(clk->parent)) {
479 ret = omap1_clk_enable(clk->parent);
481 if (unlikely(ret != 0)) {
486 if (clk->flags & CLOCK_NO_IDLE_PARENT)
487 omap1_clk_deny_idle(clk->parent);
490 ret = clk->ops->enable(clk);
492 if (unlikely(ret != 0) && clk->parent) {
493 omap1_clk_disable(clk->parent);
501 static void omap1_clk_disable(struct clk *clk)
503 if (clk->usecount > 0 && !(--clk->usecount)) {
504 clk->ops->disable(clk);
505 if (likely(clk->parent)) {
506 omap1_clk_disable(clk->parent);
507 if (clk->flags & CLOCK_NO_IDLE_PARENT)
508 omap1_clk_allow_idle(clk->parent);
513 static int omap1_clk_enable_generic(struct clk *clk)
518 if (clk->flags & ALWAYS_ENABLED)
521 if (unlikely(clk->enable_reg == NULL)) {
522 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
527 if (clk->flags & ENABLE_REG_32BIT) {
528 if (clk->flags & VIRTUAL_IO_ADDRESS) {
529 regval32 = __raw_readl(clk->enable_reg);
530 regval32 |= (1 << clk->enable_bit);
531 __raw_writel(regval32, clk->enable_reg);
533 regval32 = omap_readl(clk->enable_reg);
534 regval32 |= (1 << clk->enable_bit);
535 omap_writel(regval32, clk->enable_reg);
538 if (clk->flags & VIRTUAL_IO_ADDRESS) {
539 regval16 = __raw_readw(clk->enable_reg);
540 regval16 |= (1 << clk->enable_bit);
541 __raw_writew(regval16, clk->enable_reg);
543 regval16 = omap_readw(clk->enable_reg);
544 regval16 |= (1 << clk->enable_bit);
545 omap_writew(regval16, clk->enable_reg);
552 static void omap1_clk_disable_generic(struct clk *clk)
557 if (clk->enable_reg == NULL)
560 if (clk->flags & ENABLE_REG_32BIT) {
561 if (clk->flags & VIRTUAL_IO_ADDRESS) {
562 regval32 = __raw_readl(clk->enable_reg);
563 regval32 &= ~(1 << clk->enable_bit);
564 __raw_writel(regval32, clk->enable_reg);
566 regval32 = omap_readl(clk->enable_reg);
567 regval32 &= ~(1 << clk->enable_bit);
568 omap_writel(regval32, clk->enable_reg);
571 if (clk->flags & VIRTUAL_IO_ADDRESS) {
572 regval16 = __raw_readw(clk->enable_reg);
573 regval16 &= ~(1 << clk->enable_bit);
574 __raw_writew(regval16, clk->enable_reg);
576 regval16 = omap_readw(clk->enable_reg);
577 regval16 &= ~(1 << clk->enable_bit);
578 omap_writew(regval16, clk->enable_reg);
583 static const struct clkops clkops_generic = {
584 .enable = &omap1_clk_enable_generic,
585 .disable = &omap1_clk_disable_generic,
588 static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
592 if (clk->flags & RATE_FIXED)
595 if (clk->flags & RATE_CKCTL) {
596 dsor_exp = calc_dsor_exp(clk, rate);
601 return clk->parent->rate / (1 << dsor_exp);
604 if (clk->round_rate != NULL)
605 return clk->round_rate(clk, rate);
610 static int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
617 ret = clk->set_rate(clk, rate);
618 else if (clk->flags & RATE_CKCTL) {
619 dsor_exp = calc_dsor_exp(clk, rate);
625 regval = omap_readw(ARM_CKCTL);
626 regval &= ~(3 << clk->rate_offset);
627 regval |= dsor_exp << clk->rate_offset;
628 regval = verify_ckctl_value(regval);
629 omap_writew(regval, ARM_CKCTL);
630 clk->rate = clk->parent->rate / (1 << dsor_exp);
634 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
640 /*-------------------------------------------------------------------------
641 * Omap1 clock reset and init functions
642 *-------------------------------------------------------------------------*/
644 #ifdef CONFIG_OMAP_RESET_CLOCKS
646 static void __init omap1_clk_disable_unused(struct clk *clk)
650 /* Clocks in the DSP domain need api_ck. Just assume bootloader
651 * has not enabled any DSP clocks */
652 if (clk->enable_reg == DSP_IDLECT2) {
653 printk(KERN_INFO "Skipping reset check for DSP domain "
654 "clock \"%s\"\n", clk->name);
658 /* Is the clock already disabled? */
659 if (clk->flags & ENABLE_REG_32BIT) {
660 if (clk->flags & VIRTUAL_IO_ADDRESS)
661 regval32 = __raw_readl(clk->enable_reg);
663 regval32 = omap_readl(clk->enable_reg);
665 if (clk->flags & VIRTUAL_IO_ADDRESS)
666 regval32 = __raw_readw(clk->enable_reg);
668 regval32 = omap_readw(clk->enable_reg);
671 if ((regval32 & (1 << clk->enable_bit)) == 0)
674 /* FIXME: This clock seems to be necessary but no-one
675 * has asked for its activation. */
676 if (clk == &tc2_ck /* FIX: pm.c (SRAM), CCP, Camera */
677 || clk == &ck_dpll1out.clk /* FIX: SoSSI, SSR */
678 || clk == &arm_gpio_ck /* FIX: GPIO code for 1510 */
680 printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
685 printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name);
686 clk->ops->disable(clk);
691 #define omap1_clk_disable_unused NULL
694 static struct clk_functions omap1_clk_functions = {
695 .clk_enable = omap1_clk_enable,
696 .clk_disable = omap1_clk_disable,
697 .clk_round_rate = omap1_clk_round_rate,
698 .clk_set_rate = omap1_clk_set_rate,
699 .clk_disable_unused = omap1_clk_disable_unused,
702 int __init omap1_clk_init(void)
705 const struct omap_clock_config *info;
706 int crystal_type = 0; /* Default 12 MHz */
709 #ifdef CONFIG_DEBUG_LL
710 /* Resets some clocks that may be left on from bootloader,
711 * but leaves serial clocks on.
713 omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
716 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
717 reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
718 omap_writew(reg, SOFT_REQ_REG);
719 if (!cpu_is_omap15xx())
720 omap_writew(0, SOFT_REQ_REG2);
722 clk_init(&omap1_clk_functions);
724 /* By default all idlect1 clocks are allowed to idle */
725 arm_idlect1_mask = ~0;
727 for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) {
728 if (((*clkp)->flags &CLOCK_IN_OMAP1510) && cpu_is_omap1510()) {
733 if (((*clkp)->flags &CLOCK_IN_OMAP16XX) && cpu_is_omap16xx()) {
738 if (((*clkp)->flags &CLOCK_IN_OMAP730) && cpu_is_omap730()) {
743 if (((*clkp)->flags &CLOCK_IN_OMAP310) && cpu_is_omap310()) {
749 info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
751 if (!cpu_is_omap15xx())
752 crystal_type = info->system_clock_type;
755 #if defined(CONFIG_ARCH_OMAP730)
756 ck_ref.rate = 13000000;
757 #elif defined(CONFIG_ARCH_OMAP16XX)
758 if (crystal_type == 2)
759 ck_ref.rate = 19200000;
762 printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
763 omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
764 omap_readw(ARM_CKCTL));
766 /* We want to be in syncronous scalable mode */
767 omap_writew(0x1000, ARM_SYSST);
769 #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
770 /* Use values set by bootloader. Determine PLL rate and recalculate
771 * dependent clocks as if kernel had changed PLL or divisors.
774 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
776 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
777 if (pll_ctl_val & 0x10) {
778 /* PLL enabled, apply multiplier and divisor */
779 if (pll_ctl_val & 0xf80)
780 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
781 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
783 /* PLL disabled, apply bypass divisor */
784 switch (pll_ctl_val & 0xc) {
796 propagate_rate(&ck_dpll1);
798 /* Find the highest supported frequency and enable it */
799 if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
800 printk(KERN_ERR "System frequencies not set. Check your config.\n");
801 /* Guess sane values (60MHz) */
802 omap_writew(0x2290, DPLL_CTL);
803 omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL);
804 ck_dpll1.rate = 60000000;
805 propagate_rate(&ck_dpll1);
808 /* Cache rates for clocks connected to ck_ref (not dpll1) */
809 propagate_rate(&ck_ref);
810 printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
811 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
812 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
813 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
814 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
816 #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
817 /* Select slicer output as OMAP input clock */
818 omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
821 /* Amstrad Delta wants BCLK high when inactive */
822 if (machine_is_ams_delta())
823 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
824 (1 << SDW_MCLK_INV_BIT),
827 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
828 /* (on 730, bit 13 must not be cleared) */
829 if (cpu_is_omap730())
830 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
832 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
834 /* Put DSP/MPUI into reset until needed */
835 omap_writew(0, ARM_RSTCT1);
836 omap_writew(1, ARM_RSTCT2);
837 omap_writew(0x400, ARM_IDLECT1);
840 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
841 * of the ARM_IDLECT2 register must be set to zero. The power-on
842 * default value of this bit is one.
844 omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */
847 * Only enable those clocks we will need, let the drivers
848 * enable other clocks as necessary
850 clk_enable(&armper_ck.clk);
851 clk_enable(&armxor_ck.clk);
852 clk_enable(&armtim_ck.clk); /* This should be done by timer code */
854 if (cpu_is_omap15xx())
855 clk_enable(&arm_gpio_ck);