arch/arm/mach-ns9xxx/board-a9m9750dev.c

   1 /*
   2  * arch/arm/mach-ns9xxx/board-a9m9750dev.c
   3  *
   4  * Copyright (C) 2006,2007 by Digi International Inc.
   5  * All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  */
  11 #include <linux/platform_device.h>
  12 #include <linux/serial_8250.h>
  13 #include <linux/irq.h>
  14
  15 #include <asm/mach/map.h>
  16
  17 #include <asm/arch-ns9xxx/board.h>
  18 #include <asm/arch-ns9xxx/regs-sys.h>
  19 #include <asm/arch-ns9xxx/regs-mem.h>
  20 #include <asm/arch-ns9xxx/regs-bbu.h>
  21 #include <asm/arch-ns9xxx/regs-board-a9m9750dev.h>
  22
  23 #include "board-a9m9750dev.h"
  24
  25 static struct map_desc board_a9m9750dev_io_desc[] __initdata = {
  26         { /* FPGA on CS0 */
  27                 .virtual = io_p2v(NS9XXX_CSxSTAT_PHYS(0)),
  28                 .pfn = __phys_to_pfn(NS9XXX_CSxSTAT_PHYS(0)),
  29                 .length = NS9XXX_CS0STAT_LENGTH,
  30                 .type = MT_DEVICE,
  31         },
  32 };
  33
  34 void __init board_a9m9750dev_map_io(void)
  35 {
  36         iotable_init(board_a9m9750dev_io_desc,
  37                      ARRAY_SIZE(board_a9m9750dev_io_desc));
  38 }
  39
  40 static void a9m9750dev_fpga_ack_irq(unsigned int irq)
  41 {
  42         /* nothing */
  43 }
  44
  45 static void a9m9750dev_fpga_mask_irq(unsigned int irq)
  46 {
  47         FPGA_IER &= ~(1 << (irq - FPGA_IRQ(0)));
  48 }
  49
  50 static void a9m9750dev_fpga_maskack_irq(unsigned int irq)
  51 {
  52         a9m9750dev_fpga_mask_irq(irq);
  53         a9m9750dev_fpga_ack_irq(irq);
  54 }
  55
  56 static void a9m9750dev_fpga_unmask_irq(unsigned int irq)
  57 {
  58         FPGA_IER |= 1 << (irq - FPGA_IRQ(0));
  59 }
  60
  61 static struct irq_chip a9m9750dev_fpga_chip = {
  62         .ack            = a9m9750dev_fpga_ack_irq,
  63         .mask           = a9m9750dev_fpga_mask_irq,
  64         .mask_ack       = a9m9750dev_fpga_maskack_irq,
  65         .unmask         = a9m9750dev_fpga_unmask_irq,
  66 };
  67
  68 static void a9m9750dev_fpga_demux_handler(unsigned int irq,
  69                 struct irq_desc *desc)
  70 {
  71         int stat = FPGA_ISR;
  72
  73         desc->chip->mask_ack(irq);
  74
  75         while (stat != 0) {
  76                 int irqno = fls(stat) - 1;
  77                 struct irq_desc *fpgadesc;
  78
  79                 stat &= ~(1 << irqno);
  80
  81                 fpgadesc = irq_desc + FPGA_IRQ(irqno);
  82
  83                 desc_handle_irq(FPGA_IRQ(irqno), fpgadesc);
  84         }
  85
  86         desc->chip->unmask(irq);
  87 }
  88
  89 void __init board_a9m9750dev_init_irq(void)
  90 {
  91         u32 reg;
  92         int i;
  93
  94         /*
  95          * configure gpio for IRQ_EXT2
  96          * use GPIO 11, because GPIO 32 is used for the LCD
  97          */
  98         /* XXX: proper GPIO handling */
  99         BBU_GCONFb1(1) &= ~0x2000;
 100
 101         for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) {
 102                 set_irq_chip(i, &a9m9750dev_fpga_chip);
 103                 set_irq_handler(i, handle_level_irq);
 104                 set_irq_flags(i, IRQF_VALID);
 105         }
 106
 107         /* IRQ_EXT2: level sensitive + active low */
 108         reg = SYS_EIC(2);
 109         REGSET(reg, SYS_EIC, PLTY, AL);
 110         REGSET(reg, SYS_EIC, LVEDG, LEVEL);
 111         SYS_EIC(2) = reg;
 112
 113         set_irq_chained_handler(IRQ_EXT2,
 114                         a9m9750dev_fpga_demux_handler);
 115 }
 116
 117 static struct plat_serial8250_port board_a9m9750dev_serial8250_port[] = {
 118         {
 119                 .iobase         = FPGA_UARTA_BASE,
 120                 .membase        = (unsigned char*)FPGA_UARTA_BASE,
 121                 .mapbase        = FPGA_UARTA_BASE,
 122                 .irq            = IRQ_FPGA_UARTA,
 123                 .iotype         = UPIO_MEM,
 124                 .uartclk        = 18432000,
 125                 .regshift       = 0,
 126                 .flags          = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
 127         }, {
 128                 .iobase         = FPGA_UARTB_BASE,
 129                 .membase        = (unsigned char*)FPGA_UARTB_BASE,
 130                 .mapbase        = FPGA_UARTB_BASE,
 131                 .irq            = IRQ_FPGA_UARTB,
 132                 .iotype         = UPIO_MEM,
 133                 .uartclk        = 18432000,
 134                 .regshift       = 0,
 135                 .flags          = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
 136         }, {
 137                 .iobase         = FPGA_UARTC_BASE,
 138                 .membase        = (unsigned char*)FPGA_UARTC_BASE,
 139                 .mapbase        = FPGA_UARTC_BASE,
 140                 .irq            = IRQ_FPGA_UARTC,
 141                 .iotype         = UPIO_MEM,
 142                 .uartclk        = 18432000,
 143                 .regshift       = 0,
 144                 .flags          = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
 145         }, {
 146                 .iobase         = FPGA_UARTD_BASE,
 147                 .membase        = (unsigned char*)FPGA_UARTD_BASE,
 148                 .mapbase        = FPGA_UARTD_BASE,
 149                 .irq            = IRQ_FPGA_UARTD,
 150                 .iotype         = UPIO_MEM,
 151                 .uartclk        = 18432000,
 152                 .regshift       = 0,
 153                 .flags          = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
 154         }, {
 155                 /* end marker */
 156         },
 157 };
 158
 159 static struct platform_device board_a9m9750dev_serial_device = {
 160         .name = "serial8250",
 161         .dev = {
 162                 .platform_data = board_a9m9750dev_serial8250_port,
 163         },
 164 };
 165
 166 static struct platform_device *board_a9m9750dev_devices[] __initdata = {
 167         &board_a9m9750dev_serial_device,
 168 };
 169
 170 void __init board_a9m9750dev_init_machine(void)
 171 {
 172         u32 reg;
 173
 174         /* setup static CS0: memory base ... */
 175         REGSETIM(SYS_SMCSSMB(0), SYS_SMCSSMB, CSxB,
 176                         NS9XXX_CSxSTAT_PHYS(0) >> 12);
 177
 178         /* ... and mask */
 179         reg = SYS_SMCSSMM(0);
 180         REGSETIM(reg, SYS_SMCSSMM, CSxM, 0xfffff);
 181         REGSET(reg, SYS_SMCSSMM, CSEx, EN);
 182         SYS_SMCSSMM(0) = reg;
 183
 184         /* setup static CS0: memory configuration */
 185         reg = MEM_SMC(0);
 186         REGSET(reg, MEM_SMC, PSMC, OFF);
 187         REGSET(reg, MEM_SMC, BSMC, OFF);
 188         REGSET(reg, MEM_SMC, EW, OFF);
 189         REGSET(reg, MEM_SMC, PB, 1);
 190         REGSET(reg, MEM_SMC, PC, AL);
 191         REGSET(reg, MEM_SMC, PM, DIS);
 192         REGSET(reg, MEM_SMC, MW, 8);
 193         MEM_SMC(0) = reg;
 194
 195         /* setup static CS0: timing */
 196         MEM_SMWED(0) = 0x2;
 197         MEM_SMOED(0) = 0x2;
 198         MEM_SMRD(0) = 0x6;
 199         MEM_SMWD(0) = 0x6;
 200
 201         platform_add_devices(board_a9m9750dev_devices,
 202                         ARRAY_SIZE(board_a9m9750dev_devices));
 203 }