arch/arm/mach-ixp4xx/common.c

   1 /*
   2  * arch/arm/mach-ixp4xx/common.c
   3  *
   4  * Generic code shared across all IXP4XX platforms
   5  *
   6  * Maintainer: Deepak Saxena <dsaxena@plexity.net>
   7  *
   8  * Copyright 2002 (c) Intel Corporation
   9  * Copyright 2003-2004 (c) MontaVista, Software, Inc.
  10  *
  11  * This file is licensed under  the terms of the GNU General Public
  12  * License version 2. This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/mm.h>
  18 #include <linux/init.h>
  19 #include <linux/serial.h>
  20 #include <linux/sched.h>
  21 #include <linux/tty.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/serial_core.h>
  24 #include <linux/bootmem.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/bitops.h>
  27 #include <linux/time.h>
  28 #include <linux/timex.h>
  29 #include <linux/clocksource.h>
  30
  31 #include <asm/arch/udc.h>
  32 #include <asm/hardware.h>
  33 #include <asm/uaccess.h>
  34 #include <asm/io.h>
  35 #include <asm/pgtable.h>
  36 #include <asm/page.h>
  37 #include <asm/irq.h>
  38
  39 #include <asm/mach/map.h>
  40 #include <asm/mach/irq.h>
  41 #include <asm/mach/time.h>
  42
  43 static int __init ixp4xx_clocksource_init(void);
  44
  45 /*************************************************************************
  46  * IXP4xx chipset I/O mapping
  47  *************************************************************************/
  48 static struct map_desc ixp4xx_io_desc[] __initdata = {
  49         {       /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
  50                 .virtual        = IXP4XX_PERIPHERAL_BASE_VIRT,
  51                 .pfn            = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
  52                 .length         = IXP4XX_PERIPHERAL_REGION_SIZE,
  53                 .type           = MT_DEVICE
  54         }, {    /* Expansion Bus Config Registers */
  55                 .virtual        = IXP4XX_EXP_CFG_BASE_VIRT,
  56                 .pfn            = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
  57                 .length         = IXP4XX_EXP_CFG_REGION_SIZE,
  58                 .type           = MT_DEVICE
  59         }, {    /* PCI Registers */
  60                 .virtual        = IXP4XX_PCI_CFG_BASE_VIRT,
  61                 .pfn            = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
  62                 .length         = IXP4XX_PCI_CFG_REGION_SIZE,
  63                 .type           = MT_DEVICE
  64         },
  65 #ifdef CONFIG_DEBUG_LL
  66         {       /* Debug UART mapping */
  67                 .virtual        = IXP4XX_DEBUG_UART_BASE_VIRT,
  68                 .pfn            = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS),
  69                 .length         = IXP4XX_DEBUG_UART_REGION_SIZE,
  70                 .type           = MT_DEVICE
  71         }
  72 #endif
  73 };
  74
  75 void __init ixp4xx_map_io(void)
  76 {
  77         iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
  78 }
  79
  80
  81 /*************************************************************************
  82  * IXP4xx chipset IRQ handling
  83  *
  84  * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
  85  *       (be it PCI or something else) configures that GPIO line
  86  *       as an IRQ.
  87  **************************************************************************/
  88 enum ixp4xx_irq_type {
  89         IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
  90 };
  91
  92 /* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */
  93 static unsigned long long ixp4xx_irq_edge = 0;
  94
  95 /*
  96  * IRQ -> GPIO mapping table
  97  */
  98 static signed char irq2gpio[32] = {
  99         -1, -1, -1, -1, -1, -1,  0,  1,
 100         -1, -1, -1, -1, -1, -1, -1, -1,
 101         -1, -1, -1,  2,  3,  4,  5,  6,
 102          7,  8,  9, 10, 11, 12, -1, -1,
 103 };
 104
 105 int gpio_to_irq(int gpio)
 106 {
 107         int irq;
 108
 109         for (irq = 0; irq < 32; irq++) {
 110                 if (irq2gpio[irq] == gpio)
 111                         return irq;
 112         }
 113         return -EINVAL;
 114 }
 115 EXPORT_SYMBOL(gpio_to_irq);
 116
 117 int irq_to_gpio(int irq)
 118 {
 119         int gpio = (irq < 32) ? irq2gpio[irq] : -EINVAL;
 120
 121         if (gpio == -1)
 122                 return -EINVAL;
 123
 124         return gpio;
 125 }
 126 EXPORT_SYMBOL(irq_to_gpio);
 127
 128 static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
 129 {
 130         int line = irq2gpio[irq];
 131         u32 int_style;
 132         enum ixp4xx_irq_type irq_type;
 133         volatile u32 *int_reg;
 134
 135         /*
 136          * Only for GPIO IRQs
 137          */
 138         if (line < 0)
 139                 return -EINVAL;
 140
 141         switch (type){
 142         case IRQT_BOTHEDGE:
 143                 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
 144                 irq_type = IXP4XX_IRQ_EDGE;
 145                 break;
 146         case IRQT_RISING:
 147                 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
 148                 irq_type = IXP4XX_IRQ_EDGE;
 149                 break;
 150         case IRQT_FALLING:
 151                 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
 152                 irq_type = IXP4XX_IRQ_EDGE;
 153                 break;
 154         case IRQT_HIGH:
 155                 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
 156                 irq_type = IXP4XX_IRQ_LEVEL;
 157                 break;
 158         case IRQT_LOW:
 159                 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
 160                 irq_type = IXP4XX_IRQ_LEVEL;
 161                 break;
 162         default:
 163                 return -EINVAL;
 164         }
 165
 166         if (irq_type == IXP4XX_IRQ_EDGE)
 167                 ixp4xx_irq_edge |= (1 << irq);
 168         else
 169                 ixp4xx_irq_edge &= ~(1 << irq);
 170
 171         if (line >= 8) {        /* pins 8-15 */
 172                 line -= 8;
 173                 int_reg = IXP4XX_GPIO_GPIT2R;
 174         } else {                /* pins 0-7 */
 175                 int_reg = IXP4XX_GPIO_GPIT1R;
 176         }
 177
 178         /* Clear the style for the appropriate pin */
 179         *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
 180                         (line * IXP4XX_GPIO_STYLE_SIZE));
 181
 182         *IXP4XX_GPIO_GPISR = (1 << line);
 183
 184         /* Set the new style */
 185         *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
 186
 187         /* Configure the line as an input */
 188         gpio_line_config(line, IXP4XX_GPIO_IN);
 189
 190         return 0;
 191 }
 192
 193 static void ixp4xx_irq_mask(unsigned int irq)
 194 {
 195         if (cpu_is_ixp46x() && irq >= 32)
 196                 *IXP4XX_ICMR2 &= ~(1 << (irq - 32));
 197         else
 198                 *IXP4XX_ICMR &= ~(1 << irq);
 199 }
 200
 201 static void ixp4xx_irq_ack(unsigned int irq)
 202 {
 203         int line = (irq < 32) ? irq2gpio[irq] : -1;
 204
 205         if (line >= 0)
 206                 *IXP4XX_GPIO_GPISR = (1 << line);
 207 }
 208
 209 /*
 210  * Level triggered interrupts on GPIO lines can only be cleared when the
 211  * interrupt condition disappears.
 212  */
 213 static void ixp4xx_irq_unmask(unsigned int irq)
 214 {
 215         if (!(ixp4xx_irq_edge & (1 << irq)))
 216                 ixp4xx_irq_ack(irq);
 217
 218         if (cpu_is_ixp46x() && irq >= 32)
 219                 *IXP4XX_ICMR2 |= (1 << (irq - 32));
 220         else
 221                 *IXP4XX_ICMR |= (1 << irq);
 222 }
 223
 224 static struct irq_chip ixp4xx_irq_chip = {
 225         .name           = "IXP4xx",
 226         .ack            = ixp4xx_irq_ack,
 227         .mask           = ixp4xx_irq_mask,
 228         .unmask         = ixp4xx_irq_unmask,
 229         .set_type       = ixp4xx_set_irq_type,
 230 };
 231
 232 void __init ixp4xx_init_irq(void)
 233 {
 234         int i = 0;
 235
 236         /* Route all sources to IRQ instead of FIQ */
 237         *IXP4XX_ICLR = 0x0;
 238
 239         /* Disable all interrupt */
 240         *IXP4XX_ICMR = 0x0;
 241
 242         if (cpu_is_ixp46x()) {
 243                 /* Route upper 32 sources to IRQ instead of FIQ */
 244                 *IXP4XX_ICLR2 = 0x00;
 245
 246                 /* Disable upper 32 interrupts */
 247                 *IXP4XX_ICMR2 = 0x00;
 248         }
 249
 250         /* Default to all level triggered */
 251         for(i = 0; i < NR_IRQS; i++) {
 252                 set_irq_chip(i, &ixp4xx_irq_chip);
 253                 set_irq_handler(i, handle_level_irq);
 254                 set_irq_flags(i, IRQF_VALID);
 255         }
 256 }
 257
 258
 259 /*************************************************************************
 260  * IXP4xx timer tick
 261  * We use OS timer1 on the CPU for the timer tick and the timestamp
 262  * counter as a source of real clock ticks to account for missed jiffies.
 263  *************************************************************************/
 264
 265 static unsigned volatile last_jiffy_time;
 266
 267 #define CLOCK_TICKS_PER_USEC    ((CLOCK_TICK_RATE + USEC_PER_SEC/2) / USEC_PER_SEC)
 268
 269 static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
 270 {
 271         write_seqlock(&xtime_lock);
 272
 273         /* Clear Pending Interrupt by writing '1' to it */
 274         *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
 275
 276         /*
 277          * Catch up with the real idea of time
 278          */
 279         while ((signed long)(*IXP4XX_OSTS - last_jiffy_time) >= LATCH) {
 280                 timer_tick();
 281                 last_jiffy_time += LATCH;
 282         }
 283
 284         write_sequnlock(&xtime_lock);
 285
 286         return IRQ_HANDLED;
 287 }
 288
 289 static struct irqaction ixp4xx_timer_irq = {
 290         .name           = "IXP4xx Timer Tick",
 291         .flags          = IRQF_DISABLED | IRQF_TIMER,
 292         .handler        = ixp4xx_timer_interrupt,
 293 };
 294
 295 static void __init ixp4xx_timer_init(void)
 296 {
 297         /* Clear Pending Interrupt by writing '1' to it */
 298         *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
 299
 300         /* Setup the Timer counter value */
 301         *IXP4XX_OSRT1 = (LATCH & ~IXP4XX_OST_RELOAD_MASK) | IXP4XX_OST_ENABLE;
 302
 303         /* Reset time-stamp counter */
 304         *IXP4XX_OSTS = 0;
 305         last_jiffy_time = 0;
 306
 307         /* Connect the interrupt handler and enable the interrupt */
 308         setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
 309
 310         ixp4xx_clocksource_init();
 311 }
 312
 313 struct sys_timer ixp4xx_timer = {
 314         .init           = ixp4xx_timer_init,
 315 };
 316
 317 static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
 318
 319 void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info)
 320 {
 321         memcpy(&ixp4xx_udc_info, info, sizeof *info);
 322 }
 323
 324 static struct resource ixp4xx_udc_resources[] = {
 325         [0] = {
 326                 .start  = 0xc800b000,
 327                 .end    = 0xc800bfff,
 328                 .flags  = IORESOURCE_MEM,
 329         },
 330         [1] = {
 331                 .start  = IRQ_IXP4XX_USB,
 332                 .end    = IRQ_IXP4XX_USB,
 333                 .flags  = IORESOURCE_IRQ,
 334         },
 335 };
 336
 337 /*
 338  * USB device controller. The IXP4xx uses the same controller as PXA2XX,
 339  * so we just use the same device.
 340  */
 341 static struct platform_device ixp4xx_udc_device = {
 342         .name           = "pxa2xx-udc",
 343         .id             = -1,
 344         .num_resources  = 2,
 345         .resource       = ixp4xx_udc_resources,
 346         .dev            = {
 347                 .platform_data = &ixp4xx_udc_info,
 348         },
 349 };
 350
 351 static struct platform_device *ixp4xx_devices[] __initdata = {
 352         &ixp4xx_udc_device,
 353 };
 354
 355 static struct resource ixp46x_i2c_resources[] = {
 356         [0] = {
 357                 .start  = 0xc8011000,
 358                 .end    = 0xc801101c,
 359                 .flags  = IORESOURCE_MEM,
 360         },
 361         [1] = {
 362                 .start  = IRQ_IXP4XX_I2C,
 363                 .end    = IRQ_IXP4XX_I2C,
 364                 .flags  = IORESOURCE_IRQ
 365         }
 366 };
 367
 368 /*
 369  * I2C controller. The IXP46x uses the same block as the IOP3xx, so
 370  * we just use the same device name.
 371  */
 372 static struct platform_device ixp46x_i2c_controller = {
 373         .name           = "IOP3xx-I2C",
 374         .id             = 0,
 375         .num_resources  = 2,
 376         .resource       = ixp46x_i2c_resources
 377 };
 378
 379 static struct platform_device *ixp46x_devices[] __initdata = {
 380         &ixp46x_i2c_controller
 381 };
 382
 383 unsigned long ixp4xx_exp_bus_size;
 384 EXPORT_SYMBOL(ixp4xx_exp_bus_size);
 385
 386 void __init ixp4xx_sys_init(void)
 387 {
 388         ixp4xx_exp_bus_size = SZ_16M;
 389
 390         platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
 391
 392         if (cpu_is_ixp46x()) {
 393                 int region;
 394
 395                 platform_add_devices(ixp46x_devices,
 396                                 ARRAY_SIZE(ixp46x_devices));
 397
 398                 for (region = 0; region < 7; region++) {
 399                         if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
 400                                 ixp4xx_exp_bus_size = SZ_32M;
 401                                 break;
 402                         }
 403                 }
 404         }
 405
 406         printk("IXP4xx: Using %luMiB expansion bus window size\n",
 407                         ixp4xx_exp_bus_size >> 20);
 408 }
 409
 410 cycle_t ixp4xx_get_cycles(void)
 411 {
 412         return *IXP4XX_OSTS;
 413 }
 414
 415 static struct clocksource clocksource_ixp4xx = {
 416         .name           = "OSTS",
 417         .rating         = 200,
 418         .read           = ixp4xx_get_cycles,
 419         .mask           = CLOCKSOURCE_MASK(32),
 420         .shift          = 20,
 421         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 422 };
 423
 424 unsigned long ixp4xx_timer_freq = FREQ;
 425 static int __init ixp4xx_clocksource_init(void)
 426 {
 427         clocksource_ixp4xx.mult =
 428                 clocksource_hz2mult(ixp4xx_timer_freq,
 429                                     clocksource_ixp4xx.shift);
 430         clocksource_register(&clocksource_ixp4xx);
 431
 432         return 0;
 433 }