arch/arm/mach-ixp4xx/common.c

   1 /*
   2  * arch/arm/mach-ixp4xx/common.c
   3  *
   4  * Generic code shared across all IXP4XX platforms
   5  *
   6  * Maintainer: Deepak Saxena <dsaxena@plexity.net>
   7  *
   8  * Copyright 2002 (c) Intel Corporation
   9  * Copyright 2003-2004 (c) MontaVista, Software, Inc.
  10  *
  11  * This file is licensed under  the terms of the GNU General Public
  12  * License version 2. This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/mm.h>
  18 #include <linux/init.h>
  19 #include <linux/serial.h>
  20 #include <linux/sched.h>
  21 #include <linux/tty.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/serial_core.h>
  24 #include <linux/bootmem.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/bitops.h>
  27 #include <linux/time.h>
  28 #include <linux/timex.h>
  29 #include <linux/clocksource.h>
  30
  31 #include <asm/arch/udc.h>
  32 #include <asm/hardware.h>
  33 #include <asm/uaccess.h>
  34 #include <asm/io.h>
  35 #include <asm/pgtable.h>
  36 #include <asm/page.h>
  37 #include <asm/irq.h>
  38
  39 #include <asm/mach/map.h>
  40 #include <asm/mach/irq.h>
  41 #include <asm/mach/time.h>
  42
  43 /*************************************************************************
  44  * IXP4xx chipset I/O mapping
  45  *************************************************************************/
  46 static struct map_desc ixp4xx_io_desc[] __initdata = {
  47         {       /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
  48                 .virtual        = IXP4XX_PERIPHERAL_BASE_VIRT,
  49                 .pfn            = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
  50                 .length         = IXP4XX_PERIPHERAL_REGION_SIZE,
  51                 .type           = MT_DEVICE
  52         }, {    /* Expansion Bus Config Registers */
  53                 .virtual        = IXP4XX_EXP_CFG_BASE_VIRT,
  54                 .pfn            = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
  55                 .length         = IXP4XX_EXP_CFG_REGION_SIZE,
  56                 .type           = MT_DEVICE
  57         }, {    /* PCI Registers */
  58                 .virtual        = IXP4XX_PCI_CFG_BASE_VIRT,
  59                 .pfn            = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
  60                 .length         = IXP4XX_PCI_CFG_REGION_SIZE,
  61                 .type           = MT_DEVICE
  62         },
  63 #ifdef CONFIG_DEBUG_LL
  64         {       /* Debug UART mapping */
  65                 .virtual        = IXP4XX_DEBUG_UART_BASE_VIRT,
  66                 .pfn            = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS),
  67                 .length         = IXP4XX_DEBUG_UART_REGION_SIZE,
  68                 .type           = MT_DEVICE
  69         }
  70 #endif
  71 };
  72
  73 void __init ixp4xx_map_io(void)
  74 {
  75         iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
  76 }
  77
  78
  79 /*************************************************************************
  80  * IXP4xx chipset IRQ handling
  81  *
  82  * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
  83  *       (be it PCI or something else) configures that GPIO line
  84  *       as an IRQ.
  85  **************************************************************************/
  86 enum ixp4xx_irq_type {
  87         IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
  88 };
  89
  90 /* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */
  91 static unsigned long long ixp4xx_irq_edge = 0;
  92
  93 /*
  94  * IRQ -> GPIO mapping table
  95  */
  96 static signed char irq2gpio[32] = {
  97         -1, -1, -1, -1, -1, -1,  0,  1,
  98         -1, -1, -1, -1, -1, -1, -1, -1,
  99         -1, -1, -1,  2,  3,  4,  5,  6,
 100          7,  8,  9, 10, 11, 12, -1, -1,
 101 };
 102
 103 static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
 104 {
 105         int line = irq2gpio[irq];
 106         u32 int_style;
 107         enum ixp4xx_irq_type irq_type;
 108         volatile u32 *int_reg;
 109
 110         /*
 111          * Only for GPIO IRQs
 112          */
 113         if (line < 0)
 114                 return -EINVAL;
 115
 116         switch (type){
 117         case IRQT_BOTHEDGE:
 118                 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
 119                 irq_type = IXP4XX_IRQ_EDGE;
 120                 break;
 121         case IRQT_RISING:
 122                 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
 123                 irq_type = IXP4XX_IRQ_EDGE;
 124                 break;
 125         case IRQT_FALLING:
 126                 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
 127                 irq_type = IXP4XX_IRQ_EDGE;
 128                 break;
 129         case IRQT_HIGH:
 130                 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
 131                 irq_type = IXP4XX_IRQ_LEVEL;
 132                 break;
 133         case IRQT_LOW:
 134                 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
 135                 irq_type = IXP4XX_IRQ_LEVEL;
 136                 break;
 137         default:
 138                 return -EINVAL;
 139         }
 140
 141         if (irq_type == IXP4XX_IRQ_EDGE)
 142                 ixp4xx_irq_edge |= (1 << irq);
 143         else
 144                 ixp4xx_irq_edge &= ~(1 << irq);
 145
 146         if (line >= 8) {        /* pins 8-15 */
 147                 line -= 8;
 148                 int_reg = IXP4XX_GPIO_GPIT2R;
 149         } else {                /* pins 0-7 */
 150                 int_reg = IXP4XX_GPIO_GPIT1R;
 151         }
 152
 153         /* Clear the style for the appropriate pin */
 154         *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
 155                         (line * IXP4XX_GPIO_STYLE_SIZE));
 156
 157         *IXP4XX_GPIO_GPISR = (1 << line);
 158
 159         /* Set the new style */
 160         *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
 161
 162         /* Configure the line as an input */
 163         gpio_line_config(line, IXP4XX_GPIO_IN);
 164
 165         return 0;
 166 }
 167
 168 static void ixp4xx_irq_mask(unsigned int irq)
 169 {
 170         if (cpu_is_ixp46x() && irq >= 32)
 171                 *IXP4XX_ICMR2 &= ~(1 << (irq - 32));
 172         else
 173                 *IXP4XX_ICMR &= ~(1 << irq);
 174 }
 175
 176 static void ixp4xx_irq_ack(unsigned int irq)
 177 {
 178         int line = (irq < 32) ? irq2gpio[irq] : -1;
 179
 180         if (line >= 0)
 181                 *IXP4XX_GPIO_GPISR = (1 << line);
 182 }
 183
 184 /*
 185  * Level triggered interrupts on GPIO lines can only be cleared when the
 186  * interrupt condition disappears.
 187  */
 188 static void ixp4xx_irq_unmask(unsigned int irq)
 189 {
 190         if (!(ixp4xx_irq_edge & (1 << irq)))
 191                 ixp4xx_irq_ack(irq);
 192
 193         if (cpu_is_ixp46x() && irq >= 32)
 194                 *IXP4XX_ICMR2 |= (1 << (irq - 32));
 195         else
 196                 *IXP4XX_ICMR |= (1 << irq);
 197 }
 198
 199 static struct irq_chip ixp4xx_irq_chip = {
 200         .name           = "IXP4xx",
 201         .ack            = ixp4xx_irq_ack,
 202         .mask           = ixp4xx_irq_mask,
 203         .unmask         = ixp4xx_irq_unmask,
 204         .set_type       = ixp4xx_set_irq_type,
 205 };
 206
 207 void __init ixp4xx_init_irq(void)
 208 {
 209         int i = 0;
 210
 211         /* Route all sources to IRQ instead of FIQ */
 212         *IXP4XX_ICLR = 0x0;
 213
 214         /* Disable all interrupt */
 215         *IXP4XX_ICMR = 0x0;
 216
 217         if (cpu_is_ixp46x()) {
 218                 /* Route upper 32 sources to IRQ instead of FIQ */
 219                 *IXP4XX_ICLR2 = 0x00;
 220
 221                 /* Disable upper 32 interrupts */
 222                 *IXP4XX_ICMR2 = 0x00;
 223         }
 224
 225         /* Default to all level triggered */
 226         for(i = 0; i < NR_IRQS; i++) {
 227                 set_irq_chip(i, &ixp4xx_irq_chip);
 228                 set_irq_handler(i, handle_level_irq);
 229                 set_irq_flags(i, IRQF_VALID);
 230         }
 231 }
 232
 233
 234 /*************************************************************************
 235  * IXP4xx timer tick
 236  * We use OS timer1 on the CPU for the timer tick and the timestamp
 237  * counter as a source of real clock ticks to account for missed jiffies.
 238  *************************************************************************/
 239
 240 static unsigned volatile last_jiffy_time;
 241
 242 #define CLOCK_TICKS_PER_USEC    ((CLOCK_TICK_RATE + USEC_PER_SEC/2) / USEC_PER_SEC)
 243
 244 static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
 245 {
 246         write_seqlock(&xtime_lock);
 247
 248         /* Clear Pending Interrupt by writing '1' to it */
 249         *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
 250
 251         /*
 252          * Catch up with the real idea of time
 253          */
 254         while ((signed long)(*IXP4XX_OSTS - last_jiffy_time) >= LATCH) {
 255                 timer_tick();
 256                 last_jiffy_time += LATCH;
 257         }
 258
 259         write_sequnlock(&xtime_lock);
 260
 261         return IRQ_HANDLED;
 262 }
 263
 264 static struct irqaction ixp4xx_timer_irq = {
 265         .name           = "IXP4xx Timer Tick",
 266         .flags          = IRQF_DISABLED | IRQF_TIMER,
 267         .handler        = ixp4xx_timer_interrupt,
 268 };
 269
 270 static void __init ixp4xx_timer_init(void)
 271 {
 272         /* Clear Pending Interrupt by writing '1' to it */
 273         *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
 274
 275         /* Setup the Timer counter value */
 276         *IXP4XX_OSRT1 = (LATCH & ~IXP4XX_OST_RELOAD_MASK) | IXP4XX_OST_ENABLE;
 277
 278         /* Reset time-stamp counter */
 279         *IXP4XX_OSTS = 0;
 280         last_jiffy_time = 0;
 281
 282         /* Connect the interrupt handler and enable the interrupt */
 283         setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
 284 }
 285
 286 struct sys_timer ixp4xx_timer = {
 287         .init           = ixp4xx_timer_init,
 288 };
 289
 290 static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
 291
 292 void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info)
 293 {
 294         memcpy(&ixp4xx_udc_info, info, sizeof *info);
 295 }
 296
 297 static struct resource ixp4xx_udc_resources[] = {
 298         [0] = {
 299                 .start  = 0xc800b000,
 300                 .end    = 0xc800bfff,
 301                 .flags  = IORESOURCE_MEM,
 302         },
 303         [1] = {
 304                 .start  = IRQ_IXP4XX_USB,
 305                 .end    = IRQ_IXP4XX_USB,
 306                 .flags  = IORESOURCE_IRQ,
 307         },
 308 };
 309
 310 /*
 311  * USB device controller. The IXP4xx uses the same controller as PXA2XX,
 312  * so we just use the same device.
 313  */
 314 static struct platform_device ixp4xx_udc_device = {
 315         .name           = "pxa2xx-udc",
 316         .id             = -1,
 317         .num_resources  = 2,
 318         .resource       = ixp4xx_udc_resources,
 319         .dev            = {
 320                 .platform_data = &ixp4xx_udc_info,
 321         },
 322 };
 323
 324 static struct platform_device *ixp4xx_devices[] __initdata = {
 325         &ixp4xx_udc_device,
 326 };
 327
 328 static struct resource ixp46x_i2c_resources[] = {
 329         [0] = {
 330                 .start  = 0xc8011000,
 331                 .end    = 0xc801101c,
 332                 .flags  = IORESOURCE_MEM,
 333         },
 334         [1] = {
 335                 .start  = IRQ_IXP4XX_I2C,
 336                 .end    = IRQ_IXP4XX_I2C,
 337                 .flags  = IORESOURCE_IRQ
 338         }
 339 };
 340
 341 /*
 342  * I2C controller. The IXP46x uses the same block as the IOP3xx, so
 343  * we just use the same device name.
 344  */
 345 static struct platform_device ixp46x_i2c_controller = {
 346         .name           = "IOP3xx-I2C",
 347         .id             = 0,
 348         .num_resources  = 2,
 349         .resource       = ixp46x_i2c_resources
 350 };
 351
 352 static struct platform_device *ixp46x_devices[] __initdata = {
 353         &ixp46x_i2c_controller
 354 };
 355
 356 unsigned long ixp4xx_exp_bus_size;
 357 EXPORT_SYMBOL(ixp4xx_exp_bus_size);
 358
 359 void __init ixp4xx_sys_init(void)
 360 {
 361         ixp4xx_exp_bus_size = SZ_16M;
 362
 363         platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
 364
 365         if (cpu_is_ixp46x()) {
 366                 int region;
 367
 368                 platform_add_devices(ixp46x_devices,
 369                                 ARRAY_SIZE(ixp46x_devices));
 370
 371                 for (region = 0; region < 7; region++) {
 372                         if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
 373                                 ixp4xx_exp_bus_size = SZ_32M;
 374                                 break;
 375                         }
 376                 }
 377         }
 378
 379         printk("IXP4xx: Using %luMiB expansion bus window size\n",
 380                         ixp4xx_exp_bus_size >> 20);
 381 }
 382
 383 cycle_t ixp4xx_get_cycles(void)
 384 {
 385         return *IXP4XX_OSTS;
 386 }
 387
 388 static struct clocksource clocksource_ixp4xx = {
 389         .name           = "OSTS",
 390         .rating         = 200,
 391         .read           = ixp4xx_get_cycles,
 392         .mask           = CLOCKSOURCE_MASK(32),
 393         .shift          = 20,
 394         .is_continuous  = 1,
 395 };
 396
 397 unsigned long ixp4xx_timer_freq = FREQ;
 398 static int __init ixp4xx_clocksource_init(void)
 399 {
 400         clocksource_ixp4xx.mult =
 401                 clocksource_hz2mult(ixp4xx_timer_freq,
 402                                     clocksource_ixp4xx.shift);
 403         clocksource_register(&clocksource_ixp4xx);
 404
 405         return 0;
 406 }
 407
 408 device_initcall(ixp4xx_clocksource_init);