arch/arm/mach-at91/pm.c

   1 /*
   2  * arch/arm/mach-at91/pm.c
   3  * AT91 Power Management
   4  *
   5  * Copyright (C) 2005 David Brownell
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12
  13 #include <linux/suspend.h>
  14 #include <linux/sched.h>
  15 #include <linux/proc_fs.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/sysfs.h>
  18 #include <linux/module.h>
  19 #include <linux/platform_device.h>
  20
  21 #include <asm/io.h>
  22 #include <asm/irq.h>
  23 #include <asm/atomic.h>
  24 #include <asm/mach/time.h>
  25 #include <asm/mach/irq.h>
  26 #include <asm/mach-types.h>
  27
  28 #include <asm/arch/at91_pmc.h>
  29 #include <asm/arch/gpio.h>
  30 #include <asm/arch/cpu.h>
  31
  32 #include "generic.h"
  33
  34 #ifdef CONFIG_ARCH_AT91RM9200
  35 #include <asm/arch/at91rm9200_mc.h>
  36
  37 /*
  38  * The AT91RM9200 goes into self-refresh mode with this command, and will
  39  * terminate self-refresh automatically on the next SDRAM access.
  40  */
  41 #define sdram_selfrefresh_enable()      at91_sys_write(AT91_SDRAMC_SRR, 1)
  42 #define sdram_selfrefresh_disable()     do {} while (0)
  43
  44 #elif defined(CONFIG_ARCH_AT91CAP9)
  45 #include <asm/arch/at91cap9_ddrsdr.h>
  46
  47 static u32 saved_lpr;
  48
  49 static inline void sdram_selfrefresh_enable(void)
  50 {
  51         u32 lpr;
  52
  53         saved_lpr = at91_sys_read(AT91_DDRSDRC_LPR);
  54
  55         lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
  56         at91_sys_write(AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
  57 }
  58
  59 #define sdram_selfrefresh_disable()     at91_sys_write(AT91_DDRSDRC_LPR, saved_lpr)
  60
  61 #else
  62 #include <asm/arch/at91sam9_sdramc.h>
  63
  64 static u32 saved_lpr;
  65
  66 static inline void sdram_selfrefresh_enable(void)
  67 {
  68         u32 lpr;
  69
  70         saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);
  71
  72         lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
  73         at91_sys_write(AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
  74 }
  75
  76 #define sdram_selfrefresh_disable()     at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
  77
  78 /*
  79  * FIXME: The AT91SAM9263 has a second EBI controller which may have
  80  *        additional SDRAM.  pm_slowclock.S will require a similar fix.
  81  */
  82
  83 #endif
  84
  85
  86 static int at91_pm_valid_state(suspend_state_t state)
  87 {
  88         switch (state) {
  89                 case PM_SUSPEND_ON:
  90                 case PM_SUSPEND_STANDBY:
  91                 case PM_SUSPEND_MEM:
  92                         return 1;
  93
  94                 default:
  95                         return 0;
  96         }
  97 }
  98
  99
 100 static suspend_state_t target_state;
 101
 102 /*
 103  * Called after processes are frozen, but before we shutdown devices.
 104  */
 105 static int at91_pm_begin(suspend_state_t state)
 106 {
 107         target_state = state;
 108         return 0;
 109 }
 110
 111 /*
 112  * Verify that all the clocks are correct before entering
 113  * slow-clock mode.
 114  */
 115 static int at91_pm_verify_clocks(void)
 116 {
 117         unsigned long scsr;
 118         int i;
 119
 120         scsr = at91_sys_read(AT91_PMC_SCSR);
 121
 122         /* USB must not be using PLLB */
 123         if (cpu_is_at91rm9200()) {
 124                 if ((scsr & (AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP)) != 0) {
 125                         pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n");
 126                         return 0;
 127                 }
 128         } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263()) {
 129                 if ((scsr & (AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP)) != 0) {
 130                         pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n");
 131                         return 0;
 132                 }
 133         } else if (cpu_is_at91cap9()) {
 134                 if ((scsr & AT91CAP9_PMC_UHP) != 0) {
 135                         pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n");
 136                         return 0;
 137                 }
 138         }
 139
 140 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
 141         /* PCK0..PCK3 must be disabled, or configured to use clk32k */
 142         for (i = 0; i < 4; i++) {
 143                 u32 css;
 144
 145                 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
 146                         continue;
 147
 148                 css = at91_sys_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
 149                 if (css != AT91_PMC_CSS_SLOW) {
 150                         pr_debug("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
 151                         return 0;
 152                 }
 153         }
 154 #endif
 155
 156         return 1;
 157 }
 158
 159 /*
 160  * Call this from platform driver suspend() to see how deeply to suspend.
 161  * For example, some controllers (like OHCI) need one of the PLL clocks
 162  * in order to act as a wakeup source, and those are not available when
 163  * going into slow clock mode.
 164  *
 165  * REVISIT: generalize as clk_will_be_available(clk)?  Other platforms have
 166  * the very same problem (but not using at91 main_clk), and it'd be better
 167  * to add one generic API rather than lots of platform-specific ones.
 168  */
 169 int at91_suspend_entering_slow_clock(void)
 170 {
 171         return (target_state == PM_SUSPEND_MEM);
 172 }
 173 EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
 174
 175
 176 static void (*slow_clock)(void);
 177
 178 #ifdef CONFIG_AT91_SLOW_CLOCK
 179 extern void at91_slow_clock(void);
 180 extern u32 at91_slow_clock_sz;
 181 #endif
 182
 183
 184 static int at91_pm_enter(suspend_state_t state)
 185 {
 186         at91_gpio_suspend();
 187         at91_irq_suspend();
 188
 189         pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
 190                         /* remember all the always-wake irqs */
 191                         (at91_sys_read(AT91_PMC_PCSR)
 192                                         | (1 << AT91_ID_FIQ)
 193                                         | (1 << AT91_ID_SYS)
 194                                         | (at91_extern_irq))
 195                                 & at91_sys_read(AT91_AIC_IMR),
 196                         state);
 197
 198         switch (state) {
 199                 /*
 200                  * Suspend-to-RAM is like STANDBY plus slow clock mode, so
 201                  * drivers must suspend more deeply:  only the master clock
 202                  * controller may be using the main oscillator.
 203                  */
 204                 case PM_SUSPEND_MEM:
 205                         /*
 206                          * Ensure that clocks are in a valid state.
 207                          */
 208                         if (!at91_pm_verify_clocks())
 209                                 goto error;
 210
 211                         /*
 212                          * Enter slow clock mode by switching over to clk32k and
 213                          * turning off the main oscillator; reverse on wakeup.
 214                          */
 215                         if (slow_clock) {
 216 #ifdef CONFIG_AT91_SLOW_CLOCK
 217                                 /* copy slow_clock handler to SRAM, and call it */
 218                                 memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
 219 #endif
 220                                 slow_clock();
 221                                 break;
 222                         } else {
 223                                 pr_info("AT91: PM - no slow clock mode enabled ...\n");
 224                                 /* FALLTHROUGH leaving master clock alone */
 225                         }
 226
 227                 /*
 228                  * STANDBY mode has *all* drivers suspended; ignores irqs not
 229                  * marked as 'wakeup' event sources; and reduces DRAM power.
 230                  * But otherwise it's identical to PM_SUSPEND_ON:  cpu idle, and
 231                  * nothing fancy done with main or cpu clocks.
 232                  */
 233                 case PM_SUSPEND_STANDBY:
 234                         /*
 235                          * NOTE: the Wait-for-Interrupt instruction needs to be
 236                          * in icache so no SDRAM accesses are needed until the
 237                          * wakeup IRQ occurs and self-refresh is terminated.
 238                          */
 239                         asm("b 1f; .align 5; 1:");
 240                         asm("mcr p15, 0, r0, c7, c10, 4");      /* drain write buffer */
 241                         sdram_selfrefresh_enable();
 242                         asm("mcr p15, 0, r0, c7, c0, 4");       /* wait for interrupt */
 243                         sdram_selfrefresh_disable();
 244                         break;
 245
 246                 case PM_SUSPEND_ON:
 247                         asm("mcr p15, 0, r0, c7, c0, 4");       /* wait for interrupt */
 248                         break;
 249
 250                 default:
 251                         pr_debug("AT91: PM - bogus suspend state %d\n", state);
 252                         goto error;
 253         }
 254
 255         pr_debug("AT91: PM - wakeup %08x\n",
 256                         at91_sys_read(AT91_AIC_IPR) & at91_sys_read(AT91_AIC_IMR));
 257
 258 error:
 259         sdram_selfrefresh_disable();
 260         target_state = PM_SUSPEND_ON;
 261         at91_irq_resume();
 262         at91_gpio_resume();
 263         return 0;
 264 }
 265
 266 /*
 267  * Called right prior to thawing processes.
 268  */
 269 static void at91_pm_end(void)
 270 {
 271         target_state = PM_SUSPEND_ON;
 272 }
 273
 274
 275 static struct platform_suspend_ops at91_pm_ops ={
 276         .valid  = at91_pm_valid_state,
 277         .begin  = at91_pm_begin,
 278         .enter  = at91_pm_enter,
 279         .end    = at91_pm_end,
 280 };
 281
 282 static int __init at91_pm_init(void)
 283 {
 284 #ifdef CONFIG_AT91_SLOW_CLOCK
 285         slow_clock = (void *) (AT91_IO_VIRT_BASE - at91_slow_clock_sz);
 286 #endif
 287
 288         pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : ""));
 289
 290 #ifdef CONFIG_ARCH_AT91RM9200
 291         /* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */
 292         at91_sys_write(AT91_SDRAMC_LPR, 0);
 293 #endif
 294
 295         suspend_set_ops(&at91_pm_ops);
 296
 297         return 0;
 298 }
 299 arch_initcall(at91_pm_init);