arch/arm/mach-at91/at91sam9rl_devices.c

   1 /*
   2  *  Copyright (C) 2007 Atmel Corporation
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file COPYING in the main directory of this archive for
   6  * more details.
   7  */
   8
   9 #include <asm/mach/arch.h>
  10 #include <asm/mach/map.h>
  11
  12 #include <linux/dma-mapping.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/i2c-gpio.h>
  15
  16 #include <linux/fb.h>
  17 #include <video/atmel_lcdc.h>
  18
  19 #include <asm/arch/board.h>
  20 #include <asm/arch/gpio.h>
  21 #include <asm/arch/at91sam9rl.h>
  22 #include <asm/arch/at91sam9rl_matrix.h>
  23 #include <asm/arch/at91sam926x_mc.h>
  24
  25 #include "generic.h"
  26
  27
  28 /* --------------------------------------------------------------------
  29  *  MMC / SD
  30  * -------------------------------------------------------------------- */
  31
  32 #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
  33 static u64 mmc_dmamask = DMA_BIT_MASK(32);
  34 static struct at91_mmc_data mmc_data;
  35
  36 static struct resource mmc_resources[] = {
  37         [0] = {
  38                 .start  = AT91SAM9RL_BASE_MCI,
  39                 .end    = AT91SAM9RL_BASE_MCI + SZ_16K - 1,
  40                 .flags  = IORESOURCE_MEM,
  41         },
  42         [1] = {
  43                 .start  = AT91SAM9RL_ID_MCI,
  44                 .end    = AT91SAM9RL_ID_MCI,
  45                 .flags  = IORESOURCE_IRQ,
  46         },
  47 };
  48
  49 static struct platform_device at91sam9rl_mmc_device = {
  50         .name           = "at91_mci",
  51         .id             = -1,
  52         .dev            = {
  53                                 .dma_mask               = &mmc_dmamask,
  54                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
  55                                 .platform_data          = &mmc_data,
  56         },
  57         .resource       = mmc_resources,
  58         .num_resources  = ARRAY_SIZE(mmc_resources),
  59 };
  60
  61 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
  62 {
  63         if (!data)
  64                 return;
  65
  66         /* input/irq */
  67         if (data->det_pin) {
  68                 at91_set_gpio_input(data->det_pin, 1);
  69                 at91_set_deglitch(data->det_pin, 1);
  70         }
  71         if (data->wp_pin)
  72                 at91_set_gpio_input(data->wp_pin, 1);
  73         if (data->vcc_pin)
  74                 at91_set_gpio_output(data->vcc_pin, 0);
  75
  76         /* CLK */
  77         at91_set_A_periph(AT91_PIN_PA2, 0);
  78
  79         /* CMD */
  80         at91_set_A_periph(AT91_PIN_PA1, 1);
  81
  82         /* DAT0, maybe DAT1..DAT3 */
  83         at91_set_A_periph(AT91_PIN_PA0, 1);
  84         if (data->wire4) {
  85                 at91_set_A_periph(AT91_PIN_PA3, 1);
  86                 at91_set_A_periph(AT91_PIN_PA4, 1);
  87                 at91_set_A_periph(AT91_PIN_PA5, 1);
  88         }
  89
  90         mmc_data = *data;
  91         platform_device_register(&at91sam9rl_mmc_device);
  92 }
  93 #else
  94 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
  95 #endif
  96
  97
  98 /* --------------------------------------------------------------------
  99  *  NAND / SmartMedia
 100  * -------------------------------------------------------------------- */
 101
 102 #if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
 103 static struct at91_nand_data nand_data;
 104
 105 #define NAND_BASE       AT91_CHIPSELECT_3
 106
 107 static struct resource nand_resources[] = {
 108         {
 109                 .start  = NAND_BASE,
 110                 .end    = NAND_BASE + SZ_256M - 1,
 111                 .flags  = IORESOURCE_MEM,
 112         }
 113 };
 114
 115 static struct platform_device at91_nand_device = {
 116         .name           = "at91_nand",
 117         .id             = -1,
 118         .dev            = {
 119                                 .platform_data  = &nand_data,
 120         },
 121         .resource       = nand_resources,
 122         .num_resources  = ARRAY_SIZE(nand_resources),
 123 };
 124
 125 void __init at91_add_device_nand(struct at91_nand_data *data)
 126 {
 127         unsigned long csa;
 128
 129         if (!data)
 130                 return;
 131
 132         csa = at91_sys_read(AT91_MATRIX_EBICSA);
 133         at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
 134
 135         /* set the bus interface characteristics */
 136         at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
 137                         | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
 138
 139         at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5)
 140                         | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
 141
 142         at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
 143
 144         at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_DBW_8 | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
 145
 146         /* enable pin */
 147         if (data->enable_pin)
 148                 at91_set_gpio_output(data->enable_pin, 1);
 149
 150         /* ready/busy pin */
 151         if (data->rdy_pin)
 152                 at91_set_gpio_input(data->rdy_pin, 1);
 153
 154         /* card detect pin */
 155         if (data->det_pin)
 156                 at91_set_gpio_input(data->det_pin, 1);
 157
 158         at91_set_A_periph(AT91_PIN_PB4, 0);             /* NANDOE */
 159         at91_set_A_periph(AT91_PIN_PB5, 0);             /* NANDWE */
 160
 161         nand_data = *data;
 162         platform_device_register(&at91_nand_device);
 163 }
 164
 165 #else
 166 void __init at91_add_device_nand(struct at91_nand_data *data) {}
 167 #endif
 168
 169
 170 /* --------------------------------------------------------------------
 171  *  TWI (i2c)
 172  * -------------------------------------------------------------------- */
 173
 174 /*
 175  * Prefer the GPIO code since the TWI controller isn't robust
 176  * (gets overruns and underruns under load) and can only issue
 177  * repeated STARTs in one scenario (the driver doesn't yet handle them).
 178  */
 179 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
 180
 181 static struct i2c_gpio_platform_data pdata = {
 182         .sda_pin                = AT91_PIN_PA23,
 183         .sda_is_open_drain      = 1,
 184         .scl_pin                = AT91_PIN_PA24,
 185         .scl_is_open_drain      = 1,
 186         .udelay                 = 2,            /* ~100 kHz */
 187 };
 188
 189 static struct platform_device at91sam9rl_twi_device = {
 190         .name                   = "i2c-gpio",
 191         .id                     = -1,
 192         .dev.platform_data      = &pdata,
 193 };
 194
 195 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
 196 {
 197         at91_set_GPIO_periph(AT91_PIN_PA23, 1);         /* TWD (SDA) */
 198         at91_set_multi_drive(AT91_PIN_PA23, 1);
 199
 200         at91_set_GPIO_periph(AT91_PIN_PA24, 1);         /* TWCK (SCL) */
 201         at91_set_multi_drive(AT91_PIN_PA24, 1);
 202
 203         i2c_register_board_info(0, devices, nr_devices);
 204         platform_device_register(&at91sam9rl_twi_device);
 205 }
 206
 207 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
 208
 209 static struct resource twi_resources[] = {
 210         [0] = {
 211                 .start  = AT91SAM9RL_BASE_TWI0,
 212                 .end    = AT91SAM9RL_BASE_TWI0 + SZ_16K - 1,
 213                 .flags  = IORESOURCE_MEM,
 214         },
 215         [1] = {
 216                 .start  = AT91SAM9RL_ID_TWI0,
 217                 .end    = AT91SAM9RL_ID_TWI0,
 218                 .flags  = IORESOURCE_IRQ,
 219         },
 220 };
 221
 222 static struct platform_device at91sam9rl_twi_device = {
 223         .name           = "at91_i2c",
 224         .id             = -1,
 225         .resource       = twi_resources,
 226         .num_resources  = ARRAY_SIZE(twi_resources),
 227 };
 228
 229 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
 230 {
 231         /* pins used for TWI interface */
 232         at91_set_A_periph(AT91_PIN_PA23, 0);            /* TWD */
 233         at91_set_multi_drive(AT91_PIN_PA23, 1);
 234
 235         at91_set_A_periph(AT91_PIN_PA24, 0);            /* TWCK */
 236         at91_set_multi_drive(AT91_PIN_PA24, 1);
 237
 238         i2c_register_board_info(0, devices, nr_devices);
 239         platform_device_register(&at91sam9rl_twi_device);
 240 }
 241 #else
 242 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
 243 #endif
 244
 245
 246 /* --------------------------------------------------------------------
 247  *  SPI
 248  * -------------------------------------------------------------------- */
 249
 250 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
 251 static u64 spi_dmamask = DMA_BIT_MASK(32);
 252
 253 static struct resource spi_resources[] = {
 254         [0] = {
 255                 .start  = AT91SAM9RL_BASE_SPI,
 256                 .end    = AT91SAM9RL_BASE_SPI + SZ_16K - 1,
 257                 .flags  = IORESOURCE_MEM,
 258         },
 259         [1] = {
 260                 .start  = AT91SAM9RL_ID_SPI,
 261                 .end    = AT91SAM9RL_ID_SPI,
 262                 .flags  = IORESOURCE_IRQ,
 263         },
 264 };
 265
 266 static struct platform_device at91sam9rl_spi_device = {
 267         .name           = "atmel_spi",
 268         .id             = 0,
 269         .dev            = {
 270                                 .dma_mask               = &spi_dmamask,
 271                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 272         },
 273         .resource       = spi_resources,
 274         .num_resources  = ARRAY_SIZE(spi_resources),
 275 };
 276
 277 static const unsigned spi_standard_cs[4] = { AT91_PIN_PA28, AT91_PIN_PB7, AT91_PIN_PD8, AT91_PIN_PD9 };
 278
 279
 280 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
 281 {
 282         int i;
 283         unsigned long cs_pin;
 284
 285         at91_set_A_periph(AT91_PIN_PA25, 0);    /* MISO */
 286         at91_set_A_periph(AT91_PIN_PA26, 0);    /* MOSI */
 287         at91_set_A_periph(AT91_PIN_PA27, 0);    /* SPCK */
 288
 289         /* Enable SPI chip-selects */
 290         for (i = 0; i < nr_devices; i++) {
 291                 if (devices[i].controller_data)
 292                         cs_pin = (unsigned long) devices[i].controller_data;
 293                 else
 294                         cs_pin = spi_standard_cs[devices[i].chip_select];
 295
 296                 /* enable chip-select pin */
 297                 at91_set_gpio_output(cs_pin, 1);
 298
 299                 /* pass chip-select pin to driver */
 300                 devices[i].controller_data = (void *) cs_pin;
 301         }
 302
 303         spi_register_board_info(devices, nr_devices);
 304         platform_device_register(&at91sam9rl_spi_device);
 305 }
 306 #else
 307 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
 308 #endif
 309
 310
 311 /* --------------------------------------------------------------------
 312  *  LCD Controller
 313  * -------------------------------------------------------------------- */
 314
 315 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
 316 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
 317 static struct atmel_lcdfb_info lcdc_data;
 318
 319 static struct resource lcdc_resources[] = {
 320         [0] = {
 321                 .start  = AT91SAM9RL_LCDC_BASE,
 322                 .end    = AT91SAM9RL_LCDC_BASE + SZ_4K - 1,
 323                 .flags  = IORESOURCE_MEM,
 324         },
 325         [1] = {
 326                 .start  = AT91SAM9RL_ID_LCDC,
 327                 .end    = AT91SAM9RL_ID_LCDC,
 328                 .flags  = IORESOURCE_IRQ,
 329         },
 330 #if defined(CONFIG_FB_INTSRAM)
 331         [2] = {
 332                 .start  = AT91SAM9RL_SRAM_BASE,
 333                 .end    = AT91SAM9RL_SRAM_BASE + AT91SAM9RL_SRAM_SIZE - 1,
 334                 .flags  = IORESOURCE_MEM,
 335         },
 336 #endif
 337 };
 338
 339 static struct platform_device at91_lcdc_device = {
 340         .name           = "atmel_lcdfb",
 341         .id             = 0,
 342         .dev            = {
 343                                 .dma_mask               = &lcdc_dmamask,
 344                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 345                                 .platform_data          = &lcdc_data,
 346         },
 347         .resource       = lcdc_resources,
 348         .num_resources  = ARRAY_SIZE(lcdc_resources),
 349 };
 350
 351 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
 352 {
 353         if (!data) {
 354                 return;
 355         }
 356
 357         at91_set_B_periph(AT91_PIN_PC1, 0);     /* LCDPWR */
 358         at91_set_A_periph(AT91_PIN_PC5, 0);     /* LCDHSYNC */
 359         at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDDOTCK */
 360         at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDDEN */
 361         at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDCC */
 362         at91_set_B_periph(AT91_PIN_PC9, 0);     /* LCDD3 */
 363         at91_set_B_periph(AT91_PIN_PC10, 0);    /* LCDD4 */
 364         at91_set_B_periph(AT91_PIN_PC11, 0);    /* LCDD5 */
 365         at91_set_B_periph(AT91_PIN_PC12, 0);    /* LCDD6 */
 366         at91_set_B_periph(AT91_PIN_PC13, 0);    /* LCDD7 */
 367         at91_set_B_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
 368         at91_set_B_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
 369         at91_set_B_periph(AT91_PIN_PC17, 0);    /* LCDD13 */
 370         at91_set_B_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
 371         at91_set_B_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
 372         at91_set_B_periph(AT91_PIN_PC20, 0);    /* LCDD18 */
 373         at91_set_B_periph(AT91_PIN_PC21, 0);    /* LCDD19 */
 374         at91_set_B_periph(AT91_PIN_PC22, 0);    /* LCDD20 */
 375         at91_set_B_periph(AT91_PIN_PC23, 0);    /* LCDD21 */
 376         at91_set_B_periph(AT91_PIN_PC24, 0);    /* LCDD22 */
 377         at91_set_B_periph(AT91_PIN_PC25, 0);    /* LCDD23 */
 378
 379         lcdc_data = *data;
 380         platform_device_register(&at91_lcdc_device);
 381 }
 382 #else
 383 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
 384 #endif
 385
 386
 387 /* --------------------------------------------------------------------
 388  *  RTC
 389  * -------------------------------------------------------------------- */
 390
 391 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
 392 static struct platform_device at91sam9rl_rtc_device = {
 393         .name           = "at91_rtc",
 394         .id             = -1,
 395         .num_resources  = 0,
 396 };
 397
 398 static void __init at91_add_device_rtc(void)
 399 {
 400         platform_device_register(&at91sam9rl_rtc_device);
 401 }
 402 #else
 403 static void __init at91_add_device_rtc(void) {}
 404 #endif
 405
 406
 407 /* --------------------------------------------------------------------
 408  *  RTT
 409  * -------------------------------------------------------------------- */
 410
 411 static struct resource rtt_resources[] = {
 412         {
 413                 .start  = AT91_BASE_SYS + AT91_RTT,
 414                 .end    = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
 415                 .flags  = IORESOURCE_MEM,
 416         }
 417 };
 418
 419 static struct platform_device at91sam9rl_rtt_device = {
 420         .name           = "at91_rtt",
 421         .id             = -1,
 422         .resource       = rtt_resources,
 423         .num_resources  = ARRAY_SIZE(rtt_resources),
 424 };
 425
 426 static void __init at91_add_device_rtt(void)
 427 {
 428         platform_device_register(&at91sam9rl_rtt_device);
 429 }
 430
 431
 432 /* --------------------------------------------------------------------
 433  *  Watchdog
 434  * -------------------------------------------------------------------- */
 435
 436 #if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE)
 437 static struct platform_device at91sam9rl_wdt_device = {
 438         .name           = "at91_wdt",
 439         .id             = -1,
 440         .num_resources  = 0,
 441 };
 442
 443 static void __init at91_add_device_watchdog(void)
 444 {
 445         platform_device_register(&at91sam9rl_wdt_device);
 446 }
 447 #else
 448 static void __init at91_add_device_watchdog(void) {}
 449 #endif
 450
 451
 452 /* --------------------------------------------------------------------
 453  *  LEDs
 454  * -------------------------------------------------------------------- */
 455
 456 #if defined(CONFIG_LEDS)
 457 u8 at91_leds_cpu;
 458 u8 at91_leds_timer;
 459
 460 void __init at91_init_leds(u8 cpu_led, u8 timer_led)
 461 {
 462         /* Enable GPIO to access the LEDs */
 463         at91_set_gpio_output(cpu_led, 1);
 464         at91_set_gpio_output(timer_led, 1);
 465
 466         at91_leds_cpu   = cpu_led;
 467         at91_leds_timer = timer_led;
 468 }
 469 #else
 470 void __init at91_init_leds(u8 cpu_led, u8 timer_led) {}
 471 #endif
 472
 473
 474 /* --------------------------------------------------------------------
 475  *  UART
 476  * -------------------------------------------------------------------- */
 477
 478 #if defined(CONFIG_SERIAL_ATMEL)
 479 static struct resource dbgu_resources[] = {
 480         [0] = {
 481                 .start  = AT91_VA_BASE_SYS + AT91_DBGU,
 482                 .end    = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
 483                 .flags  = IORESOURCE_MEM,
 484         },
 485         [1] = {
 486                 .start  = AT91_ID_SYS,
 487                 .end    = AT91_ID_SYS,
 488                 .flags  = IORESOURCE_IRQ,
 489         },
 490 };
 491
 492 static struct atmel_uart_data dbgu_data = {
 493         .use_dma_tx     = 0,
 494         .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
 495         .regs           = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
 496 };
 497
 498 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
 499
 500 static struct platform_device at91sam9rl_dbgu_device = {
 501         .name           = "atmel_usart",
 502         .id             = 0,
 503         .dev            = {
 504                                 .dma_mask               = &dbgu_dmamask,
 505                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 506                                 .platform_data          = &dbgu_data,
 507         },
 508         .resource       = dbgu_resources,
 509         .num_resources  = ARRAY_SIZE(dbgu_resources),
 510 };
 511
 512 static inline void configure_dbgu_pins(void)
 513 {
 514         at91_set_A_periph(AT91_PIN_PA21, 0);            /* DRXD */
 515         at91_set_A_periph(AT91_PIN_PA22, 1);            /* DTXD */
 516 }
 517
 518 static struct resource uart0_resources[] = {
 519         [0] = {
 520                 .start  = AT91SAM9RL_BASE_US0,
 521                 .end    = AT91SAM9RL_BASE_US0 + SZ_16K - 1,
 522                 .flags  = IORESOURCE_MEM,
 523         },
 524         [1] = {
 525                 .start  = AT91SAM9RL_ID_US0,
 526                 .end    = AT91SAM9RL_ID_US0,
 527                 .flags  = IORESOURCE_IRQ,
 528         },
 529 };
 530
 531 static struct atmel_uart_data uart0_data = {
 532         .use_dma_tx     = 1,
 533         .use_dma_rx     = 1,
 534 };
 535
 536 static u64 uart0_dmamask = DMA_BIT_MASK(32);
 537
 538 static struct platform_device at91sam9rl_uart0_device = {
 539         .name           = "atmel_usart",
 540         .id             = 1,
 541         .dev            = {
 542                                 .dma_mask               = &uart0_dmamask,
 543                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 544                                 .platform_data          = &uart0_data,
 545         },
 546         .resource       = uart0_resources,
 547         .num_resources  = ARRAY_SIZE(uart0_resources),
 548 };
 549
 550 static inline void configure_usart0_pins(void)
 551 {
 552         at91_set_A_periph(AT91_PIN_PA6, 1);             /* TXD0 */
 553         at91_set_A_periph(AT91_PIN_PA7, 0);             /* RXD0 */
 554         at91_set_A_periph(AT91_PIN_PA9, 0);             /* RTS0 */
 555         at91_set_A_periph(AT91_PIN_PA10, 0);            /* CTS0 */
 556 }
 557
 558 static struct resource uart1_resources[] = {
 559         [0] = {
 560                 .start  = AT91SAM9RL_BASE_US1,
 561                 .end    = AT91SAM9RL_BASE_US1 + SZ_16K - 1,
 562                 .flags  = IORESOURCE_MEM,
 563         },
 564         [1] = {
 565                 .start  = AT91SAM9RL_ID_US1,
 566                 .end    = AT91SAM9RL_ID_US1,
 567                 .flags  = IORESOURCE_IRQ,
 568         },
 569 };
 570
 571 static struct atmel_uart_data uart1_data = {
 572         .use_dma_tx     = 1,
 573         .use_dma_rx     = 1,
 574 };
 575
 576 static u64 uart1_dmamask = DMA_BIT_MASK(32);
 577
 578 static struct platform_device at91sam9rl_uart1_device = {
 579         .name           = "atmel_usart",
 580         .id             = 2,
 581         .dev            = {
 582                                 .dma_mask               = &uart1_dmamask,
 583                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 584                                 .platform_data          = &uart1_data,
 585         },
 586         .resource       = uart1_resources,
 587         .num_resources  = ARRAY_SIZE(uart1_resources),
 588 };
 589
 590 static inline void configure_usart1_pins(void)
 591 {
 592         at91_set_A_periph(AT91_PIN_PA11, 1);            /* TXD1 */
 593         at91_set_A_periph(AT91_PIN_PA12, 0);            /* RXD1 */
 594 }
 595
 596 static struct resource uart2_resources[] = {
 597         [0] = {
 598                 .start  = AT91SAM9RL_BASE_US2,
 599                 .end    = AT91SAM9RL_BASE_US2 + SZ_16K - 1,
 600                 .flags  = IORESOURCE_MEM,
 601         },
 602         [1] = {
 603                 .start  = AT91SAM9RL_ID_US2,
 604                 .end    = AT91SAM9RL_ID_US2,
 605                 .flags  = IORESOURCE_IRQ,
 606         },
 607 };
 608
 609 static struct atmel_uart_data uart2_data = {
 610         .use_dma_tx     = 1,
 611         .use_dma_rx     = 1,
 612 };
 613
 614 static u64 uart2_dmamask = DMA_BIT_MASK(32);
 615
 616 static struct platform_device at91sam9rl_uart2_device = {
 617         .name           = "atmel_usart",
 618         .id             = 3,
 619         .dev            = {
 620                                 .dma_mask               = &uart2_dmamask,
 621                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 622                                 .platform_data          = &uart2_data,
 623         },
 624         .resource       = uart2_resources,
 625         .num_resources  = ARRAY_SIZE(uart2_resources),
 626 };
 627
 628 static inline void configure_usart2_pins(void)
 629 {
 630         at91_set_A_periph(AT91_PIN_PA13, 1);            /* TXD2 */
 631         at91_set_A_periph(AT91_PIN_PA14, 0);            /* RXD2 */
 632 }
 633
 634 static struct resource uart3_resources[] = {
 635         [0] = {
 636                 .start  = AT91SAM9RL_BASE_US3,
 637                 .end    = AT91SAM9RL_BASE_US3 + SZ_16K - 1,
 638                 .flags  = IORESOURCE_MEM,
 639         },
 640         [1] = {
 641                 .start  = AT91SAM9RL_ID_US3,
 642                 .end    = AT91SAM9RL_ID_US3,
 643                 .flags  = IORESOURCE_IRQ,
 644         },
 645 };
 646
 647 static struct atmel_uart_data uart3_data = {
 648         .use_dma_tx     = 1,
 649         .use_dma_rx     = 1,
 650 };
 651
 652 static u64 uart3_dmamask = DMA_BIT_MASK(32);
 653
 654 static struct platform_device at91sam9rl_uart3_device = {
 655         .name           = "atmel_usart",
 656         .id             = 4,
 657         .dev            = {
 658                                 .dma_mask               = &uart3_dmamask,
 659                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 660                                 .platform_data          = &uart3_data,
 661         },
 662         .resource       = uart3_resources,
 663         .num_resources  = ARRAY_SIZE(uart3_resources),
 664 };
 665
 666 static inline void configure_usart3_pins(void)
 667 {
 668         at91_set_A_periph(AT91_PIN_PB0, 1);             /* TXD3 */
 669         at91_set_A_periph(AT91_PIN_PB1, 0);             /* RXD3 */
 670 }
 671
 672 static struct platform_device *at91_uarts[ATMEL_MAX_UART];      /* the UARTs to use */
 673 struct platform_device *atmel_default_console_device;   /* the serial console device */
 674
 675 void __init at91_init_serial(struct at91_uart_config *config)
 676 {
 677         int i;
 678
 679         /* Fill in list of supported UARTs */
 680         for (i = 0; i < config->nr_tty; i++) {
 681                 switch (config->tty_map[i]) {
 682                         case 0:
 683                                 configure_usart0_pins();
 684                                 at91_uarts[i] = &at91sam9rl_uart0_device;
 685                                 at91_clock_associate("usart0_clk", &at91sam9rl_uart0_device.dev, "usart");
 686                                 break;
 687                         case 1:
 688                                 configure_usart1_pins();
 689                                 at91_uarts[i] = &at91sam9rl_uart1_device;
 690                                 at91_clock_associate("usart1_clk", &at91sam9rl_uart1_device.dev, "usart");
 691                                 break;
 692                         case 2:
 693                                 configure_usart2_pins();
 694                                 at91_uarts[i] = &at91sam9rl_uart2_device;
 695                                 at91_clock_associate("usart2_clk", &at91sam9rl_uart2_device.dev, "usart");
 696                                 break;
 697                         case 3:
 698                                 configure_usart3_pins();
 699                                 at91_uarts[i] = &at91sam9rl_uart3_device;
 700                                 at91_clock_associate("usart3_clk", &at91sam9rl_uart3_device.dev, "usart");
 701                                 break;
 702                         case 4:
 703                                 configure_dbgu_pins();
 704                                 at91_uarts[i] = &at91sam9rl_dbgu_device;
 705                                 at91_clock_associate("mck", &at91sam9rl_dbgu_device.dev, "usart");
 706                                 break;
 707                         default:
 708                                 continue;
 709                 }
 710                 at91_uarts[i]->id = i;          /* update ID number to mapped ID */
 711         }
 712
 713         /* Set serial console device */
 714         if (config->console_tty < ATMEL_MAX_UART)
 715                 atmel_default_console_device = at91_uarts[config->console_tty];
 716         if (!atmel_default_console_device)
 717                 printk(KERN_INFO "AT91: No default serial console defined.\n");
 718 }
 719
 720 void __init at91_add_device_serial(void)
 721 {
 722         int i;
 723
 724         for (i = 0; i < ATMEL_MAX_UART; i++) {
 725                 if (at91_uarts[i])
 726                         platform_device_register(at91_uarts[i]);
 727         }
 728 }
 729 #else
 730 void __init at91_init_serial(struct at91_uart_config *config) {}
 731 void __init at91_add_device_serial(void) {}
 732 #endif
 733
 734
 735 /* -------------------------------------------------------------------- */
 736
 737 /*
 738  * These devices are always present and don't need any board-specific
 739  * setup.
 740  */
 741 static int __init at91_add_standard_devices(void)
 742 {
 743         at91_add_device_rtc();
 744         at91_add_device_rtt();
 745         at91_add_device_watchdog();
 746         return 0;
 747 }
 748
 749 arch_initcall(at91_add_standard_devices);