arch/arm/include/asm/cachetype.h

   1 #ifndef __ASM_ARM_CACHETYPE_H
   2 #define __ASM_ARM_CACHETYPE_H
   3
   4 #include <asm/cputype.h>
   5
   6 #define __cacheid_present(val)                  (val != read_cpuid_id())
   7 #define __cacheid_type_v7(val)                  ((val & (7 << 29)) == (4 << 29))
   8
   9 #define __cacheid_vivt_prev7(val)               ((val & (15 << 25)) != (14 << 25))
  10 #define __cacheid_vipt_prev7(val)               ((val & (15 << 25)) == (14 << 25))
  11 #define __cacheid_vipt_nonaliasing_prev7(val)   ((val & (15 << 25 | 1 << 23)) == (14 << 25))
  12 #define __cacheid_vipt_aliasing_prev7(val)      ((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23))
  13
  14 #define __cacheid_vivt(val)                     (__cacheid_type_v7(val) ? 0 : __cacheid_vivt_prev7(val))
  15 #define __cacheid_vipt(val)                     (__cacheid_type_v7(val) ? 1 : __cacheid_vipt_prev7(val))
  16 #define __cacheid_vipt_nonaliasing(val)         (__cacheid_type_v7(val) ? 1 : __cacheid_vipt_nonaliasing_prev7(val))
  17 #define __cacheid_vipt_aliasing(val)            (__cacheid_type_v7(val) ? 0 : __cacheid_vipt_aliasing_prev7(val))
  18 #define __cacheid_vivt_asid_tagged_instr(val)   (__cacheid_type_v7(val) ? ((val & (3 << 14)) == (1 << 14)) : 0)
  19
  20 #if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
  21 /*
  22  * VIVT caches only
  23  */
  24 #define cache_is_vivt()                 1
  25 #define cache_is_vipt()                 0
  26 #define cache_is_vipt_nonaliasing()     0
  27 #define cache_is_vipt_aliasing()        0
  28 #define icache_is_vivt_asid_tagged()    0
  29
  30 #elif !defined(CONFIG_CPU_CACHE_VIVT) && defined(CONFIG_CPU_CACHE_VIPT)
  31 /*
  32  * VIPT caches only
  33  */
  34 #define cache_is_vivt()                 0
  35 #define cache_is_vipt()                 1
  36 #define cache_is_vipt_nonaliasing()                                     \
  37         ({                                                              \
  38                 unsigned int __val = read_cpuid_cachetype();            \
  39                 __cacheid_vipt_nonaliasing(__val);                      \
  40         })
  41
  42 #define cache_is_vipt_aliasing()                                        \
  43         ({                                                              \
  44                 unsigned int __val = read_cpuid_cachetype();            \
  45                 __cacheid_vipt_aliasing(__val);                         \
  46         })
  47
  48 #define icache_is_vivt_asid_tagged()                                    \
  49         ({                                                              \
  50                 unsigned int __val = read_cpuid_cachetype();            \
  51                 __cacheid_vivt_asid_tagged_instr(__val);                \
  52         })
  53
  54 #else
  55 /*
  56  * VIVT or VIPT caches.  Note that this is unreliable since ARM926
  57  * and V6 CPUs satisfy the "(val & (15 << 25)) == (14 << 25)" test.
  58  * There's no way to tell from the CacheType register what type (!)
  59  * the cache is.
  60  */
  61 #define cache_is_vivt()                                                 \
  62         ({                                                              \
  63                 unsigned int __val = read_cpuid_cachetype();            \
  64                 (!__cacheid_present(__val)) || __cacheid_vivt(__val);   \
  65         })
  66
  67 #define cache_is_vipt()                                                 \
  68         ({                                                              \
  69                 unsigned int __val = read_cpuid_cachetype();            \
  70                 __cacheid_present(__val) && __cacheid_vipt(__val);      \
  71         })
  72
  73 #define cache_is_vipt_nonaliasing()                                     \
  74         ({                                                              \
  75                 unsigned int __val = read_cpuid_cachetype();            \
  76                 __cacheid_present(__val) &&                             \
  77                  __cacheid_vipt_nonaliasing(__val);                     \
  78         })
  79
  80 #define cache_is_vipt_aliasing()                                        \
  81         ({                                                              \
  82                 unsigned int __val = read_cpuid_cachetype();            \
  83                 __cacheid_present(__val) &&                             \
  84                  __cacheid_vipt_aliasing(__val);                        \
  85         })
  86
  87 #define icache_is_vivt_asid_tagged()                                    \
  88         ({                                                              \
  89                 unsigned int __val = read_cpuid_cachetype();            \
  90                 __cacheid_present(__val) &&                             \
  91                  __cacheid_vivt_asid_tagged_instr(__val);               \
  92         })
  93
  94 #endif
  95
  96 #endif