2 * linux/arch/arm/boot/compressed/head.S
4 * Copyright (C) 1996-2002 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/config.h>
11 #include <linux/linkage.h>
16 * Note that these macros must not contain any code which is not
17 * 100% relocatable. Any attempt to do so will result in a crash.
18 * Please select one of the following when turning on debugging.
22 #if defined(CONFIG_DEBUG_ICEDCC)
26 mcr p14, 0, \ch, c0, c1, 0
30 #include <asm/arch/debug-macro.S>
36 #if defined(CONFIG_ARCH_SA1100)
38 mov \rb, #0x80000000 @ physical base address
39 #ifdef CONFIG_DEBUG_LL_SER3
40 add \rb, \rb, #0x00050000 @ Ser3
42 add \rb, \rb, #0x00010000 @ Ser1
45 #elif defined(CONFIG_ARCH_OMAP2)
47 mov \rb, #0x48000000 @ physical base address
48 add \rb, \rb, #0x0006a000
49 #ifdef CONFIG_OMAP_LL_DEBUG_UART2
50 add \rb, \rb, #0x00002000
52 #ifdef CONFIG_OMAP_LL_DEBUG_UART3
53 add \rb, \rb, #0x00004000
59 #elif defined(CONFIG_ARCH_IOP331)
62 orr \rb, \rb, #0x00ff0000
63 orr \rb, \rb, #0x0000f700 @ location of the UART
65 #elif defined(CONFIG_ARCH_S3C2410)
68 add \rb, \rb, #0x4000 * CONFIG_S3C2410_LOWLEVEL_UART_PORT
89 .macro debug_reloc_start
92 kphex r6, 8 /* processor id */
94 kphex r7, 8 /* architecture id */
96 mrc p15, 0, r0, c1, c0
97 kphex r0, 8 /* control reg */
99 kphex r5, 8 /* decompressed kernel start */
101 kphex r9, 8 /* decompressed kernel end */
103 kphex r4, 8 /* kernel execution address */
108 .macro debug_reloc_end
110 kphex r5, 8 /* end of kernel */
113 bl memdump /* dump 256 bytes at start of kernel */
117 .section ".start", #alloc, #execinstr
119 * sort out different calling conventions
123 .type start,#function
129 .word 0x016f2818 @ Magic numbers to help the loader
130 .word start @ absolute load/run zImage address
131 .word _edata @ zImage end address
132 1: mov r7, r1 @ save architecture ID
133 mov r8, r2 @ save atags pointer
135 #ifndef __ARM_ARCH_2__
137 * Booting from Angel - need to enter SVC mode and disable
138 * FIQs/IRQs (numeric definitions from angel arm.h source).
139 * We only do this if we were in user mode on entry.
141 mrs r2, cpsr @ get current mode
142 tst r2, #3 @ not user?
144 mov r0, #0x17 @ angel_SWIreason_EnterSVC
145 swi 0x123456 @ angel_SWI_ARM
147 mrs r2, cpsr @ turn off interrupts to
148 orr r2, r2, #0xc0 @ prevent angel from running
151 teqp pc, #0x0c000003 @ turn off interrupts
155 * Note that some cache flushing and other stuff may
156 * be needed here - is there an Angel SWI call for this?
160 * some architecture specific code can be inserted
161 * by the linker here, but it should preserve r7, r8, and r9.
166 ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp}
167 subs r0, r0, r1 @ calculate the delta offset
169 @ if delta is zero, we are
170 beq not_relocated @ running at the address we
174 * We're running at a different address. We need to fix
175 * up various pointers:
176 * r5 - zImage base address
184 #ifndef CONFIG_ZBOOT_ROM
186 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
187 * we need to fix up pointers into the BSS region.
197 * Relocate all entries in the GOT table.
199 1: ldr r1, [r6, #0] @ relocate entries in the GOT
200 add r1, r1, r0 @ table. This fixes up the
201 str r1, [r6], #4 @ C references.
207 * Relocate entries in the GOT table. We only relocate
208 * the entries that are outside the (relocated) BSS region.
210 1: ldr r1, [r6, #0] @ relocate entries in the GOT
211 cmp r1, r2 @ entry < bss_start ||
212 cmphs r3, r1 @ _end < entry
213 addlo r1, r1, r0 @ table. This fixes up the
214 str r1, [r6], #4 @ C references.
219 not_relocated: mov r0, #0
220 1: str r0, [r2], #4 @ clear bss
228 * The C runtime environment should now be setup
229 * sufficiently. Turn the cache on, set up some
230 * pointers, and start decompressing.
234 mov r1, sp @ malloc space above stack
235 add r2, sp, #0x10000 @ 64k max
238 * Check to see if we will overwrite ourselves.
239 * r4 = final kernel address
240 * r5 = start of this image
241 * r2 = end of malloc space (and therefore this image)
244 * r4 + image length <= r5 -> OK
248 add r0, r4, #4096*1024 @ 4MB largest kernel size
252 mov r5, r2 @ decompress after malloc space
258 bic r0, r0, #127 @ align the kernel length
260 * r0 = decompressed kernel length
262 * r4 = kernel execution address
263 * r5 = decompressed kernel start
265 * r7 = architecture ID
269 add r1, r5, r0 @ end of decompressed kernel
273 1: ldmia r2!, {r9 - r14} @ copy relocation code
274 stmia r1!, {r9 - r14}
275 ldmia r2!, {r9 - r14}
276 stmia r1!, {r9 - r14}
281 add pc, r5, r0 @ call relocation code
284 * We're not in danger of overwriting ourselves. Do this the simple way.
286 * r4 = kernel execution address
287 * r7 = architecture ID
289 wont_overwrite: mov r0, r4
296 .word __bss_start @ r2
300 .word _got_start @ r6
302 .word user_stack+4096 @ sp
303 LC1: .word reloc_end - reloc_start
306 #ifdef CONFIG_ARCH_RPC
308 params: ldr r0, =params_phys
315 * Turn on the cache. We need to setup some page tables so that we
316 * can have both the I and D caches on.
318 * We place the page tables 16k down from the kernel execution address,
319 * and we hope that nothing else is using it. If we're using it, we
323 * r4 = kernel execution address
325 * r7 = architecture number
327 * r9 = run-time address of "start" (???)
329 * r1, r2, r3, r9, r10, r12 corrupted
330 * This routine must preserve:
334 cache_on: mov r3, #8 @ cache_on function
337 __setup_mmu: sub r3, r4, #16384 @ Page directory size
338 bic r3, r3, #0xff @ Align the pointer
341 * Initialise the page tables, turning on the cacheable and bufferable
342 * bits for the RAM area only.
346 mov r9, r9, lsl #18 @ start of RAM
347 add r10, r9, #0x10000000 @ a reasonable RAM size
351 1: cmp r1, r9 @ if virt > start of RAM
352 orrhs r1, r1, #0x0c @ set cacheable, bufferable
353 cmp r1, r10 @ if virt > end of RAM
354 bichs r1, r1, #0x0c @ clear cacheable, bufferable
355 str r1, [r0], #4 @ 1:1 mapping
360 * If ever we are running from Flash, then we surely want the cache
361 * to be enabled also for our execution instance... We map 2MB of it
362 * so there is no map overlap problem for up to 1 MB compressed kernel.
363 * If the execution is in RAM then we would only be duplicating the above.
368 orr r1, r1, r2, lsl #20
369 add r0, r3, r2, lsl #2
379 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
380 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
381 mrc p15, 0, r0, c1, c0, 0 @ read control reg
382 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
386 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
393 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
394 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
398 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
403 orr r0, r0, #0x000d @ Write buffer, mmu
406 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
407 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
408 mcr p15, 0, r0, c1, c0, 0 @ load control register
412 * All code following this line is relocatable. It is relocated by
413 * the above code to the end of the decompressed kernel image and
414 * executed there. During this time, we have no stacks.
416 * r0 = decompressed kernel length
418 * r4 = kernel execution address
419 * r5 = decompressed kernel start
421 * r7 = architecture ID
426 reloc_start: add r9, r5, r0
431 ldmia r5!, {r0, r2, r3, r10 - r14} @ relocate kernel
432 stmia r1!, {r0, r2, r3, r10 - r14}
439 call_kernel: bl cache_clean_flush
441 mov r0, #0 @ must be zero
442 mov r1, r7 @ restore architecture number
443 mov r2, r8 @ restore atags pointer
444 mov pc, r4 @ call kernel
447 * Here follow the relocatable cache support functions for the
448 * various processors. This is a generic hook for locating an
449 * entry and jumping to an instruction at the specified offset
450 * from the start of the block. Please note this is all position
460 call_cache_fn: adr r12, proc_types
461 mrc p15, 0, r6, c0, c0 @ get processor ID
462 1: ldr r1, [r12, #0] @ get value
463 ldr r2, [r12, #4] @ get mask
464 eor r1, r1, r6 @ (real ^ match)
466 addeq pc, r12, r3 @ call cache function
471 * Table for cache operations. This is basically:
474 * - 'cache on' method instruction
475 * - 'cache off' method instruction
476 * - 'cache flush' method instruction
478 * We match an entry using: ((real_id ^ match) & mask) == 0
480 * Writethrough caches generally only need 'on' and 'off'
481 * methods. Writeback caches _must_ have the flush method
484 .type proc_types,#object
486 .word 0x41560600 @ ARM6/610
488 b __arm6_cache_off @ works, but slow
491 @ b __arm6_cache_on @ untested
493 @ b __armv3_cache_flush
495 .word 0x00000000 @ old ARM ID
501 .word 0x41007000 @ ARM7/710
507 .word 0x41807200 @ ARM720T (writethrough)
513 .word 0x00007000 @ ARM7 IDs
519 @ Everything from here on will be the new ID system.
521 .word 0x4401a100 @ sa110 / sa1100
525 b __armv4_cache_flush
527 .word 0x6901b110 @ sa1110
531 b __armv4_cache_flush
533 @ These match on the architecture ID
535 .word 0x00020000 @ ARMv4T
539 b __armv4_cache_flush
541 .word 0x00050000 @ ARMv5TE
545 b __armv4_cache_flush
547 .word 0x00060000 @ ARMv5TEJ
551 b __armv4_cache_flush
553 .word 0x00070000 @ ARMv6
557 b __armv6_cache_flush
559 .word 0 @ unrecognised type
565 .size proc_types, . - proc_types
568 * Turn off the Cache and MMU. ARMv3 does not support
569 * reading the control register, but ARMv4 does.
571 * On entry, r6 = processor ID
572 * On exit, r0, r1, r2, r3, r12 corrupted
573 * This routine must preserve: r4, r6, r7
576 cache_off: mov r3, #12 @ cache_off function
580 mrc p15, 0, r0, c1, c0
582 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
584 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
585 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
589 mov r0, #0x00000030 @ ARM6 control reg.
593 mov r0, #0x00000070 @ ARM7 control reg.
597 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
599 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
600 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
604 * Clean and flush the cache to maintain consistency.
609 * r1, r2, r3, r11, r12 corrupted
610 * This routine must preserve:
620 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
621 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
622 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
623 mcr p15, 0, r1, c7, c10, 4 @ drain WB
627 mov r2, #64*1024 @ default: 32K dcache size (*2)
628 mov r11, #32 @ default: 32 byte line size
629 mrc p15, 0, r3, c0, c0, 1 @ read cache type
630 teq r3, r6 @ cache ID register present?
635 mov r2, r2, lsl r1 @ base dcache size *2
636 tst r3, #1 << 14 @ test M bit
637 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
641 mov r11, r11, lsl r3 @ cache line size in bytes
643 bic r1, pc, #63 @ align to longest cache line
645 1: ldr r3, [r1], r11 @ s/w flush D cache
649 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
650 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
651 mcr p15, 0, r1, c7, c10, 4 @ drain WB
656 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
660 * Various debugging routines for printing hex characters and
661 * memory, which again must be relocatable.
664 .type phexbuf,#object
666 .size phexbuf, . - phexbuf
668 phex: adr r3, phexbuf
705 2: mov r0, r11, lsl #2
713 ldr r0, [r12, r11, lsl #2]
734 .section ".stack", "w"
735 user_stack: .space 4096